CN104934291A - Method for processing abnormal wafer - Google Patents
Method for processing abnormal wafer Download PDFInfo
- Publication number
- CN104934291A CN104934291A CN201410105748.8A CN201410105748A CN104934291A CN 104934291 A CN104934291 A CN 104934291A CN 201410105748 A CN201410105748 A CN 201410105748A CN 104934291 A CN104934291 A CN 104934291A
- Authority
- CN
- China
- Prior art keywords
- polyimides
- abnormal wafer
- wafer
- abnormal
- etching
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31127—Etching organic layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31127—Etching organic layers
- H01L21/31133—Etching organic layers by chemical means
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31127—Etching organic layers
- H01L21/31133—Etching organic layers by chemical means
- H01L21/31138—Etching organic layers by chemical means by dry-etching
Abstract
The invention provides a method for processing an abnormal wafer. The method for processing the abnormal wafer at least includes a step of removing cured polyimide on the surface of the wafer, the step at least includes: providing an abnormal wafer having a protective area on which cured polyimide is formed; coating positive photoresist on the abnormal wafer and polyimide surface; performing exposure on the positive photoresist through a first masking plate, and exposing polyimide on the protective area after development; adopting an etching process to remove the exposed polyimide by etching; and removing the positive photoresist. The method for processing the abnormal wafer changes the way of removing polyimide from conventional cleaning into etching, can completely clean cured polyimide on the surface of the abnormal wafer; the positive photoresist achieves a blocking function in etching processing, thereby protecting the surface of a chip from being damaged, realizing reworking processing of the abnormal wafer with cured polyimide, and preventing the wafer from being scrapped; and the method provided by the invention does not need to modify a technological manufacture process and a machine structure, and is low in industrial cost.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, relate to a kind of method processing abnormal wafer, particularly relate to a kind of method removing the polyimides of abnormal wafer surface solidification.
Background technology
Polyimides (Polyimide) is widely used in microelectronics industry with its excellent performance, can be used as the passivation protection and inter-level dielectric etc. of all kinds of device in process industry.Polyimides, as the protective layer of microelectronic component, can shield a-particle, the soft error of abatement device, reduces environment to the impact of device, can improve the ability of microelectronic component anti-adverse environment.Polyimides or a kind of negative photoresist, itself not only plays photoresist but also be dielectric material, when preparing polyimide covercoat without the need to applying extra photoresist at polyimide surface, substantially reduces operation.
In integrated circuit fabrication process, can firmly be attached on device after polyimide curing is shaping, device is played a protective role; but; wafer, after tentatively having manufactured, usually can be found various abnormal conditions, such as occurs during test that electrical property exception, residual particles are too many etc.Once wafer occurs abnormal, then need to do over again process to abnormal wafer.
The first step of process of doing over again is removed by the protective layer polyimides of abnormal wafer surface, but the polyimides after solidification has the antiacid anticorrosive characteristic such as high temperature resistant, and and the adhesiveness of wafer good, the polyimides after causing curing molding is difficult to removal.Until current wafer abnormality processing remains the difficult problem of industry, wafer success rate of doing over again is very low, and scrappage reaches more than 95%, and enterprises' loss is serious, and cost increases substantially.
If find after polyimide curing in prior art that wafer can carry out by repeatedly cleaning polyimides process of doing over again extremely; but the wafer after doing over again still has large-area polyimides to remain; after carrying out repeatedly cleaning by force; polyimides on wafer is residual on a small quantity still can be accepted; but chip surface can be serious due to cleaning damage, and abnormal wafer still can be scrapped.
Therefore, the method providing the method for the abnormal wafer of a kind of process of improvement especially to remove polyimides is the problem that those skilled in the art need to solve.
Summary of the invention
The shortcoming of prior art in view of the above, the object of the present invention is to provide a kind of method processing abnormal wafer, removing not thoroughly for solving when the polyimides of abnormal wafer surface solidification is removed in cleaning in prior art, removing in polyimides process the problem damaged abnormal wafer surface and cause abnormal wafer scrap.
For achieving the above object and other relevant objects, the invention provides a kind of method processing abnormal wafer, the method for the abnormal wafer of described process at least comprises the step of the polyimides removing wafer surface solidification, and this step at least comprises:
The abnormal wafer with protection zone is provided, described protection zone is formed with the polyimides of solidification;
Described abnormal wafer and polyimide surface apply positive photoresist;
By the first mask plate, described positive photoresist is exposed, after development, expose the polyimides on described protection zone;
Etching technics etching is adopted to remove the polyimides of described exposure;
Remove described positive photoresist.
As a kind of prioritization scheme of the method for the abnormal wafer of process of the present invention, described abnormal wafer comprises Semiconductor substrate and is formed in the circuit structure of described semiconductor substrate surface.
As a kind of prioritization scheme of the method for the abnormal wafer of process of the present invention, the step that described protection zone is formed the polyimides of solidification comprises:
First, coating polyimide on described semiconductor substrate structure; Secondly, exposed described polyimides by the second mask plate, after development, described polyimides is formed on the protection zone of semiconductor substrate structure; Finally, baking-curing is carried out to the polyimides on protection zone.
As a kind of prioritization scheme of the method for the abnormal wafer of process of the present invention, described first mask plate and the second mask plate are same mask plate.
As a kind of prioritization scheme of the method for the abnormal wafer of process of the present invention, the thickness range of described polyimides is 10 ~ 90 μm.
As a kind of prioritization scheme of the method for the abnormal wafer of process of the present invention, the model of described positive photoresist is PFI58 or AR89.
As a kind of prioritization scheme of the method for the abnormal wafer of process of the present invention, dry method or wet-etching technology is adopted to etch described polyimides.
As a kind of prioritization scheme of the method for the abnormal wafer of process of the present invention, adopt wet-etching technology to etch described polyimides, etching liquid adopts hydrofluoric acid.
As a kind of prioritization scheme of the method for the abnormal wafer of process of the present invention, adopt dry etch process to etch described polyimides, the gas of etching adopts fluoro-gas.
As a kind of prioritization scheme of the method for the abnormal wafer of process of the present invention, described fluoro-gas is CF
4, CHF
3or C
3f
8.
As mentioned above, the method for the abnormal wafer of process of the present invention, comprise the step of the polyimides removing wafer surface solidification, this step at least comprises: provide the abnormal wafer with protection zone, described protection zone is formed with the polyimides of solidification; Described abnormal wafer and polyimide surface apply positive photoresist; By the first mask plate described positive photoresist exposed and develop, exposing the polyimides on described protection zone; Etching technics etching is adopted to remove the polyimides of described exposure; Remove described positive photoresist.The present invention changes by traditional cleaning the mode removing polyimides into etching, thoroughly can clean out the polyimides of abnormal wafer surface solidification; Positive photoresist plays barrier effect when etching processing, and protect IC surface is injury-free, thus realizes doing over again process to the abnormal wafer after polyimide curing, avoids wafer scrap; And the present invention does not need amendment manufacturing process and bench structure, industrial cost is low.
Accompanying drawing explanation
Fig. 1 is the process flow diagram of the method for the abnormal wafer of process of the present invention.
Fig. 2 ~ Fig. 4 is the structural representation forming the polyimides of solidification in the method for the abnormal wafer of process of the present invention.
Fig. 5 ~ Fig. 9 is the polyimides schematic diagram removing solidification in the method for the abnormal wafer of process of the present invention.
Element numbers explanation
1 abnormal wafer
11 Semiconductor substrate
12 circuit structures
2 polyimides
3 second mask plates
4 positive photoresists
5 first mask plates
Embodiment
Below by way of specific instantiation, embodiments of the present invention are described, those skilled in the art the content disclosed by this specification can understand other advantages of the present invention and effect easily.The present invention can also be implemented or be applied by embodiments different in addition, and the every details in this specification also can based on different viewpoints and application, carries out various modification or change not deviating under spirit of the present invention.
Refer to accompanying drawing.It should be noted that, the diagram provided in the present embodiment only illustrates basic conception of the present invention in a schematic way, then only the assembly relevant with the present invention is shown in graphic but not component count, shape and size when implementing according to reality is drawn, it is actual when implementing, and the kenel of each assembly, quantity and ratio can be a kind of change arbitrarily, and its assembly layout kenel also may be more complicated.
The invention provides a kind of method processing abnormal wafer, as shown in Figure 1, the method for the abnormal wafer of described process comprises the step of the polyimides removing wafer surface solidification, and this step at least comprises:
First, the abnormal wafer with protection zone is provided, described protection zone is formed with the polyimides of solidification;
Secondly, described abnormal wafer and polyimide surface apply positive photoresist;
Then, by the first mask plate, described positive photoresist is exposed, after development, expose the polyimides on described protection zone;
Then, etching technics etching is adopted to remove the polyimides of described exposure;
Finally, described positive photoresist is removed.
The method of the abnormal wafer of process of the present invention is specifically described below in conjunction with accompanying drawing.
First perform step one, ask Shenfu Fig. 4, the abnormal wafer 1 with protection zone is provided, described protection zone is formed with the polyimides 2 of solidification.
Described abnormal wafer 1 comprises Semiconductor substrate 11 and is formed in the circuit structure 12 on described Semiconductor substrate 11 surface.Wherein, described Semiconductor substrate 11 can be silicon substrate or silicon-on-insulator (SOI), and in the present embodiment, described Semiconductor substrate 11 is preferably silicon substrate.Described circuit structure 12 is subsequent growth structures with certain device function on described silicon substrate 11, such as, includes source electrode, drain electrode, grid and metal interconnecting wires etc. in circuit structure.According to the needs of actual wafer, some circuit structure needs to make polyimides 2 on its surface and protects, and needs those circuit structures of protection to be defined as protection zone.
Refer to Fig. 2 ~ Fig. 4, the step that described protection zone is formed polyimides 2 is specially:
First at described abnormal wafer 1 coating polyimide 2, as shown in Figure 2, described polyimides 2 covers the surface of whole wafer 1; Then by the second mask plate 3, described polyimides 2 is exposed, as shown in Figure 3; Because described polyimides 2 itself is as a kind of negative photoresist, therefore, the polyimides 2 be exposed can not be dissolved by the developing, and the described polyimides 2 after development is formed on the protection zone of abnormal wafer 1, as shown in Figure 4; Finally, carry out baking make it solidification to the polyimides 2 on protection zone, the polyimides 2 after solidification has very strong adhesiveness with wafer, can realize the protection to circuit structure.
It should be noted that, described polyimides 2 itself can, as a kind of negative photoresist, therefore, not need extra photoresist just directly can carry out patterning to polyimides 2 when protection zone makes polyimides 2, reduces operation, cost-saving.
The thickness of the polyimides 2 that described protection zone is formed is within the scope of 10 ~ 90 μm, and in the present embodiment, this thickness can be 60 μm.
Next performs step 2, and described abnormal wafer and polyimide surface apply positive photoresist.
The abnormal wafer 1 that surface has formed polyimides 2 protective layer is being detected extremely by various detection means by technical staff, and need to carry out process of doing over again, the polyimides 2 being about to be cured is removed, to repair the internal structure of abnormal wafer 1.
Particularly, adopt the mode of spin coating to apply positive photoresist 4 on the surface at described abnormal wafer 1 and polyimides 2, the structure after spin coating positive photoresist 4 as shown in Figure 5.The model of the positive photoresist 4 of spin coating can be PFI58 or AR89.In the present embodiment, employing model is AR89.Positive photoresist 4.
Then perform step 3, by the first mask plate, described positive photoresist is exposed, after development, expose the polyimides on described protection zone.
Refer to accompanying drawing 6 and accompanying drawing 7, the first mask plate 5 adopted in this step can be same mask plate with the second mask plate 3 in step one, as shown in Figure 6.By this mask plate, the positive photoresist 4 on described abnormal wafer 1 protection zone is exposed, the positive photoresist 4 of exposure is removed after developing solution dissolution, thus exposes the polyimides 2 on protection zone, for the polyimides 2 on subsequent etching protection zone is prepared.
Then perform step 4, adopt etching technics etching to remove the polyimides of described exposure.
The positive photoresist 2 be not dissolved by the developing in above-mentioned steps three covers the region beyond abnormal wafer 1 protection zone; carrying out playing barrier effect when polyimides 2 etches; etching technics can be avoided the damage of wafer surface, be conducive to keeping wafer surface characteristics.
Dry etching or wet-etching technology can be adopted to etch and to remove described polyimides 2.
In one embodiment, adopt wet-etching technology to etch described polyimides 2, the etching liquid of employing is hydrofluoric acid, and etch period is within the scope of tens seconds.Particularly, described etching technics adopts the hydrofluoric acid of dilution as wet etching solution, and the concentration range of described hydrofluoric acid solution is 45:1 ~ 55:1; The temperature of carrying out etching is within the scope of 20 ~ 30 DEG C; The time of wet etching is within the scope of 8 ~ 15 seconds.More specifically, the concentration of described hydrofluoric acid solution is preferably 50:1; The temperature of etching is preferably 23 DEG C; The time of etching is preferably 10 seconds.
In another embodiment, adopt dry etch process to etch described polyimides 2, particularly, described in be dry-etched in etching reaction chamber and carry out, adopt etching gas to be fluorine-containing gas, described fluoro-gas can be CF
4or CHF
3or C
3f
8.The range of flow of described etching gas is 50 ~ 100sccm, and the time of carrying out dry etching is about tens seconds.More specifically, the flow of described etching gas is preferably 80sccm.
Also it should be noted that, after described etching technics, need to carry out cleaning step to described abnormal wafer 1, the concrete deionized water that adopts rinses described abnormal wafer 1, and the time of flushing is 5 ~ 10 minutes, then dries described abnormal wafer 1.
Etching removes the structure after the polyimides 2 of protection zone as shown in Figure 8.
Finally perform step 5, remove described positive photoresist.
Described positive photoresist 4 can be removed by the method for ashing or chemistry.In the present embodiment, cineration technics is adopted to remove described positive photoresist 4, as shown in Figure 9.
In sum, the invention provides a kind of method processing abnormal wafer, the method comprises the step of the polyimides removing wafer surface solidification, at least comprises: provide the abnormal wafer with protection zone, described protection zone is formed with the polyimides of solidification; Described abnormal wafer and polyimide surface apply positive photoresist; By the first mask plate described positive photoresist exposed and develop, exposing the polyimides on described protection zone; Etching technics etching is adopted to remove the polyimides of described exposure; Remove described positive photoresist.The present invention changes by traditional cleaning the mode removing polyimides into etching, thoroughly can clean out the polyimides of abnormal wafer surface solidification; Positive photoresist plays barrier effect when etching processing, and protect IC surface is injury-free, thus realizes doing over again process to the abnormal wafer after polyimide curing, avoids wafer scrap; And the present invention does not need amendment manufacturing process and bench structure, industrial cost is low.
So the present invention effectively overcomes various shortcoming of the prior art and tool high industrial utilization.
Above-described embodiment is illustrative principle of the present invention and effect thereof only, but not for limiting the present invention.Any person skilled in the art scholar all without prejudice under spirit of the present invention and category, can modify above-described embodiment or changes.Therefore, such as have in art usually know the knowledgeable do not depart from complete under disclosed spirit and technological thought all equivalence modify or change, must be contained by claim of the present invention.
Claims (10)
1. process a method for abnormal wafer, it is characterized in that, the method for the abnormal wafer of described process at least comprises the step of the polyimides removing wafer surface solidification, and this step at least comprises:
The abnormal wafer with protection zone is provided, described protection zone is formed with the polyimides of solidification;
Described abnormal wafer and polyimide surface apply positive photoresist;
By the first mask plate, described positive photoresist is exposed, after development, expose the polyimides on described protection zone;
Etching technics etching is adopted to remove the polyimides of described exposure;
Remove described positive photoresist.
2. the method for the abnormal wafer of process according to claim 1, is characterized in that: described abnormal wafer comprises Semiconductor substrate and is formed in the circuit structure of described semiconductor substrate surface.
3. the method for the abnormal wafer of process according to claim 1, is characterized in that: the step forming the polyimides of solidification on described protection zone comprises:
First, at the surface application polyimides of described abnormal wafer; Secondly, exposed described polyimides by the second mask plate, after development, described polyimides is formed on the protection zone of abnormal wafer; Finally, baking-curing is carried out to the polyimides on protection zone.
4. the method for the abnormal wafer of process according to claim 3, is characterized in that: described first mask plate and the second mask plate are same mask plate.
5. the method for the abnormal wafer of process according to claim 1, is characterized in that: the thickness range of described polyimides is 10 ~ 90 μm.
6. the method for the abnormal wafer of process according to claim 1, is characterized in that: the model of described positive photoresist is PFI58 or AR89.
7. the method for the abnormal wafer of process according to claim 1, is characterized in that: adopt dry method or wet-etching technology to etch described polyimides.
8. the method for the abnormal wafer of process according to claim 7, is characterized in that: adopt wet-etching technology to etch described polyimides, etching liquid adopts hydrofluoric acid.
9. the method for the abnormal wafer of process according to claim 7, is characterized in that: adopt dry etch process to etch described polyimides, and the gas of etching adopts fluoro-gas.
10. the method for the abnormal wafer of process according to claim 9, is characterized in that: described fluoro-gas is CF
4, CHF
3or C
3f
8.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410105748.8A CN104934291B (en) | 2014-03-20 | 2014-03-20 | A kind of method for handling abnormal chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410105748.8A CN104934291B (en) | 2014-03-20 | 2014-03-20 | A kind of method for handling abnormal chip |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN104934291A true CN104934291A (en) | 2015-09-23 |
| CN104934291B CN104934291B (en) | 2018-05-04 |
Family
ID=54121408
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201410105748.8A Active CN104934291B (en) | 2014-03-20 | 2014-03-20 | A kind of method for handling abnormal chip |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN104934291B (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106128939A (en) * | 2016-08-01 | 2016-11-16 | 上海华虹宏力半导体制造有限公司 | The method processing abnormal MIM capacitor dielectric layer |
| CN107768232A (en) * | 2016-08-23 | 2018-03-06 | 中芯国际集成电路制造(上海)有限公司 | The minimizing technology of the protective layer of device surface |
| CN107919267A (en) * | 2016-10-10 | 2018-04-17 | 中芯国际集成电路制造(上海)有限公司 | A kind of semiconductor devices and preparation method thereof |
| CN108321085A (en) * | 2017-01-17 | 2018-07-24 | 中芯国际集成电路制造(上海)有限公司 | A kind of minimizing technology of polyimide layer and the production method of semiconductor devices |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6664200B1 (en) * | 2000-04-28 | 2003-12-16 | Motorola Inc | Method of manufacturing a semiconductor component and polyimide etchant therefor |
| CN1956284A (en) * | 2005-10-29 | 2007-05-02 | 深圳飞通光电子技术有限公司 | Ridge waveguide type semiconductor laser and its manufacturing method |
| CN101192506A (en) * | 2006-11-20 | 2008-06-04 | 中芯国际集成电路制造(上海)有限公司 | Device and method for removing chip outer protective layer |
| CN101419933A (en) * | 2007-10-24 | 2009-04-29 | 中芯国际集成电路制造(上海)有限公司 | Protection layer making method capable of avoiding projection generation |
| CN102931145A (en) * | 2011-08-09 | 2013-02-13 | 中芯国际集成电路制造(上海)有限公司 | Method for forming pad structure |
-
2014
- 2014-03-20 CN CN201410105748.8A patent/CN104934291B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6664200B1 (en) * | 2000-04-28 | 2003-12-16 | Motorola Inc | Method of manufacturing a semiconductor component and polyimide etchant therefor |
| CN1956284A (en) * | 2005-10-29 | 2007-05-02 | 深圳飞通光电子技术有限公司 | Ridge waveguide type semiconductor laser and its manufacturing method |
| CN101192506A (en) * | 2006-11-20 | 2008-06-04 | 中芯国际集成电路制造(上海)有限公司 | Device and method for removing chip outer protective layer |
| CN101419933A (en) * | 2007-10-24 | 2009-04-29 | 中芯国际集成电路制造(上海)有限公司 | Protection layer making method capable of avoiding projection generation |
| CN102931145A (en) * | 2011-08-09 | 2013-02-13 | 中芯国际集成电路制造(上海)有限公司 | Method for forming pad structure |
Non-Patent Citations (2)
| Title |
|---|
| 罗萍，张为: "《集成电路设计导论》", 31 May 2010 * |
| 董拴成等: "聚酰亚胺微刻蚀加工工艺研究", 《微纳电子技术》 * |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106128939A (en) * | 2016-08-01 | 2016-11-16 | 上海华虹宏力半导体制造有限公司 | The method processing abnormal MIM capacitor dielectric layer |
| CN107768232A (en) * | 2016-08-23 | 2018-03-06 | 中芯国际集成电路制造(上海)有限公司 | The minimizing technology of the protective layer of device surface |
| CN107768232B (en) * | 2016-08-23 | 2020-03-13 | 中芯国际集成电路制造(上海)有限公司 | Method for removing protective layer on surface of device |
| CN107919267A (en) * | 2016-10-10 | 2018-04-17 | 中芯国际集成电路制造(上海)有限公司 | A kind of semiconductor devices and preparation method thereof |
| CN108321085A (en) * | 2017-01-17 | 2018-07-24 | 中芯国际集成电路制造(上海)有限公司 | A kind of minimizing technology of polyimide layer and the production method of semiconductor devices |
| CN108321085B (en) * | 2017-01-17 | 2021-04-23 | 中芯国际集成电路制造(上海)有限公司 | Method for removing polyimide layer and method for manufacturing semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| CN104934291B (en) | 2018-05-04 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN105280473A (en) | Method of reducing residual contamination in singulated semiconductor die | |
| CN104934291A (en) | Method for processing abnormal wafer | |
| CN103151245B (en) | Film patterning method | |
| TWI525673B (en) | Method of fabricating a wafer-level chip package | |
| JP2006135287A (en) | Cleaning solution and cleaning method of semiconductor device using the same | |
| CN105573068B (en) | The reworking method of photoresist minimizing technology and photoetching process | |
| US20200168464A1 (en) | Method for removing a sacrificial layer on semiconductor wafers | |
| JP2016040795A (en) | Method for dividing wafer | |
| US20180019284A1 (en) | Method of optimizing an interface for processing of an organic semiconductor | |
| CN104752233A (en) | Welding pad manufacturing method | |
| CN104425216A (en) | Method for photo-etching semiconductor substrate having trench | |
| CN103996626B (en) | The reworking method of fairlead | |
| JP6305269B2 (en) | Processing method | |
| US20090042388A1 (en) | Method of cleaning a semiconductor substrate | |
| CN107785307B (en) | Method for manufacturing titanium nitride pattern with step shape | |
| CN105253854A (en) | Method for protecting metal electrode during SOI MEMS sacrificial layer etching | |
| CN112201615B (en) | Method for manufacturing bonding pad of semiconductor device and method for manufacturing semiconductor device | |
| CN106298442B (en) | Method for removing residue | |
| CN114895531B (en) | Method for cleaning a substrate for a lithographic process | |
| CN203941899U (en) | A kind of semiconductor structure | |
| CN106449501B (en) | Method for improving flatness of back surface of epitaxial wafer and epitaxial wafer | |
| TW201417163A (en) | Wafer edge trimming method | |
| TWI792260B (en) | Method for manufacturing semiconductor element using metal lift-off process and semiconductor element made therefrom | |
| KR100884980B1 (en) | Manufacturing method of semiconductor device | |
| KR100598287B1 (en) | Method for cleaning the semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |