CN104917494B - A kind of function signal generator - Google Patents
A kind of function signal generator Download PDFInfo
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- CN104917494B CN104917494B CN201510234339.2A CN201510234339A CN104917494B CN 104917494 B CN104917494 B CN 104917494B CN 201510234339 A CN201510234339 A CN 201510234339A CN 104917494 B CN104917494 B CN 104917494B
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Abstract
This application discloses a kind of function signal generator, including phase accumulator, the frequency control word for being inputted according to user carries out phase-accumulated under the effect of the first clock；Waveform inquiry table, for stored waveform data and inquires about table address according to waveform and exports corresponding Wave data；Digital analog converter, for Wave data to be converted into waveform signal under the effect of the first clock；Low pass filter, for filtering out glitch noise to waveform signal and exporting；Also include clock conversion module, table address is inquired about for producing adjustable virtual sampling clock according to phase accumulator, and the waveform being produced under the effect of virtual sampling clock.In the embodiment of the application, table address is inquired about due to adjustable virtual sampling clock including clock conversion module, can be produced by phase accumulator, and waveform is produced under the effect of virtual sampling clock.The application changes function signal generator sample rate by PLD, occurs chip without using clock.
Description
Technical field
The application is related to electronic instrument, more particularly to a kind of function signal generator.
Background technology
As shown in figure 1, existing function signal generator includes phase accumulator, phase register, waveform inquiry table, number
Weighted-voltage D/A converter and low pass filter.The frequency control word that phase accumulator is used to be inputted according to user enters under the effect of the first clock
Line phase is added up, and accumulation result is sent into phase register；Phase register, under the effect of the first clock according to tired
Plus result, obtain waveform inquiry table address；Waveform inquiry table, corresponding waveform number is exported for inquiring about table address according to waveform
According to.
There is the function signal generator of variable sampling rate at present, it is most of to occur chip using clock, during by configuring
Clock chip changes sample rate.
The content of the invention
The application technical problem to be solved is that there is provided a kind of function signal generator in view of the shortcomings of the prior art.
The application technical problem to be solved is solved by the following technical programs：
A kind of function signal generator, including phase accumulator, waveform inquiry table, digital analog converter and low pass filter；
The phase accumulator, the frequency control word for being inputted according to user enters line phase under the effect of the first clock and tired out
Plus；
The waveform inquiry table, for stored waveform data and inquires about table address according to waveform and exports corresponding waveform number
According to；
The digital analog converter, for the Wave data to be converted into waveform signal under first clock effect；
The low pass filter, for filtering out glitch noise to the waveform signal and exporting；
Also include clock conversion module, for making the phase accumulator produce adjustable void by PLD
Intend sampling clock, and the waveform inquiry table address is produced under the virtual sampling clock effect.
Above-mentioned function signal generator, the waveform inquiry table address is obtained under the virtual sampling clock effect, is made
The waveform lookup table data is exported one by one.
Above-mentioned function signal generator, the waveform inquiry table address is obtained especially by cumulative 1 mode.
Above-mentioned function signal generator, when the phase accumulator is added to maximum, produces the virtual sampling clock
Enable signal, the size of the virtual sampling clock is according to the frequency control word, phase accumulator width and described first
Clock is designed.
Above-mentioned function signal generator, the calculation formula of the virtual sampling clock is：
Wherein, FvarFor virtual sampling clock, FTW is frequency control word, and N is phase accumulator width, when Fs is first
Clock.
Above-mentioned function signal generator, the calculation formula of the output signal frequency of the function signal generator is：
Wherein, FoutFor output signal frequency, L is waveform table length.
The calculation formula of the virtual sampling clock resolution ratio of above-mentioned function signal generator is：
Wherein, F0For virtual sampling clock resolution ratio.
As a result of above technical scheme, it is the beneficial effect that the application possesses：
(1) in the embodiment of the application, due to that including clock conversion module, can be produced by phase accumulator
Adjustable virtual sampling clock, and the generation waveform inquiry table address under the effect of virtual sampling clock.The application passes through programmable
Logical device changes function signal generator sample rate, occurs chip without using clock, portable high, cost is low.
(2) in the embodiment of the application, because waveform inquiry table address is obtained under the effect of virtual sampling clock
Take, waveform is inquired about table address and obtained especially by cumulative 1 mode, waveform lookup table data is exported one by one, it is no to repeat or jump
Waveform table data is crossed, it is undistorted during output random waveform.
(3) in the embodiment of the application, because virtual sampling clock resolution ratio is the first clock and 2NRatio
Value, N is phase accumulator width, can make the value very little of virtual sampling clock resolution ratio by adjusting N.
Brief description of the drawings
Fig. 1 is the high-level schematic functional block diagram of existing function signal generator；
Fig. 2 is the high-level schematic functional block diagram of the application function signal generator in one embodiment；
Fig. 3 is the application phase accumulator accumulation result and virtual sampling clock matching relationship schematic diagram.
Embodiment
The application is described in further detail below by embodiment combination accompanying drawing.
As shown in Fig. 2 the function signal generator of the application, a kind of its embodiment, including phase accumulator, clock turn
Change module, waveform inquiry table, digital analog converter and low pass filter.Phase accumulator, for the frequency control inputted according to user
Word processed carries out phase-accumulated under the effect of the first clock.Clock conversion module, for tiring out phase by PLD
Plus device produces adjustable virtual sampling clock, and the generation waveform inquiry table address under the effect of virtual sampling clock.Waveform is inquired about
Table, for stored waveform data and inquires about table address according to waveform and exports corresponding Wave data.Digital analog converter, for
Wave data is converted into waveform signal under the effect of one clock.Low pass filter, for waveform signal to be filtered out after glitch noise
Output.In one embodiment, the first clock of the application can be system clock, and each several part of function signal generator is equal
It can be realized by PLD.
Waveform is inquired about table address and obtained under the effect of virtual sampling clock, waveform lookup table data is exported one by one.Waveform
Inquiry table address can specifically be obtained by way of cumulative 1.The initial address of waveform inquiry table can be preset by user.Waveform is looked into
Asking table address can also be obtained by other digital modes that add up, as long as making waveform lookup table data export one by one.
As shown in figure 3, when phase accumulator is added to maximum, producing the enable signal of virtual sampling clock, virtually adopting
The size of sample clock is designed according to frequency control word, phase accumulator width and the first clock.Phase accumulator it is instantaneous
Value, by 0 to 2N-1, digital quantity is represented, whenever accumulator is more than maximum 2N-1When, accumulator will produce spill over, also
It is to generate adjustable sampling clock FvarSignal is enabled, accumulator is weighed afterwards and is further continued for adding up.In one embodiment, virtually
The calculation formula of sampling clock is：
Wherein, FvarFor virtual sampling clock, FTW is frequency control word, and N is phase accumulator width, when Fs is first
Clock.
The calculation formula of the output signal frequency of function signal generator is：
Wherein, FoutFor the output signal frequency of function signal generator output end, FTW is frequency control word, and N is phase
Accumulator width, Fs is the first clock, and L is waveform table length.
The calculation formula of the virtual sampling clock resolution ratio of function signal generator is：
Wherein, F0For virtual sampling clock resolution ratio, Fs is the first clock, and N is phase accumulator width.
In one embodiment, the function signal generator of the application can be specifically carrier by PLD
Realized.
If phase accumulator bit wide 4bit, FTW are 3, thenIf waveform table length L is 4, then defeated
The frequency gone outIf Fs is 100MHz, then Fout=4.6875MHz.
When phase accumulator bit wide N is 4bit, virtual sampling clock resolution ratioAnd when N is
During 48bit, virtual sampling clock resolution ratioThe feelings that i.e. the application can be fixed in waveform table length
The signal of wide range of frequencies is exported under condition, and virtual sampling clock resolution ratio can be with very little.
Above content is to combine the further description that specific embodiment is made to the application, it is impossible to assert this Shen
Specific implementation please is confined to these explanations.For the application person of an ordinary skill in the technical field, do not taking off
On the premise of from the application design, some simple deduction or replace can also be made.
Claims (6)
1. a kind of function signal generator, including phase accumulator, waveform inquiry table, digital analog converter and low pass filter；
The phase accumulator, the frequency control word for being inputted according to user carries out phase-accumulated under the effect of the first clock；
The waveform inquiry table, for stored waveform data and inquires about table address according to waveform and exports corresponding Wave data；
The digital analog converter, for the Wave data to be converted into waveform signal under first clock effect；
The low pass filter, for filtering out glitch noise to the waveform signal and exporting；
Characterized in that, also including clock conversion module, for producing the phase accumulator by PLD
Adjustable virtual sampling clock, and produce the waveform inquiry table address under the virtual sampling clock effect；
The calculation formula of the output signal frequency of the function signal generator is：
<mrow>
<msub>
<mi>F</mi>
<mrow>
<mi>o</mi>
<mi>u</mi>
<mi>t</mi>
</mrow>
</msub>
<mo>=</mo>
<mfrac>
<mrow>
<mi>F</mi>
<mi>T</mi>
<mi>W</mi>
</mrow>
<msup>
<mn>2</mn>
<mi>N</mi>
</msup>
</mfrac>
<mo>&times;</mo>
<mfrac>
<msub>
<mi>F</mi>
<mi>s</mi>
</msub>
<mi>L</mi>
</mfrac>
</mrow>
Wherein, FoutFor output signal frequency, L is waveform table length, and FTW is frequency control word, and N is phase accumulator width, Fs
For the first clock.
2. function signal generator as claimed in claim 1, it is characterised in that the waveform inquiry table address is described virtual
Sampling clock effect is lower to be obtained, and the waveform lookup table data is exported one by one.
3. function signal generator as claimed in claim 2, it is characterised in that the waveform inquiry table address is especially by tired
The mode for plus 1 is obtained.
4. function signal generator as claimed in claim 1, it is characterised in that the phase accumulator is added to maximum
When, the enable signal of the virtual sampling clock is produced, the size of the virtual sampling clock is according to the frequency control word, phase
Bit accumulator width and first clock are designed.
5. function signal generator as claimed in claim 4, it is characterised in that the calculation formula of the virtual sampling clock
For：
<mrow>
<msub>
<mi>F</mi>
<mi>var</mi>
</msub>
<mo>=</mo>
<mfrac>
<mrow>
<mi>F</mi>
<mi>T</mi>
<mi>W</mi>
</mrow>
<msup>
<mn>2</mn>
<mi>N</mi>
</msup>
</mfrac>
<mo>&times;</mo>
<msub>
<mi>F</mi>
<mi>s</mi>
</msub>
</mrow>
Wherein, FvarFor virtual sampling clock.
6. function signal generator as claimed in claim 5, it is characterised in that the virtual sampling of the function signal generator
The calculation formula of clock resolution is：
<mrow>
<msub>
<mi>F</mi>
<mn>0</mn>
</msub>
<mo>=</mo>
<mfrac>
<msub>
<mi>F</mi>
<mi>s</mi>
</msub>
<msup>
<mn>2</mn>
<mi>N</mi>
</msup>
</mfrac>
</mrow>
Wherein, F0For virtual sampling clock resolution ratio.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN201510234339.2A CN104917494B (en) | 2015-05-08 | 2015-05-08 | A kind of function signal generator |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510234339.2A CN104917494B (en) | 2015-05-08 | 2015-05-08 | A kind of function signal generator |
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| CN104917494A CN104917494A (en) | 2015-09-16 |
| CN104917494B true CN104917494B (en) | 2017-10-31 |
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Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105262459A (en) * | 2015-10-15 | 2016-01-20 | 深圳市鼎阳科技有限公司 | DDS random waveform generator with interpolation structure and a method thereof |
| CN108572266B (en) * | 2017-12-11 | 2020-09-15 | 深圳市鼎阳科技股份有限公司 | Waveform generating device |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7284025B2 (en) * | 2003-12-18 | 2007-10-16 | Tektronix, Inc. | DDS pulse generator architecture |
| CN102468868A (en) * | 2010-11-03 | 2012-05-23 | 北京普源精电科技有限公司 | DDS signal generator and frequency hopping method |
| CN102497205A (en) * | 2011-11-28 | 2012-06-13 | 杭州电子科技大学 | Improved DDS signal generator and signal generating method |
-
2015
- 2015-05-08 CN CN201510234339.2A patent/CN104917494B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7284025B2 (en) * | 2003-12-18 | 2007-10-16 | Tektronix, Inc. | DDS pulse generator architecture |
| CN102468868A (en) * | 2010-11-03 | 2012-05-23 | 北京普源精电科技有限公司 | DDS signal generator and frequency hopping method |
| CN102497205A (en) * | 2011-11-28 | 2012-06-13 | 杭州电子科技大学 | Improved DDS signal generator and signal generating method |
Non-Patent Citations (1)
| Title |
|---|
| "任意波发生器的研究与设计";铁奎等;《电子设计工程》;20120730;第20卷(第14期);第53页左栏第一段至第54页右栏最后一段 * |
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Address after: 518000 Guangdong Province, Baoan District, Baoan District, Xin'an Street, Xingdong Community, 68 District, Antongda Industrial Factory Area, 4 factories, 3 floors, 5 office buildings, 1-3 floors Patentee after: Shenzhen dingyang Technology Co., Ltd Address before: Shenzhen City, Guangdong province Baoan District 518000 District 68 road left three Antongda Industrial Park, 4 floor Patentee before: Shenzhen Siglent Technologies Co., Ltd. |
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