CN104915301B - A kind of plug-in RAM Interface data access system based on 8051 single-chip microcomputers - Google Patents
A kind of plug-in RAM Interface data access system based on 8051 single-chip microcomputers Download PDFInfo
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- CN104915301B CN104915301B CN201510291300.4A CN201510291300A CN104915301B CN 104915301 B CN104915301 B CN 104915301B CN 201510291300 A CN201510291300 A CN 201510291300A CN 104915301 B CN104915301 B CN 104915301B
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- 230000005540 biological transmission Effects 0.000 claims description 3
- 230000009286 beneficial effect Effects 0.000 description 2
- 230000000630 rising effect Effects 0.000 description 2
- 230000007547 defect Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- 239000004575 stone Substances 0.000 description 1
Classifications
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
- G06F13/161—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement
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Abstract
The present invention is more particularly directed to a kind of plug-in RAM Interface data access system based on 8051 single-chip microcomputers.The plug-in RAM Interface data access system based on 8051 single-chip microcomputers, including 8051 single-chip microcomputers, Wishbone master modules, fifo module, register module, RAM module, interruption control module and external equipment；8051 single-chip microcomputer, fifo module, register module and RAM module are connected to Wishbone master modules, and the fifo module and register module are connected by interruption control module with 8051 single-chip microcomputers.The plug-in RAM Interface data access system based on 8051 single-chip microcomputers, can correctly read and write the register of different submodules by plug-in RAM Interface, FIFO, RAM etc., can compatible different read latches submodule；In addition, present invention also adds temporary register, using twi-read order and the method for interruption delay so that 8051 single-chip microcomputers can correctly read the data of each submodule, the present invention has the characteristics that read latch compatibility is strong, is easy to implement, and has broad application prospects.
Description
Technical field
The present invention relates to single chip application technical field, more particularly to a kind of plug-in RAM Interface based on 8051 single-chip microcomputers
Data access system.
Background technology
Wishbone buses complete interconnection by establishing a general-purpose interface between IP kernel, can be used in soft core, admittedly
Interconnected between core and stone.For other IP kernel interface specifications, Wishbone interface specifications have it is simple,
Open, be efficient, beneficial to the features such as realization and completely free.Connect based on above-mentioned advantage, therefore using Wishbone buses
Mouth design.However, when Wishbone buses are as 8051 SCM system bus protocol, 8051 single-chip microcomputer GPIO quantity is not
It is enough.
Reading order of 8051 single-chip microcomputers to sub- module data, it is desirable in this rising edge clock or next of single-chip microcomputer order
Individual rising edge clock reads back data, so when read operation order is sent, it is desirable to which the data of reading are already prepared to.Outside
Portion's equipment can cause the data variation of fifo module and register module, be interrupted so as to produce, and 8051 single-chip microcomputers, which perform, interrupts journey
Sequence, the new data of submodule is read out, but it is that may all occur any time to interrupt, and may interrupt 8051 monolithics
The original read operation order of machine, after causing interrupt routine to be finished, the read operation order being interrupted can not be performed correctly.
It is inadequate for 8051 single-chip microcomputer GPIO quantity, and interrupt and cause single-chip microcomputer can not correctly perform read operation order
The problems such as, the present invention proposes a kind of plug-in RAM Interface data access system based on 8051 single-chip microcomputers.It is intended to compatible different readings
The submodule of delay is taken, and ensures that 8051 single-chip microcomputers can correctly read the data of each submodule.
The content of the invention
The defects of present invention is in order to make up prior art, there is provided a kind of compatibility it is strong based on the plug-in of 8051 single-chip microcomputers
RAM Interface data access system.
The present invention is achieved through the following technical solutions：
A kind of plug-in RAM Interface data access system based on 8051 single-chip microcomputers, it is characterised in that：Including 8051 monolithics
Machine, Wishbone master modules, fifo module, register module, RAM module, interruption control module and external equipment；Will
Interface of the plug-in RAM Interface of 8051 single-chip microcomputer as Wishbone bus protocols, 8051 single-chip microcomputer are connected to
Wishbone master modules, the fifo module, register module and RAM module are connected to by Wishbone buses
Wishbone master modules, it is also associated with postponing control between the Wishbone master modules and Wishbone buses
Module, the external equipment are connected to fifo module and register module, and the fifo module and register module pass through interruption
Control module is connected with 8051 single-chip microcomputers.
The fifo module, register module and RAM module unified distribution Wishbone base address, the register module
Multiple offset address are distributed with RAM module.
The fifo module, register module and RAM module further respectively have a temporary register, store respectively from
The data that fifo module, register module and RAM module are read.
The temporary register unified distribution Wishbone base address of the fifo module, register module and RAM module.
The access method of plug-in RAM Interface data access system of the invention based on 8051 single-chip microcomputers, it is characterised in that：Institute
State Wishbone master modules and the address of 8051 single-chip microcomputers, data and read-write enable signal are converted into standard
Wishbone bus signals, and pass through Wishbone bus access fifo modules, register module, RAM module and FIFO moulds
The temporary register of block, register module and RAM module three respectively；External equipment causes fifo module and register module
Data variation, when producing interruption, interrupt signal is deferred to 8051 single-chip microcomputers by interruption control module, right again at the end of read command pair
8051 single-chip microcomputers are interrupted, and it is implemented as：
8051 single-chip microcomputer sends the address read operation life of fifo module, register module and any module of RAM module
Respective modules are made, after certain delay, respective modules data are read into corresponding temporary register；8051 monolithic afterwards
Temporary register address read operation order corresponding to machine transmission, the data of corresponding temporary register are read in into 8051 single-chip microcomputers；
Now, interrupt signal is interrupted to 8051 single-chip microcomputers again.
The beneficial effects of the invention are as follows：The plug-in RAM Interface data access system based on 8051 single-chip microcomputers, by plug-in
RAM Interface can correctly read and write the register of different submodules, FIFO, RAM etc., can compatible different read latches submodule
Block；In addition, present invention also adds temporary register, using twi-read order and the method for interruption delay so that 8051 is single
Piece machine can correctly read the data of each submodule, and the present invention has the characteristics that read latch compatibility is strong, is easy to implement, has
Have broad application prospects.
Brief description of the drawings
Accompanying drawing 1 is illustrated for plug-in RAM Interface data access system logic module structure of the present invention based on 8051 single-chip microcomputers
Figure.
Embodiment
The present invention is described in detail below in conjunction with the accompanying drawings.
The plug-in RAM Interface data access system based on 8051 single-chip microcomputers, including 8051 single-chip microcomputers, Wishbone
Master modules, fifo module, register module, RAM module, interruption control module and external equipment；By 8051 monolithic
Interface of the plug-in RAM Interface of machine as Wishbone bus protocols, 8051 single-chip microcomputer are connected to Wishbone master moulds
Block, the fifo module, register module and RAM module are connected to Wishbone master modules by Wishbone buses,
It is also associated with postponing control module between the Wishbone master modules and Wishbone buses, the external equipment connects
Fifo module and register module are connected to, the fifo module and register module pass through interruption control module and 8051 single-chip microcomputers
It is connected.
The fifo module, register module and RAM module unified distribution Wishbone base address are 16 ' h1000,16 '
H2000,16 ' h3000, the register module and RAM module distribute multiple offset address.
Because the same data of fifo module can only be read once, the fifo module, register module and RAM module are also
A temporary register is respectively equipped with, stores the data read from fifo module, register module and RAM module respectively.
The temporary register unified distribution Wishbone base address of the fifo module, register module and RAM module is
16 ' h4000,16 ' h4001,16 ' h4002.
The access method of the plug-in RAM Interface data access system based on 8051 single-chip microcomputers, the Wishbone
Master modules are converted to the address of 8051 single-chip microcomputers, data and read-write enable signal the Wishbone bus signals of standard,
And pass through Wishbone bus access fifo modules, register module, RAM module and fifo module, register module and RAM
The temporary register of module three respectively；External equipment causes the data variation of fifo module and register module, produces interruption
When, during interruption control module is carried out to 8051 single-chip microcomputers again at the end of interrupt signal is deferred into 8051 single-chip microcomputer read commands pair
It is disconnected.
8051 single-chip microcomputer sends the address read operation life of fifo module, register module and any module of RAM module
Respective modules are made, after certain delay, respective modules data are read into corresponding temporary register；8051 monolithic afterwards
Temporary register address read operation order corresponding to machine transmission, the data of corresponding temporary register are read in into 8051 single-chip microcomputers.
When reading fifo module data, 8051 single-chip microcomputers first send out 16 ' h1000 addresses read operation orders, prolong by certain
Lag, fifo module data are read into fifo module data temporary register.16 ' h4000 addresses read operation lives are retransmited afterwards
Order, the data of fifo module data temporary register are read in into 8051 single-chip microcomputers.
When reading register module data, 8051 single-chip microcomputers first send out 16 ' h2000 addresses read operation orders, by certain
After delay, register module data are read into register module data temporary register.The reading of 16 ' h4001 addresses is retransmited afterwards
Operational order, the data of register module data temporary register are read in into 8051 single-chip microcomputers.
When reading RAM module data, 8051 single-chip microcomputers first send out 16 ' h3000 addresses read operation orders, by certain delay
Afterwards, RAM module data are read into RAM module data temporary register.16 ' h4002 addresses read operation orders are retransmited afterwards, will
The data of RAM module data temporary register read in 8051 single-chip microcomputers.
It is likely to be interrupted at any time to interrupt in view of 8051 single-chip microcomputers, and then performs the read operation order for reading new data,
The read operation order that may cause to be interrupted can not correctly read data after interrupt routine is finished.The present invention interrupts control
Interrupt signal can be deferred to reading by molding block when 8051 single-chip microcomputers have also been not carried out a complete read operation order pair
Order is interrupted to 8051 single-chip microcomputers again at the end of.
Claims (5)
- A kind of 1. plug-in RAM Interface data access system based on 8051 single-chip microcomputers, it is characterised in that：Including 8051 single-chip microcomputers, Wishbone master modules, fifo module, register module, RAM module, interruption control module and external equipment；By described in Interface of the plug-in RAM Interface of 8051 single-chip microcomputers as Wishbone bus protocols, 8051 single-chip microcomputer are connected to Wishbone Master modules, the fifo module, register module and RAM module are connected to Wishbone by Wishbone buses Master modules, it is also associated with postponing control module between the Wishbone master modules and Wishbone buses, it is described External equipment is connected to fifo module and register module, the fifo module and register module by interruption control module with 8051 single-chip microcomputers are connected.
- 2. the plug-in RAM Interface data access system according to claim 1 based on 8051 single-chip microcomputers, it is characterised in that： The fifo module, register module and RAM module unified distribution Wishbone base address, register module and the RAM mould Block distributes multiple offset address.
- 3. the plug-in RAM Interface data access system according to claim 1 based on 8051 single-chip microcomputers, it is characterised in that： The fifo module, register module and RAM module further respectively have a temporary register, store respectively from fifo module, The data that register module and RAM module are read.
- 4. the plug-in RAM Interface data access system according to claim 3 based on 8051 single-chip microcomputers, it is characterised in that： The temporary register unified distribution Wishbone base address of the fifo module, register module and RAM module.
- 5. the access of the plug-in RAM Interface data access system based on 8051 single-chip microcomputers according to claim 1,2,3 or 4 Method, it is characterised in that：The Wishbone master modules are by the address of 8051 single-chip microcomputers, data and read-write enable signal The Wishbone bus signals of standard are converted to, and pass through Wishbone bus access fifo modules, register module, RAM moulds Block and fifo module, the temporary register of register module and RAM module three respectively；External equipment cause fifo module and The data variation of register module, when producing interruption, interrupt signal is deferred to 8051 single-chip microcomputers, read command by interruption control module 8051 single-chip microcomputers are interrupted again at the end of, it is implemented as：8051 single-chip microcomputer sends fifo module, register The address read operation order of module and any module of RAM module is to respective modules, after certain delay, respective modules data It is read into corresponding temporary register；Temporary register address read operation order corresponding to 8051 single-chip microcomputers transmission afterwards, will be right The data for the temporary register answered read in 8051 single-chip microcomputers；Now, interrupt signal is interrupted to 8051 single-chip microcomputers again.
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| CN101000593A (en) * | 2006-06-23 | 2007-07-18 | 华为技术有限公司 | Device and method for implementing communication between processes |
| CN101615287A (en) * | 2009-08-06 | 2009-12-30 | 黄以华 | A kind of image processing IP core based on the Wishbone bus |
| CN102591817A (en) * | 2011-12-30 | 2012-07-18 | 中山大学 | Multi-bus bridge controller and implementing method thereof |
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| US8169839B2 (en) * | 2009-02-11 | 2012-05-01 | Stec, Inc. | Flash backed DRAM module including logic for isolating the DRAM |
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| CN2886683Y (en) * | 2006-04-17 | 2007-04-04 | 四川大学 | SoC chip with multimedia and network processing function |
| CN101000593A (en) * | 2006-06-23 | 2007-07-18 | 华为技术有限公司 | Device and method for implementing communication between processes |
| CN1975635A (en) * | 2006-12-28 | 2007-06-06 | 陈曦 | Enhanced wishbone on-chip bus for leading-in bus code |
| CN101615287A (en) * | 2009-08-06 | 2009-12-30 | 黄以华 | A kind of image processing IP core based on the Wishbone bus |
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