The shared device of multiple identical I2C address of devices
Technical field:
The utility model belongs to electronic circuit design field, relates in particular to the shared device of multiple identical I2C address of devices.
Background technology:
I2C bus is the twin wire universal serial bus of being developed by PHILIPS company, for connecting microcontroller and peripherals thereof.It is a kind of bus standard that microelectronics Control on Communication field extensively adopts.It is a kind of special shape of synchronous communication, has interface line few, and control mode is simple, and device package form is little, and traffic rate is compared with advantages of higher.
I2C agreement specifies: each device is to identify by unique address of devices, comes from the 6th page the 0 4th. 0 3rd of Philips Semiconductors " THE I2C-BUS SPECIFICATION " VERSION 2.1 JANUARY 2000.
Owing to possessing, the part category of I2C interface is various, and PHILIPS also recognizes this problem, so the address of devices that has also configured two kinds of specifications in I2C agreement is for selecting, is respectively 7-BIT ADDRESSING/10-BIT ADDRESSING.But however; in the time of the electronic circuit of many I2C of actual design slave communication; also often can meet the same situation of I2C address of devices of some device, AUDIO CODEC tlv320aic3104 and the tlv320aic3105 of for example TI company, both I2C device addresses are the same.Existing I2C agreement not can solve this address of devices collision problem.
Summary of the invention:
Technical problem to be solved in the utility model is: provide a kind of multiple identical I2C address of devices shared device, unibus three-state buffer coordinates the I/O mouth pin of outside MCU microcontroller to control, for the SCL clock line of I2C bus has increased a tri-state break-make electronic switch, solve the communications constraints problem of the unique address of devices in I2C agreement.
In order to achieve the above object, the technical solution adopted in the utility model is:
The shared device of multiple identical I2C address of devices, it is characterized in that, comprise unibus three-state buffer, MCU microcontroller, I2C bus, the MCU microcontroller with several I/O mouths is electrically connected with several unibus three-state buffers simultaneously, unibus three-state buffer and the electrical connection of I2C bus.
Optimal technical scheme, I2C bus is universal serial bus, comprises data line SDA and clock line SCL.
Optimal technical scheme, unibus three-state buffer comprises the OE control pin that is set to enable to hold EN, and A pin and the Y pin of synchronous clock frequency is provided; The A pin of unibus three-state buffer and the clock line SCL of I2C bus electrical connection; The Y pin of unibus three-state buffer and address module electrical connection.
Optimal technical scheme, the data line SDA lead-in wire in I2C bus is directly connected to address module, and a tri-state break-make electronic switch of the upper increase of clock line SCL, carries out level control.
Owing to adopting technique scheme, advantage and good effect that the utility model has are: be convenient to multiple identical I2C address of devices and share, and to realize the time division multiplex processing to identical I2C address of devices module, convenient and practical.
Brief description of the drawings
Fig. 1 is unibus three-state buffer and peripheral circuit diagram thereof.
Fig. 2 is the unibus three-state buffer abstract graph of Fig. 1.
Fig. 3 is the syndeton schematic diagram of address module and unibus three-state buffer.
Embodiment
For being illustrated more clearly in content of the present utility model, be further described below in conjunction with the drawings and specific embodiments:
As shown in Figure 1: the shared device of multiple identical I2C address of devices comprises unibus three-state buffer, MCU microcontroller, I2C bus, the MCU microcontroller with several I/O mouths is electrically connected with several unibus three-state buffers simultaneously, unibus three-state buffer and the electrical connection of I2C bus.I2C bus is universal serial bus, comprises data line SDA and clock line SCL.
R10 is that OE controls the pull-up resistor on pin, the decoupling capacitance that C22 is U5, and R11 is the current-limiting resistance of Y pin output, VCC is supply voltage, GND ground wire; Unibus three-state buffer comprises the OE control pin that is set to enable to hold EN, and A pin and the Y pin of synchronous clock frequency is provided; The A pin of unibus three-state buffer and the clock line SCL of I2C bus electrical connection; The Y pin of unibus three-state buffer and address module electrical connection; Data line SDA lead-in wire in I2C bus is directly connected to address module.
Unibus three-state buffer is connected with MCU microcontroller, controls by the I/O mouth pin of MCU microcontroller, for the SCL clock line of I2C bus increases a tri-state break-make electronic switch, carries out level control.
In the time will carrying out I2C communication to device 1, first MCU_IO1 is set low to level, gating SCL, to SCL2, the SCL clock line of I2C bus can be input on I2C_DEVICE1 address module by bus buffer module.After configuration I2C_DEVICE1, MCU_IO1 is set high to level, block the path of SCL and SCL2, making SCL2 is high-impedance state.
Three I/O mouth controls of MCU microcontroller are processed upper, can not MCU_IO1, MCU_IO2, MCU_IO3 be set high simultaneously and carry out I2C communication simultaneously.Go up at one time and one of them I/O mouth can only be set low, to realize the time division multiplex processing to identical I2C address of devices module.