CN105068961B - A kind of Ethernet interface manages circuit - Google Patents
A kind of Ethernet interface manages circuit Download PDFInfo
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- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
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Abstract
The present invention provides a kind of Ethernet interface management circuit, transit module is made to be electrically connected one first power supply with the processor by first supply port, and a second source is electrically connected with the ethernet interface module by second supply port, the transit module is to according to the control signal, the data transfer direction between control processor and the ethernet interface module.Allow the processor in different voltages domain with the ethernet interface module according to their needs, select corresponding power supply, circuit connection is more flexible, the problem of signal level margin caused by processor and ethernet interface module in the prior art are directly connected to is inadequate is also solved, ensure that the quality of signal of communication.
Description
Technical field
The present invention relates to network connection management field, and circuit is managed more particularly to a kind of Ethernet interface.
Background technology
MIIM (the Medium of 10G ethernet PHYs (Physical Layer, physical layer) chip of mainstream at present
Independent Interface Management, Media Independent Interface management bus) interface support optional 1.2V and
2.5V level, and the MIIM interfaces of general CPU only support 3.3V level, this resulted in general CPU MIIM interfaces and
The MIIM interfaces of 10G PHY chips are in different power domains.Existing implementation is by the MIIM interfaces of 10G PHY chips
Power pin 2.5V powers, i.e. the MIIM interface levels of PHY chip are 2.5V, the MIIM interfaces of CPU and 10G PHY chips
MIIM interfaces are directly connected to.Existing technical disadvantages：One：The MIIM interface powers of 10G PHY are 1.2V power supplys and 2.5V electricity
Source is optional, and in existing technology, the MIIM interface powers of 10G PHY chips only support 2.5V, do not support 1.2V, limit PHY
The design of the flexible more options of power supply.Secondly：The LVTTL level standards of 3.3V LVTTL and 2.5V are：
3.3V LVTTL：Vcc：3.3V；VOH>=2.4V；VOL<=0.4V；VIH>=2V；VIL<=0.8V.
2.5V LVTTL：Vcc：2.5V；VOH>=2.0V；VOL<=0.2V；VIH>=1.7V；VIL<=0.7V.
Wherein, Vcc represents voltage, and VOH represents output high level voltage, and VOL represents output low level voltage, VIH
Represent putting high level voltage, VIL represents input low level voltage.I.e. when PHY chip sends high level signal to CPU, PHY
The high RST that chip is sent is VOH>=2V, and the criterion that CPU receives high level is VIH>=2V, two indices can match somebody with somebody
Close, but without allowance.If the transmission range between CPU to PHY is long, or a CPU manages multiple PHY, line load
When heavier, the decay and deformation of signal may result in so that when the VOH sent from signal PHY chip reaches CPU, due to letter
Number decay, it is impossible to reach 2V, i.e. the allowance of level is inadequate, easily produces error code.
The content of the invention
In view of the foregoing deficiencies of prior art, it is an object of the invention to provide a kind of Ethernet interface management electricity
Road, it is inconsistent and cause PHY chip Power Management Design ineffective for solving the power supply of CPU in the prior art and the power supply of PHY chip
The problem of living.
In order to achieve the above objects and other related objects, the present invention provides a kind of Ethernet interface management circuit, including：Place
Manage device；Ethernet interface module, is communicated by bus with the processor；Transit module, with the processor and described
Ethernet interface module is electrically connected, including control port, the first supply port and the second supply port, the control port connect
Receive a control signal, first supply port is electrically connected one first power supply with the processor, second supply port with
The ethernet interface module is electrically connected a second source, and the transit module is to according to the control signal, control process
Data transfer direction between device and the ethernet interface module.
Optionally, the Ethernet interface management circuit further includes：Complex Programmable Logic Devices module, with the transfer
Module is electrically connected, for providing the control signal to the control port of the transit module.
Optionally, the Complex Programmable Logic Devices module is connected with the bus, with according to the processor and
The parsing of the communication protocol of bus between the ethernet interface module and produce the control signal.
Optionally, before the Complex Programmable Logic Devices module includes the analysis result of the communication protocol of the bus
Leading code, frame start mark, command code, ethernet interface module internal register addresses, State Transferring domain, read/write status mark
Position.
Optionally, it is from the processor to described that the control signal, which is defaulted as being used to control the data transfer direction,
Ethernet interface module, and when judging the read/write status flag bit to read, make the transit module be believed according to the control
Number, it is from the ethernet interface module to the processor to make the data transfer direction.
Optionally, the processor is also to produce a clock signal, and by the transit module to the Ethernet
Interface module transmits the clock signal.
Optionally, the transit module controls the transmission direction of the clock signal to remain from the processor to described
Ethernet interface module.
Optionally, the transit module is SN74AVC2T245 chips.
Optionally, led between the processor and the ethernet interface module by Media Independent Interface bus
Letter.
Optionally, the first power supply is 3.3V power supplys, and the second source is 1.2V or 2.5V power supplys.
As described above, the present invention Ethernet interface management circuit, make transit module by first supply port with
The processor is electrically connected one first power supply, and is electrically connected one with the ethernet interface module by second supply port
Second source, the transit module is to according to the control signal, between control processor and the ethernet interface module
Data transfer direction.The processor in different voltages domain is set according to their needs, to be selected with the ethernet interface module
Corresponding power supply is selected, circuit connection is more flexible, also solves processor in the prior art and is directly connected to ethernet interface module
Caused by signal level margin it is inadequate the problem of, ensure that the quality of signal of communication.
Brief description of the drawings
Fig. 1 is shown as a kind of module diagram of Ethernet interface management circuit of the present invention in one embodiment.
The sequence diagram of DIR2 during the circuit that Fig. 2 is shown as shown in Fig. 2 is run in one embodiment.
Fig. 3 is shown as a kind of circuit diagram of Ethernet interface management circuit of the present invention in one embodiment.
Component label instructions
1 Ethernet interface manages circuit
11 processors
12 ethernet interface modules
13 transit modules
Embodiment
Illustrate embodiments of the present invention below by way of specific instantiation, those skilled in the art can be by this specification
Disclosed content understands other advantages and effect of the present invention easily.The present invention can also pass through in addition different specific realities
The mode of applying is embodied or practiced, the various details in this specification can also be based on different viewpoints with application, without departing from
Various modifications or alterations are carried out under the spirit of the present invention.It should be noted that in the case where there is no conflict, following embodiments and implementation
Feature in example can be mutually combined.
It should be noted that the diagram provided in following embodiments only illustrates the basic structure of the present invention in a schematic way
Think, component count, shape and size when only display is with related component in the present invention rather than according to actual implementation in illustrating then
Draw, kenel, quantity and the ratio of each component can be a kind of random change during its actual implementation, and its assembly layout kenel
It is likely more complexity.
MIIM (Management Interface, Media Independent Interface) bus is CPU to 10G Ethernet PHY chips
Management interface, MIIM have two signal wires, management data clock MDC (Management Data Clock) and management data letter
Number MDIO (Management Data Input/Output).CPU can be believed by MIIM buses to configure the register of PHY
Breath, for example, the operating rate of PHY, interface transmission medium selection and operating mode selection, can also by MIIM buses come
The content of registers for reading PHY obtains the work state information of PHY.
The MIIM interfaces of the 10G Ethernet PHY chips of mainstream support optional 1.2V and 2.5V level at present, if PHY
The power pin 1.2V power supplies of chip MIIM interfaces, MIIM buses just support 1.2V level；If the electricity of PHY chip MIIM interfaces
Source capsule foot 2.5V powers, and MIIM buses just support 2.5V level.And the MIIM interfaces of general CPU only support 3.3V level, this
The MIIM interfaces of general CPU are resulted in and the MIIM interfaces of 10G PHY chips are in different power domains.And in order to can be with
Normally communicated with the CPU, it is necessary to the power supply for selecting Ethernet PHY chip is 2.5V, and due to 3.3V LVTTL and
The LVTTL level standards of 2.5V are：
3.3V LVTTL：Vcc：3.3V；VOH>=2.4V；VOL<=0.4V；VIH>=2V；VIL<=0.8V.
2.5V LVTTL：Vcc：2.5V；VOH>=2.0V；VOL<=0.2V；VIH>=1.7V；VIL<=0.7V.
Wherein, Vcc represents voltage, and VOH represents output high level voltage, and VOL represents output low level voltage, VIH
Represent putting high level voltage, VIL represents input low level voltage.I.e. when PHY chip sends high level signal to CPU, PHY
The high RST that chip is sent is VOH>=2V, and the criterion that CPU receives high level is VIH>=2V, two indices can match somebody with somebody
Close, but without allowance.If the transmission range between CPU to PHY is long, or a CPU manages multiple PHY, line load
When heavier, the decay and deformation of signal may result in so that when the VOH sent from signal PHY chip reaches CPU, due to letter
Number decay, it is impossible to reach 2V, i.e. the allowance of level is inadequate, easily produces error code.
So the CPU and PHY chip is set to be in the Ethernet interface of same power domain present invention proposes this
Circuit is managed, referring to Fig. 1, being shown as a kind of module of Ethernet interface management circuit of the present invention in one embodiment
Schematic diagram.The Ethernet interface management circuit 1 includes processor 11, ethernet interface module 12 and transit module 13.
The ethernet interface module 12 is communicated by bus with the processor 11；In this present embodiment, it is described
Bus is MIIM buses.
The transit module 13 is electrically connected with the processor 11 and the ethernet interface module 12, including control terminal
Mouthful, the first supply port and the second supply port, the control port receives a control signal, first supply port with
The processor is electrically connected one first power supply, and second supply port is electrically connected one second electricity with the ethernet interface module
Source, the transit module 13 is to according to the control signal, between control processor 11 and the ethernet interface module 12
Data transfer direction.The processor 11 in different voltages domain can be allow with the ethernet interface module 12 according to itself
Need, select corresponding power supply, for example, first power supply is 3.3V power supplys, the second source is 1.2V or 2.5V power supplys.
I.e. when the processor 11 chooses power supply 3.3V, 1.2V power supplys or 2.5V power supplys may be selected in the ethernet interface module 12,
Circuit connection is more flexible, and ensures there are enough level margins between processor 11 and ethernet interface module 12, ensure that logical
Believe the quality of signal.
In another specific embodiment, the Ethernet interface management circuit 1 further includes：Complex Programmable Logic Devices mould
Block (CPLD, Complex Programmable Logic Device), is electrically connected with the transit module 13, for described
The control port of transit module 13 provides the control signal.And the CPLD can be according to the processor 11 and described
The parsing of the communication protocol of bus between ethernet interface module 12 and produce the control signal.The CPLD is to described total
The analysis result of the communication protocol of line is with including lead code, frame start mark, command code, ethernet interface module internal register
Location, State Transferring domain, read/write status flag bit.The control signal be defaulted as be used for control the data transfer direction be from
The processor 11 arrives the ethernet interface module 12, and when judging the read/write status flag bit to read, make it is described in
For revolving die block 13 according to the control signal, it is from the ethernet interface module 13 to the processing to make the data transfer direction
Device 12.
Specifically, in a concrete application, the ethernet interface module 12 is the PHY Ethernets of model BCM8705
Chip, the transit module 13 are the dual power supply driving chip of model SN74AVC2T245, and the processor 11 is one
CPU.The CPLD produces the control according to analysis result to parse the signal of communication of the MDIO pins of the processor
Signal processed.Specifically, referring to table 1, the sequential allocation list of MDIO is shown as, wherein " Pre " is lead code, includes 32-bit's
' 1 ' data；" ST " is frame start mark, it is 2-bit " 00 "；" OP " is 2-bit command codes, and " 10 " are read operations, and " 01 " is to write
Operation；" PRTAD " is 5-bit PHY chips address, and PHY chip sets PHY addresses by hardware pins；" REGAD " is 5-bit
PHY chip internal register addresses；" TA " is State Transferring domain, common 2bit.If read operation, then 1bit is high by CPU submittings
Resistance state, 2bit send out " 0 " bit by PHY chip, are such as write operation, then CPU sends " TA " signal of 2-bit " 10 ".
| Operation | Pre | ST | OP | PRTAD | REGAD | TA | DATA | IDLE |
| READ | 1..1 | 00 | 10 | AAAAA | TTTTT | Z0 | 16bits Data | Z..Z |
| WRITE | 1..1 | 00 | 01 | AAAAA | TTTTT | 10 | 16bits Data | Z..Z |
Table 1
And the operation principle flow of CPLD parsings MDIO is specially：
The sequence diagram of DIR2 with reference to shown in Fig. 2, CPLD is default to assign high level ' 1 ' by DIR2, control the data of MDIO from
The A2 ports of SN74AVC2T245 enter, and B2 ports output, data flow to PHY chip from CPU.CPLD searches for lead code first,
Following search frame beginning flag position, then judges whether operation is reading, if reading, continues 9 clock cycle of holding
DIR2 is ' 1 ', and the address of PHY and register address are continued to be transmitted in PHY chip by CPU, then DIR2 is put ' 0 ', control
The data of MDIO enter from the B2 ports of SN74AVC2T245, the output of A2 ports, by the of PHY " TA " the State Transferring domains sent
The 16bit data of 2bit ' 0 ' and the specified register read give CPU, and ' 0 ' state of DIR2 is tied after continuing 17 clock cycle
Beam, default value ' 1 ' is put by DIR2, into etc. the next instruction cycle to be searched.When CPU carries out write operation to PHY chip,
MDIO data flows remain that from CPU to PHY chip CPLD puts ' 1 ' to DIR2 all the time.
I.e. during this period, as shown in Fig. 2, DIR2 is during write operation, DIR2 be ' 1 ', in read operation, DIR2 from
2nd bit of " TA " starts to be low, continues 17 bit durations altogether, and other time is ' 1 '.The MDIO pins that CPLD passes through CPU
Signal of communication parsing, produce control signal and control the direction of twin voltage driving chip so that between CPU and PHY chip
Carry out normal data transfer.
In one embodiment, the processor 11 is also to produce a clock signal, and pass through the transit module
13 transmit the clock signal to the ethernet interface module 12, and the transit module 13 controls the transmission of the clock signal
Direction is remained from the processor 11 to the ethernet interface module 12.
Further referring to Fig. 3, a kind of Ethernet interface management circuit of the present invention is shown as in one embodiment
Circuit diagram.
Wherein, the circuit includes a CPU and a CPLD logic chips, and the ethernet interface module is model
The PHY Ethernet chips of BCM8705, the transit module are the dual power supply driving chip of model SN74AVC2T245.
Wherein, specific circuit is connected as：SCL pins, SDA pins, MDC pins and the MDIO pins point of the CPU
SCL pins, SDA pins, MDC pins and MDIO pins not with the CPLD are electrically connected, SCL pins, the SDA of the CPU
Pin, MDC pins and MDIO pins, and the SCL pins of the CPLD, SDA pins, MDC pins and MDIO pins point
Do not connect after a resistance with the first power electric connection, the MDIO_DR pins of the CPLD and the SN74AVC2T245 chips
DR2 pins are electrically connected, and the CPLD produces the control signal and pass through institute to parse the information of its MDIO pin reception
MDIO_DR pins are stated to be sent on the DR2 pins of the SN74AVC2T245.
It is described and the A1 pins of the SN74AVC2T245 chips are electrically connected with the MDC pins of the CPU
The B1 pins of SN74AVC2T245 chips are electrically connected with the MDC pins of the BCM8705 chips, the SN74AVC2T245 chips
DR1 pins and VCCA pins connect first power supply, the VCC pin of the CPU and the CPLD logic chips
VCC pin is all connected with first power supply.When the DR1 pins of the SN74AVC2T245 chips receive high level, signal is from A1
B1 is flowed to, opposite, when DR1 pins receive low level, signal flows to A1 from B1, and MDC signals are one way signals, and signal flow direction is
From CPU to PHY chip, so make the DR1 be constantly in high level state, even the A1 of the SN74AVC2T245 chips and
Data transfer direction between B1 is A1 to B1, realizes the connection of the clock signal of CPU and PHY chip.
And the MDIO pins of the CPU are electrically connected with the A2 pins of the SN74AVC2T245 chips, and it is described
The B2 pins of SN74AVC2T245 chips are electrically connected with the MDIO pins of the BCM8705 chips, the SN74AVC2T245 cores
The VCCB pins of piece and the VCC pin of the BCM8705 chips are all connected with same second source, the SN74AVC2T245 chips
According to the parsing to the DR2 received signals, the data transfer direction between pin A2 and pin B2 is selected.Wherein, it is described
When the DR2 pins of SN74AVC2T245 chips receive high level, signal flows to B1 from A1, opposite, DR2 pins receive high level
When, signal flows to A1 from B1.MDIO is two-way signaling, therefore the DIR2 pins of the control direction signal of SN74AVC2T245 need
Always controlled according to actual signal stream, direction control signal DIR2 is produced by CPLD, the MIIM buses between CPU and PHY
CPLD is connected to, CPLD parses the information on MDIO signals, and the control signal of input DIR2 pins is produced according to analysis result.It is excellent
Choosing, first power supply is 3.3V, and the second source is the 1.2V or 2.5V that can flexibly select, and the resistance is 1.5K Europe
Nurse.
Further, the BCM8705 chips are electrically connected with an Ethernet physical interface, for example, SFP optical modules, and institute
State TX+, TX-, RX+, the RX- of TX+, TX-, RX+, RX- of BCM8705 respectively with the SFP optical modules to be electrically connected, to receive
The network insertion of external devices.
In conclusion the present invention Ethernet interface management circuit, make transit module by first supply port with
The processor is electrically connected one first power supply, and is electrically connected one with the ethernet interface module by second supply port
Second source, the transit module is to according to the control signal, between control processor and the ethernet interface module
Data transfer direction.The processor in different voltages domain is set according to their needs, to be selected with the ethernet interface module
Corresponding power supply is selected, circuit connection is flexible, also solves processor in the prior art and is directly connected to make with ethernet interface module
Into signal level margin it is inadequate the problem of, ensure that the quality of signal of communication.So the present invention effectively overcomes the prior art
In various shortcoming and have high industrial utilization.
The above-described embodiments merely illustrate the principles and effects of the present invention, not for the limitation present invention.It is any ripe
Know the personage of this technology all can carry out modifications and changes under the spirit and scope without prejudice to the present invention to above-described embodiment.Cause
This, those of ordinary skill in the art is complete without departing from disclosed spirit and institute under technological thought such as
Into all equivalent modifications or change, should by the present invention claim be covered.
Claims (6)
1. a kind of Ethernet interface manages circuit, it is characterised in that including：
Processor；
Ethernet interface module, is communicated by bus with the processor；
Transit module, is electrically connected with the processor and the ethernet interface module, including control port, the first supply port
And second supply port, the control port receive a control signal, first supply port is electrically connected with the processor
One first power supply is connect, second supply port is electrically connected a second source, the middle revolving die with the ethernet interface module
Block is to according to the control signal, the data transfer direction between control processor and the ethernet interface module；
The Ethernet interface management circuit further includes：
Complex Programmable Logic Devices module, is electrically connected with the transit module, for the control to the transit module
Port provides the control signal；
The Complex Programmable Logic Devices module is connected with the bus, and the processor and the Ethernet are connect with basis
The parsing of the communication protocol of bus between mouth mold block and produce the control signal；
The Complex Programmable Logic Devices module includes lead code to the analysis result of the communication protocol of the bus, frame originates
Mark, command code, ethernet interface module internal register addresses, State Transferring domain, read/write status flag bit；
It is from the processor to the Ethernet interface that the control signal, which is defaulted as being used to control the data transfer direction,
Module, and when judging the read/write status flag bit to read, the transit module is made according to the control signal, described in order
Data transfer direction is from the ethernet interface module to the processor.
2. Ethernet interface according to claim 1 manages circuit, it is characterised in that：The processor is also producing one
Clock signal, and the clock signal is transmitted to the ethernet interface module by the transit module.
3. Ethernet interface according to claim 2 manages circuit, it is characterised in that：When the transit module controls described
The transmission direction of clock signal is remained from the processor to the ethernet interface module.
4. circuit is managed according to claims 1 to 3 any one of them Ethernet interface, it is characterised in that the transit module
For SN74AVC2T245 chips.
5. according to claims 1 to 3 any one of them Ethernet interface manage circuit, it is characterised in that the processor with
Communicated between the ethernet interface module by Media Independent Interface bus.
6. circuit is managed according to claims 1 to 3 any one of them Ethernet interface, it is characterised in that the first power supply is
3.3V power supplys, the second source are 1.2V or 2.5V power supplys.
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| CN105912494A (en) * | 2016-04-11 | 2016-08-31 | 上海斐讯数据通信技术有限公司 | MIIM bus circuit |
| CN109580997A (en) * | 2018-11-30 | 2019-04-05 | 泸州威恩德科技有限公司 | Test fixture, test device and test macro |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101059691A (en) * | 2007-05-24 | 2007-10-24 | 北京天航信民航通信网络发展有限公司 | Automatic metering controller |
| CN101291059A (en) * | 2007-08-28 | 2008-10-22 | 东南大学 | Electricity quality analyzer oriented to digitalized electrical system and electricity quality analysis method |
| CN102833002A (en) * | 2012-08-23 | 2012-12-19 | 哈尔滨工业大学 | Data transmission device and method supporting fibre channel protocol |
| CN202679392U (en) * | 2012-06-19 | 2013-01-16 | 华自科技股份有限公司 | Embedded type communication management machine |
| CN202759472U (en) * | 2012-09-03 | 2013-02-27 | 北京东土科技股份有限公司 | Industrial Ethernet switch |
| CN104037941A (en) * | 2014-06-05 | 2014-09-10 | 中国海洋石油总公司 | Control protection system for flexible direct-current power transmission system |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20090006659A1 (en) * | 2001-10-19 | 2009-01-01 | Collins Jack M | Advanced mezzanine card for digital network data inspection |
-
2015
- 2015-09-11 CN CN201510578628.4A patent/CN105068961B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101059691A (en) * | 2007-05-24 | 2007-10-24 | 北京天航信民航通信网络发展有限公司 | Automatic metering controller |
| CN101291059A (en) * | 2007-08-28 | 2008-10-22 | 东南大学 | Electricity quality analyzer oriented to digitalized electrical system and electricity quality analysis method |
| CN202679392U (en) * | 2012-06-19 | 2013-01-16 | 华自科技股份有限公司 | Embedded type communication management machine |
| CN102833002A (en) * | 2012-08-23 | 2012-12-19 | 哈尔滨工业大学 | Data transmission device and method supporting fibre channel protocol |
| CN202759472U (en) * | 2012-09-03 | 2013-02-27 | 北京东土科技股份有限公司 | Industrial Ethernet switch |
| CN104037941A (en) * | 2014-06-05 | 2014-09-10 | 中国海洋石油总公司 | Control protection system for flexible direct-current power transmission system |
Non-Patent Citations (1)
| Title |
|---|
| DUAL-BIT DUAL-SUPPLY BUS TRANSCEIVER WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS;Texas Instruments Incorporated;《http://www.farnell.com/datasheets/1863675.pdf》;20120531;第2页功能表1及第3页附图1 * |
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