CN105912494A - MIIM bus circuit - Google Patents
MIIM bus circuit Download PDFInfo
- Publication number
- CN105912494A CN105912494A CN201610221360.3A CN201610221360A CN105912494A CN 105912494 A CN105912494 A CN 105912494A CN 201610221360 A CN201610221360 A CN 201610221360A CN 105912494 A CN105912494 A CN 105912494A
- Authority
- CN
- China
- Prior art keywords
- circuit
- master control
- control borad
- line
- miim
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Classifications
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4063—Device-to-bus coupling
- G06F13/4068—Electrical coupling
Abstract
The present invention discloses an MIIM bus circuit. The MIIM bus circuit at least comprises two main control boards and an uplink card; each main control board at least comprises a main control board main circuit; an MIIM interface of the main control board main circuit of each main control board is connected with an MIIM interface of the uplink card through a backboard; and main/standby notification signals are generated by the main control boards and sent to the uplink card, so that the uplink card is only controlled by the main-use main control boards. An Ethernet PHY chip on the uplink card is directly managed by CPUs on the main control boards, system cost is saved, complexity of system design is reduced, and rapid execution of instructions is also ensured.
Description
Technical field
The present invention relates to a kind of MIIM bus circuit, particularly relate to a kind of MIIM transmitted by backboard total
Line circuit.
Background technology
For ensureing network system operational reliability, existing network system is generally designed as master control system, and one
Block is main control board, and one piece is slave control board, to realize redundancy backup function, and the most primary master
Control plate realizes the management function of whole system, slave control board Hot Spare, is receiving system masterslave switchover order
After, two pieces of master control borad masterslave switchovers, the most original slave control board becomes main control board, obtains system
Control, and original main control board becomes standby plate, has the control of system no longer.
In network system, the business datum of other line card converges to Wan Card, the first line of a couplet by backboard
10G ethernet PHY chip on card passes through the equipment outside 10G optical module optical fiber and system and connects, it is achieved
The function of the data first line of a couplet.
MIIM (Medium Independent Interface Management, GMII manages)
Interface is the management interface of ethernet PHY chip, and it has unidirectional clock signal MCK and a two-way number
The number of it is believed that MDIO.In dual master control plate system, the CPU on main control board passes through MIIM bus to first line of a couplet card
On 10G ethernet PHY management of software ic, 10G ethernet PHY chip can be read by MIIM bus
Depositor with obtain Ethernet interface state, or configuration 10G ethernet PHY chip depositor, change
Become the mode of operation etc. of 10G ethernet PHY chip.
Fig. 1 is the block schematic illustration in existing dual master control plate system to the management of first line of a couplet card.In current network system
In system, being typically all by increasing a cpu chip on first line of a couplet card, the MIIM interface utilizing CPU is direct
Management PHY chip, then main control board is again by 100,000,000 of the CPU on a 100-M network Ethernet and first line of a couplet card
Network interface communicates, and indirectly manages the PHY chip of first line of a couplet card.
Above-mentioned prior art has the disadvantage that on first line of a couplet card to need to increase supports MIIM interface and 100-M network Ethernet
CPU, add the cost of system and the complexity of design；Main control board and 10G ethernet PHY chip
During communication, need by the CPU transfer on first line of a couplet card, cause controlling Ethernet interface and obtaining Ethernet interface shape
The time delay of state.
Summary of the invention
For the deficiency overcoming above-mentioned prior art to exist, the purpose of the present invention is to provide a kind of MIIM bus
Circuit, it utilizes the CPU on master control borad directly to manage the 10G ethernet PHY chip on first line of a couplet card, saves
The cost of system, reduces the complexity of system design, also ensure that the quick execution of instruction.
For reaching above-mentioned purpose, the present invention proposes a kind of MIIM bus circuit, at least include two master control borads with
And first line of a couplet card, each master control borad at least includes a master control borad main circuit, the master control borad main circuit of each master control borad
MIIM interface be connected with the MIIM interface of described first line of a couplet card by backboard, master control borad generation standby usage lead to
Know that signal, to described first line of a couplet card, makes described first line of a couplet card only by main control board control.
Further, each master control borad also includes that master control borad enables circuit and master control borad interface circuit, described master
Control plate enables circuit and connects described master control borad main circuit, for producing the switching signal of two master control borads to described
First line of a couplet card；Described master control borad interface circuit connects described master control borad main circuit, for by main described in data separate
The MIIM interface of control plate circuit transmits to described first line of a couplet card through backboard from master control borad main circuit.
Further, described first line of a couplet card includes first line of a couplet card interface circuit and first line of a couplet card main circuit, the described first line of a couplet
Card interface circuit connects described master control borad by backboard and enables circuit and described master control borad interface circuit, with will be through
The ethernet PHY chip of the main control board data transmission extremely described first line of a couplet card main circuit that backboard transmission comes.
Further, one of them of described first line of a couplet card interface circuit and two master control borad enable circuit connects.
Further, described master control borad interface circuit comprises bidirectional interface circuit and the periphery thereof supporting hot plug
Circuit, its input connects the MIIM interface of described master control borad main circuit, and outfan is connected to institute by backboard
State the input port of first line of a couplet card interface circuit.
Further, the enable pin of described bidirectional interface circuit connects earth signal, Low level effective.
Further, described first line of a couplet card interface circuit includes two analog switches supporting hot plug, two moulds
The one end intending switch connects clock signal mouth and the bi-direction data signal mouth of described first line of a couplet card main circuit, often respectively
The another two ends of individual analog switch connect described master control borad interface circuit, and the enable port of each analog switch connects
Described master control borad enables the outfan of circuit.
Further, described master control borad enables circuit and includes a CPLD or FPGA circuitry and peripheral circuit thereof,
It is communicated with the CPU of data signal line with described master control borad main circuit by the clock cable of data/address bus.
Further, described first line of a couplet card is 10G first line of a couplet card.
Compared with prior art, the MIIM interface of master control borad CPU is led to by a kind of MIIM of present invention bus circuit
Cross master control borad interface circuit, first line of a couplet card interface circuit is connected with the MIIM interface of first line of a couplet card, and master control borad produces main
Standby notification signal is to first line of a couplet card, it is ensured that first line of a couplet card is only by main control board control, and the present invention utilizes master control borad
On CPU directly manage the ethernet PHY chip of first line of a couplet card, save the cost of system, decrease system
The complexity of design, also ensure that the quick execution of instruction；The present invention is respectively at master control borad and the MIIM of first line of a couplet card
Hot plug design is done, it is ensured that do not damage chip when plugging veneer on interface.
Accompanying drawing explanation
Fig. 1 is the block schematic illustration in existing dual master control plate system to the management of first line of a couplet card；
Fig. 2 is the circuit structure diagram of the present invention a kind of MIIM bus circuit；
Fig. 3 is the circuit structure diagram of the MIIM bus circuit of present pre-ferred embodiments.
Detailed description of the invention
Below by way of specific instantiation accompanying drawings embodiments of the present invention, art technology
Personnel can be understood further advantage and effect of the present invention easily by content disclosed in the present specification.The present invention
Also can be implemented by other different instantiation or be applied, the every details in this specification also can base
In different viewpoints and application, under the spirit without departing substantially from the present invention, carry out various modification and change.
Fig. 2 is the circuit structure diagram of the present invention a kind of MIIM bus circuit.As in figure 2 it is shown, the present invention is a kind of
MIIM bus circuit, including: the first master control borad the 1, second master control borad 2 and first line of a couplet card 3, the first master control borad
1, the second master control borad 2, first line of a couplet card 3 are connected by backboard, and wherein, each master control borad includes: master control borad
Enabling circuit 10, master control borad interface circuit 20, master control borad main circuit 40, first line of a couplet card 3 includes first line of a couplet card interface
Circuit 30 and first line of a couplet card main circuit 50.
Wherein, master control borad main circuit 40 and first line of a couplet card main circuit 50 are system primary circuit, and master control borad enables electricity
Road 10 is CPLD or FPGA (for U2 in figure) circuit and peripheral circuit such as bus pull-up resistor R1/R2 thereof,
It is by data/address bus such as I2C (clock cable SCL/ data signal line SDA) and master control borad main circuit 40
CPU communicates, for producing the switching signal of the first master control borad 1 and the second master control borad 2 to first line of a couplet card interface circuit
30, and inform that the duty of this master control borad is primary or standby, it should be noted that, here owing to passing through
One switching signal achieves that the first master control borad 1 and switching of the second master control borad 2, therefore, the first master control
A master control borad in plate 1 or the second master control borad 2 enables circuit 10 and connects first line of a couplet card interface circuit 30,
But the present invention is not limited；Master control borad interface circuit 20 comprises the bidirectional interface circuit U3 supporting hot plug
And peripheral circuit such as bus pull-up resistor R3/R4, being used for data separate MIIM interface (is clock in figure
Line MDC/ bidirectional data line MDIO) transmit to first line of a couplet card interface circuit 30 through backboard from master control borad main circuit 40,
And support hot plug；First line of a couplet card interface circuit 30 is made up of the analog switch U4/U5 supporting hot plug, is used for
The main control board data come through backboard transmission is transmitted the ethernet PHY chip U6 to first line of a couplet card main circuit 50, and
Support hot plug.
Specifically, I2C data/address bus (the clock cable SCL/ of the CPU (U1) of master control borad main circuit 40
Data signal line SDA) connect master control borad enable circuit 10 corresponding port, the CPU of master control borad main circuit 40
(U1) MIIM bus (MDC/MDIO) connects the input (A1/A2) of master control borad interface circuit 20,
The output port of master control borad enable circuit 10 is connected to the enable port of first line of a couplet card interface circuit 30 by backboard
(the 1 foot IN interface of U4/U5), the outfan (B1/B2) of the master control borad interface circuit 20 of the first master control borad 1
The first input port (the 9 foot NC interfaces of U4/U5) of first line of a couplet card interface circuit 30 it is connected to by backboard,
The outfan (B1/B2) of the master control borad interface circuit 20 of the second master control borad 2 is connected to first line of a couplet card by backboard
Second input port (the 2 foot NO interfaces of U4/U5) of interface circuit 30, first line of a couplet card interface circuit 30
Output port (the 10 foot com interfaces of U4/U5) is connected to the Ethernet of the first line of a couplet card main circuit 50 of first line of a couplet card
The MIIM EBI (being clock line MDC/ bidirectional data line MDIO in figure) of PHY chip U6.
Fig. 3 is the circuit structure diagram of the MIIM bus circuit of present pre-ferred embodiments.Wherein, master control borad A
Representing the master control borad inserting backboard A groove, master control borad B represents the master control borad inserting backboard B groove, one piece of 10G
The MIIM bus of first line of a couplet card is connected to two pieces of master control borads by backboard, and principal and subordinate is indicated by the master control borad being inserted in A groove
Signal/ACT IVE_A is dealt on 10G first line of a couplet card, and 10G first line of a couplet card signal accordingly judges to distinguish active and standby master control borad,
When/ACT IVE_A signal is low, master control borad A is primary, and when/ACT IVE_A is high, master control borad B is
Primary.On master control borad, U1 is CPU, and U2 is CPLD, CPU by clock signal SCL of I2C interface and
Data signal SDA communicates with CPLD, informs that this plate of CPLD is main board or standby plate, and CPLD exports
/ ACT IVE_A (/ACT IVE_B) signal is to backboard.Main control board output/ACT IVE_A signal is to backboard, standby
With master control borad output/ACT IVE_B signal to backboard, U3 is a bidirectional drive supporting hot plug, makes
Can link on earth signal by pin/OE, Low level effective, the bidirectional drive of U3 be opened.
On 10G first line of a couplet card, U6 be 10G ethernet PHY chip BCM8705, U4 and U5 be support heat insert
The analog switch chip MAX4736 pulled out, its truth table is as shown in table 1.When being ' 0 ' when selecting signal IN,
NC turns on, and NO closes.When being ' 1 ' when selecting signal IN, NO turns on, and NC closes.
Table 1
When master control borad A is primary ,/ACT IVE_A signal is ' 0 ', ethernet PHY chip BCM8705
Select to communicate with MDC_A with MD IO_A signal, otherwise, when master control borad A is standby ,/ACT IVE_A believes
Number being ' 1 ', ethernet PHY chip BCM8705 selects to communicate with MDC_B with MD IO_B signal, thus
The 10G ethernet PHY chip achieved on first line of a couplet card communicates with the CPU on main control board, and standby
The CPU of master control borad disconnects.
In sum, the MIIM interface of master control borad CPU is passed through master control by a kind of MIIM of present invention bus circuit
Plate interface circuit, first line of a couplet card interface circuit are connected with the MIIM interface of first line of a couplet card, and master control borad produces standby usage and leads to
Know that signal is to first line of a couplet card, it is ensured that first line of a couplet card is only by main control board control, and the present invention utilizes the CPU on master control borad
Directly manage the ethernet PHY chip of first line of a couplet card, save the cost of system, decrease answering of system design
Polygamy, also ensure that the quick execution of instruction；The present invention is respectively on the MIIM interface of master control borad and first line of a couplet card
Do hot plug design, it is ensured that do not damage chip when plugging veneer.
Any those skilled in the art all can be under the spirit and the scope of the present invention, to above-described embodiment
Modify and change.Therefore, the scope of the present invention, should be as listed by claims.
Claims (9)
1. a MIIM bus circuit, at least includes two master control borads and a first line of a couplet card, each master control borad
At least include a master control borad main circuit, it is characterised in that: the MIIM of the master control borad main circuit of each master control borad connects
Mouth is connected with the MIIM interface of described first line of a couplet card by backboard, master control borad produce standby usage notification signal to institute
State first line of a couplet card, make described first line of a couplet card only by main control board control.
2. a kind of MIIM bus circuit as claimed in claim 1, it is characterised in that: each master control borad is also
Enabling circuit and master control borad interface circuit including master control borad, described master control borad enables circuit and connects described master control borad
Main circuit, for producing the switching signal of two master control borads to described first line of a couplet card；Described master control borad interface circuit
Connect described master control borad main circuit, be used for the MIIM interface of master control borad circuit described in data separate from master control borad
Main circuit is through backboard transmission extremely described first line of a couplet card.
3. a kind of MIIM bus circuit as claimed in claim 2, it is characterised in that: described first line of a couplet Ka Bao
Including first line of a couplet card interface circuit and first line of a couplet card main circuit, described first line of a couplet card interface circuit connects described by backboard
Master control borad enables circuit and described master control borad interface circuit, with the main control board data transmission that will come through backboard transmission
Ethernet PHY chip to described first line of a couplet card main circuit.
4. a kind of MIIM bus circuit as claimed in claim 3, it is characterised in that: described first line of a couplet clamping
One of them of mouth circuit and two master control borad enable circuit connects.
5. a kind of MIIM bus circuit as claimed in claim 4, it is characterised in that: described master control borad connects
Mouth circuit comprises bidirectional interface circuit and the peripheral circuit thereof supporting hot plug, and its input connects described master control
The MIIM interface of plate main circuit, outfan is connected to the input port of described first line of a couplet card interface circuit by backboard.
6. a kind of MIIM bus circuit as claimed in claim 5, it is characterised in that: described bidirectional interface
The enable pin of circuit connects earth signal, Low level effective.
7. a kind of MIIM bus circuit as claimed in claim 5, it is characterised in that: described first line of a couplet clamping
Mouth circuit includes two analog switches supporting hot plugs, and the common port of two analog switches connects described respectively
The clock signal mouth of first line of a couplet card main circuit and bi-direction data signal mouth, the another two ends of each analog switch connect institute
Stating master control borad interface circuit, the enable port of each analog switch connects described master control borad and enables the output of circuit
End.
8. a kind of MIIM bus circuit as claimed in claim 7, it is characterised in that: described master control borad makes
Can include a CPLD or FPGA circuitry and peripheral circuit thereof by circuit, it is by the clock cable of data/address bus
Communicate with the CPU of data signal line with described master control borad main circuit.
9. a kind of MIIM bus circuit as claimed in claim 8, it is characterised in that: described first line of a couplet card is
10G first line of a couplet card.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610221360.3A CN105912494A (en) | 2016-04-11 | 2016-04-11 | MIIM bus circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610221360.3A CN105912494A (en) | 2016-04-11 | 2016-04-11 | MIIM bus circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN105912494A true CN105912494A (en) | 2016-08-31 |
Family
ID=56745792
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201610221360.3A Pending CN105912494A (en) | 2016-04-11 | 2016-04-11 | MIIM bus circuit |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115982086A (en) * | 2023-02-14 | 2023-04-18 | 井芯微电子技术(天津)有限公司 | Chip prototype verification board |
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| CN101114913A (en) * | 2007-08-28 | 2008-01-30 | 福建星网锐捷网络有限公司 | Modularized switch |
| CN103532953A (en) * | 2013-10-16 | 2014-01-22 | 中国南方电网有限责任公司 | IEEE (Institute of Electrical and Electronics Engineers) 1588 master station based on Ucos-II operating system and Lwip (Lightweight Internet Protocol) stack and method for processing message based on master station |
| CN204272166U (en) * | 2014-12-22 | 2015-04-15 | 绵阳灵通电讯设备有限公司 | A kind of Ethernet switch |
| CN105068961A (en) * | 2015-09-11 | 2015-11-18 | 上海斐讯数据通信技术有限公司 | Ethernet interface management circuit |
| CN105263071A (en) * | 2015-10-30 | 2016-01-20 | 上海斐讯数据通信技术有限公司 | OLT self-adaptive system and method thereof |
| CN105306324A (en) * | 2015-09-22 | 2016-02-03 | 上海斐讯数据通信技术有限公司 | Ethernet multiplexed communication system and Ethernet interface setting method applied to Ethernet multiplexed communication system |
-
2016
- 2016-04-11 CN CN201610221360.3A patent/CN105912494A/en active Pending
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101114913A (en) * | 2007-08-28 | 2008-01-30 | 福建星网锐捷网络有限公司 | Modularized switch |
| CN103532953A (en) * | 2013-10-16 | 2014-01-22 | 中国南方电网有限责任公司 | IEEE (Institute of Electrical and Electronics Engineers) 1588 master station based on Ucos-II operating system and Lwip (Lightweight Internet Protocol) stack and method for processing message based on master station |
| CN204272166U (en) * | 2014-12-22 | 2015-04-15 | 绵阳灵通电讯设备有限公司 | A kind of Ethernet switch |
| CN105068961A (en) * | 2015-09-11 | 2015-11-18 | 上海斐讯数据通信技术有限公司 | Ethernet interface management circuit |
| CN105306324A (en) * | 2015-09-22 | 2016-02-03 | 上海斐讯数据通信技术有限公司 | Ethernet multiplexed communication system and Ethernet interface setting method applied to Ethernet multiplexed communication system |
| CN105263071A (en) * | 2015-10-30 | 2016-01-20 | 上海斐讯数据通信技术有限公司 | OLT self-adaptive system and method thereof |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115982086A (en) * | 2023-02-14 | 2023-04-18 | 井芯微电子技术(天津)有限公司 | Chip prototype verification board |
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| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20160831 |
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| RJ01 | Rejection of invention patent application after publication |