CN2886683Y

CN2886683Y - SoC chip with multimedia and network processing function

Info

Publication number: CN2886683Y
Application number: CN 200620033833
Authority: CN
Inventors: 植涌; 王勇; 苟旭; 孙曼
Original assignee: Sichuan University
Current assignee: Sichuan University
Priority date: 2006-04-17
Filing date: 2006-04-17
Publication date: 2007-04-04
Anticipated expiration: 2016-04-17

Abstract

Disclosed is an SoC chipset with the function of multimedia and network processing. The chipset consists of a network interface able to be connected with the internet, a storage controller, an image encoding and decoding device and an embedded CPU kernel. The above components and circuits are interlinked by an on-chip Wishbone bus and controlled and scheduled by the embedded CPU kernel. A high-speed DMA controller, an audio interface, a video interface, a serial interface, a Flash controller, a PCI interface, a 1553B controller, an SPI controller and a PIO controller that are not intervened by the CPU can be added to extend the function of the chipset. Compared with multi-chipset structures, the SoC chipset system runs more reliably and is more convenient to use.

Description

SoC chip with multimedia and network processes function

Technical field

The utility model belongs to the chip with image compression and network remote transfer function, the SoC chip of the integrated designing technique exploitation of particularly a kind of employing SOC (system on a chip) (System On Chip is abbreviated as SoC).

Background technology

The heavy demand of informationized society people to various information satisfied in the combination of multimedia technology and network technology.Developing rapidly of network multimedia technology quickened the multiple network application of multimedia technology, as: video conferencing system, digital video monitor system, rich email, video request program (VOD), remote multi-media database etc.Along with the development of microprocessor technology and the increasingly extensive application of embedded OS, embedded system with its high-speed response, increasingly automated, function is easy to unique advantages such as expansion has become the computer industry new hot-spot for growth.

The most frequently used hardware plan of embedded multimedia system is at present: CPU adds that a DSP constitutes kernel processor chip, wherein DSP finishes encoding and decoding speech, video decompression scheduling algorithm, CPU finishes high-rise consultative management and control function, external physical interfaces such as CODEC, SLIC chip finish communication line connection, external memory chip is used to deposit program and data.Above-mentioned multi-chip structure had both influenced reliability of system operation, also made troubles to use.Because a large amount of appearance of embedded multimedia system have had many companies such as TI, Philips, WINDSPEED, ST to release chipset now or single-chip is realized image compression and network remote transmission, but chipset of being released or single-chip price are higher.

Summary of the invention

The purpose of this utility model is to overcome the deficiencies in the prior art, and a kind of SoC chip with multimedia and network processes function is provided, and this kind chip has image compression and network remote transfer function concurrently, the not only system reliability height of Gou Chenging, and cost performance height.

SoC chip described in the utility model provides soft nuclear and examines dual mode admittedly, adopts verilog HDL language description and design system for soft nuclear, soft nuclear is carried out the optimization of aspects such as resource, speed, sequential, power consumption, forms IP at last and examines admittedly.If the user needs the stone mode, can adopt the hardcopy process of altera company, the SOC chip of similar stone is provided.This chip is equipped with network interface, Memory Controller, the decoding coded image device that is connected with internet and has digital signal processing and the embedded type CPU of JTAG real-time debug function nuclear, above-mentioned device and circuit all interconnect by Wishbone bus in the sheet, and are subjected to the control and the scheduling of embedded type CPU nuclear.

In order to expand its function, also but addition is used to realize not have dma controller, audio interface, video interface, serial line interface, Flash controller, pci interface, 1553B controller, SPI controller, the PIO interface of the high-speed data transfer that CPU intervenes, above-mentioned device and circuit all interconnect by Wishbone bus in the sheet, and are subjected to the control and the scheduling of embedded type CPU nuclear.

The utility model is base chip with the field programmable gate array chip, described embedded type CPU nuclear is based on the openrisc1200 CPU that increases income, improve and optimize its 5 grades of integer track performance, increase the DSP special instruction, increase H.264 codec hardware accelerator, increase JTAG real-time debug function, strengthen the instruction antijamming capability of openrisc1200, and exploitation and integrated multiple peripheral hardware IP are to constitute utility system.Wherein, the ALU of embedded type CPU nuclear utilizes the multiply operation in the hardware multiplier optimization DSP class instruction built-in in the field programmable gate array chip.

The standard of decoding coded image has multiple, for ratio of compression and the compression back image quality that improves image, has selected H.264 decoding coded image standard for use, and has designed and supported the H.264 decoding coded image device of standard.

The utlity model has following beneficial effect:

1, bus on chip adopts the wishbone bus, is convenient to design, and its signal is very direct, can be easy to if desired be adopted by other interface; Wishbone bus full disclosure, free fully is easy to promote.

2, embedded type CPU is optimized and improves with the openrisc1200 prototype, the CPU cost performance is very high and openrisc1200 increases income, and existing successful commerce is used, therefore, employing designs the embedded type CPU of this chip to the improvement of openrisc1200 CPU, and the reliability of CPU is ensured better.

3, SOC chip development described in the utility model and integrated multiple peripheral hardware IP can constitute complete utility system.

4, SOC chip described in the utility model provides soft nuclear and examines dual mode admittedly, soft nuclear is carried out the optimization of aspects such as resource, speed, sequential, power consumption, forms IP at last to examine admittedly, can reach better cost performance,

5, owing to selected H.264 decoding coded image standard for use, and designed and supported the H.264 decoding coded image device of standard, thereby improved the ratio of compression of multi-media image and the image quality after the compression.

6. with respect to multi-chip structure, SOC chip system operation described in the utility model is more reliable, uses more convenient.

Description of drawings

Fig. 1 is a kind of structural representation with SoC chip of multimedia and network processes function described in the utility model;

Fig. 2 is another structural representation with SoC chip of multimedia and network processes function described in the utility model;

Fig. 3 is a kind of structural representation of embedded type CPU nuclear;

Fig. 4 is SoC chip described in the utility model carries out the DMA transmission between peripheral hardware A and peripheral hardware B a synoptic diagram.

Among the figure, 1-Wishbone bus, 2-network interface, 3-embedded type CPU nuclear, 4-Memory Controller, 5-decoding coded image device, 6-DMA controller, 7-audio interface, 8-video interface, 9-serial line interface, 10-Flash controller, 11-PCI interface, 12-1553B controller, 13-SPI controller, 14-PIO interface.

Embodiment

Embodiment 1

The described SoC chip of present embodiment is a base chip with field programmable gate array chip (FPGA), adopt the preparation of SOC (system on a chip) integrated approach, fpga chip can adopt Cyclone, the CycloneII chip (as EP1C20, EP2C35) of U.S. altera company, or U.S. xilinx, lattice company produce chip.

The structure of the described SoC chip of present embodiment is equipped with network interface 2, Memory Controller 4, the decoding coded image device 5 that is connected with internet and has digital signal processing and the embedded type CPU of JTAG real-time debug function nuclear 3 as shown in Figure 1; Decoding coded image device 5 meets H.264 standard, and bus on chip is selected the Wishbone bus for use, and above-mentioned device and circuit all interconnect by Wishbone bus 1 in the sheet, and is subjected to the control and the scheduling of embedded type CPU nuclear 3.The compression and decompression that its decoding coded image device 5 is realized vision signal, network interface is realized the teletransmission of data, the read-write sequence of Memory Controller 4 control external memory storages.

Embedded type CPU nuclear 3 improves on openrisc1200 increases income the basis of CPU and forms, improvements are: optimize 5 grades of integer track performance, increase the DSP special instruction, increase H.264 codec hardware accelerator, increase JTAG real-time debug function, strengthen the instruction antijamming capability of openrisc1200, exploitation and integrated multiple peripheral hardware IP are to constitute utility system.Wherein, the ALU of embedded type CPU nuclear utilizes the multiply operation in the hardware multiplier optimization DSP class instruction built-in in the field programmable gate array chip.The structure of embedded type CPU nuclear comprises Instructions Cache and metadata cache as shown in Figure 3 among the figure, instruction storage management unit and data storage management unit have improved the treatment effeciency of instruction and data greatly; Embedded type CPU nuclear 3 master ports as the wishbone bus, it is by in various of the system bus interface control or the sheet exterior part; Embedded type CPU is examined 3 built-in timers can produce the periodic interruptions signal, to satisfy the time scheduling requirement of operating system; Embedded type CPU is examined 3 built-in debugging interfaces and is met the JTAG standard, for chip provides a kind of means of on-line debugging cheaply.

Embodiment 2

The structure of the described SoC chip of present embodiment as shown in Figure 2, difference from Example 1 is to have set up dma controller 6, audio interface 7, video interface 8, serial line interface 9, Flash controller 10, pci interface 11,1553B controller 12, SPI controller 13 and the PIO interface 14 that is used to realize not have the high-speed data transfer that CPU intervenes, above-mentioned device and circuit all interconnect by Wishbone bus 1 in the sheet, and are subjected to the control and the scheduling of embedded type CPU nuclear 3.Its pci interface 11 is used to connect PCI equipment, realizes the data transmission of this SOC chip and computer PCI bus; The 1553B bus is widely used on aviation testing apparatus and the instrument, by the 1553B controller 12 of this SOC chip, can conveniently connect the testing apparatus of the various 1553B of meeting bus specifications, is convenient to form multi-functional Auto-Test System.This system has also realized the general interface and the controller of some standards on the Wishbone bus, such as IO interface PIO 14 able to programme and SPI controller 13, wherein PIO interface can be used for realizing the control to the User Defined logic, and the SPI controller can be controlled the corresponding interface and connect in the sheet that meets the SPI standard or the sheet exterior part.

Wherein audio interface 7, video interface 8 and serial line interface 9 can transmit by dma mode, can improve the handling capacity of data and the work efficiency of raising embedded type CPU nuclear 3 so greatly.Dma controller 6 has one from port and two master ports, one of them master port is used for finishing data transmission with peripheral hardware A, another master port is used for finishing data transmission with peripheral hardware B, also have one to be used for communicating, make embedded type CPU endorse from port DMA is controlled and manages by this with embedded type CPU nuclear 3 from port.This dma controller inside mainly comprises six registers: two initial address register, two address increment registers, a transmission mode register and a transmission length register.Wherein initial address register is used to preserve the start address of dma mode data transmission, and address increment register is used to be provided with address increment, and (this address increment register is to be unit with the byte, therefore can select 1,2,4, its corresponding 8 respectively, 16 and 32 s' data transmission).Illustrate below in conjunction with Fig. 4 how the described SoC chip of present embodiment carries out data transmission (tentation data reaches peripheral hardware A by peripheral hardware B) by dma mode between peripheral hardware A and peripheral hardware B: at first, embedded type CPU nuclear 3 by it a master port (not marking among the figure) to dma controller 6 initiate communication from port, to the initial address register in the dma controller, address increment register, transmission mode register with transmit length register and carry out corresponding setting; After finishing the configuration to dma controller, embedded type CPU nuclear 3 starts dma controller 6 work; Dma controller 6 need not under 3 interventions of embedded type CPU nuclear then, according to the assigned address reading of data of the setting in the initial address register from peripheral hardware B, the data that read are reached FIFO (first input first output memory) in the dma controller, dma controller 6 is sent to peripheral hardware A by the master port that it links to each other with peripheral hardware A with the data among the FIFO then, in the data transmission procedure, address increment and transmission data length are controlled by address increment register and transmission length register respectively.After transmission was finished, dma controller 6 sent interrupt request by interrupt request singal to embedded type CPU nuclear 3, and a DMA transmission has been finished in expression, and discharges externally if the bus control right of storer.Then, 3 responses of embedded type CPU nuclear are handled interrupt request from the interrupt request of dma controller 6.So far, finish once normal DMA transmission.

Concrete structure of the present utility model is not limited to the foregoing description, can insert electron device, module and circuit according to user's needs.

Claims

1, a kind of SoC chip with multimedia and network processes function, it is characterized in that described chip is equipped with network interface (2), Memory Controller (4), decoding coded image device (5) and the embedded type CPU nuclear (3) that is connected with internet, above-mentioned device and circuit all interconnect by Wishbone bus (1) in the sheet, and are subjected to the control and the scheduling of embedded type CPU nuclear (3).

2, the SoC chip with multimedia and network processes function according to claim 1, it is characterized in that described chip also is equipped with dma controller (6), audio interface (7), video interface (8), serial line interface (9), Flash controller (10), pci interface (11), 1553B controller (12), SPI controller (13), the PIO interface (14) that is used to realize not have the high-speed data transfer that CPU intervenes, above-mentioned device and circuit all interconnect by Wishbone bus (1) in the sheet, and are subjected to the control and the scheduling of embedded type CPU nuclear (3).

3, the SoC chip with multimedia and network processes function according to claim 1 and 2, it is characterized in that with the field programmable gate array chip being base chip, the ALU of embedded type CPU nuclear (3) utilizes the multiply operation in the hardware multiplier optimization DSP class instruction built-in in the field programmable gate array chip.

4, the SoC chip with multimedia and network processes function according to claim 1 and 2 is characterized in that decoding coded image device (5) is for meeting the H.264 decoding coded image device of standard.

5, the SoC chip with multimedia and network processes function according to claim 3 is characterized in that decoding coded image device (5) is for meeting the H.264 decoding coded image device of standard.