CN206258694U - Digital channel machine interface circuit based on CPLD - Google Patents
Digital channel machine interface circuit based on CPLD Download PDFInfo
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- CN206258694U CN206258694U CN201621358045.7U CN201621358045U CN206258694U CN 206258694 U CN206258694 U CN 206258694U CN 201621358045 U CN201621358045 U CN 201621358045U CN 206258694 U CN206258694 U CN 206258694U
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- 230000005540 biological transmission Effects 0.000 claims abstract description 4
- 238000006243 chemical reaction Methods 0.000 abstract description 6
- 238000000034 method Methods 0.000 abstract description 5
- 238000012546 transfer Methods 0.000 abstract description 4
- 238000012827 research and development Methods 0.000 description 6
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Abstract
The utility model discloses a kind of digital channel machine interface circuit based on CPLD, mainly the gate circuit chip by CPLD chips and with ternary output is constituted；The parts of I/O Bank 2 of CPLD are powered using 1.8V, and its I/O interface is used as digital channel machine interface；The parts of I/O Bank 1 are powered using 3.3V, and its I/O interface is used as ARM chip interfaces；Gate circuit with ternary output is used as the passage to digital channel machine transmission data.Timing conversion is carried out to digital channel device communication interface data and ARM communication interface datas by CPLD and interface level is bridged, so as to realize the data transfer communications of ARM chips and digital channel machine.The R＆D cycle in railway 400MHz digital communications radio station is preferably shortened while equipment dependability is preferably ensured using there are technical conditions in the digitized process of railway communication, R＆D costs are saved.
Description
Technical field
The utility model is related to carry out data transmission the digital interface circuit that communicates using ARM chips and digital channel machine,
More particularly to a kind of digital channel machine interface circuit based on CPLD.
Background technology
Current China railways Radio Train Dispatch Communication System is in from 450MHz analog systems to the upgrading of 400MHz digital systems and changes
The stage in generation, the widely used main flow 400MHz digital channels machine of in the market such as XIR M6600 series and XIR M8200 series etc.
The external control communications interface for using is 128 SSI EBIs, and interface level is generally 1.8V.The EBI will be per frame
Data are divided into 8 time slots, and each time slot has 16 data, the time division multiplex to data/address bus realized with this, by preceding 2 buses
Time slot is used as channel device intercommunication, and 6 bus slots communicate with channel device as peripheral control unit and use afterwards.China's iron
Road Radio Train Dispatch Communication System broadcasting station equipment control chip generally uses arm processor, such as LPC1700 series, LPC4300 series at present
Deng arm processor low cost, function admirable uses technology maturation.The SSI EBIs of general ARM chips can for 4-16
Configuration data bus, interface level is generally 3.3V, therefore ARM chips typically cannot be with XIR M6600 series and XIR M8200
The external control interface of the main flow digital channel machine such as series directly enters row data communication.
Can with 128 bit digital channel device SSI EBIs directly enter row data communication processor model it is few, and
Need to set up corresponding software translating environment using the processor chips of new model, then the delay product R＆D cycle, increase research and development
Cost.
The content of the invention
In view of the problem that prior art is present, the purpose of this utility model is to provide a kind of digital channel machine based on CPLD
Interface circuit.This interface circuit is mainly made up of CPLD chips with the gate circuit chip with ternary output；The I/O of CPLD
The parts of Bank 2 are powered using 1.8V, and its I/O interface is used as digital channel machine interface；The parts of I/O Bank 1 are supplied using 3.3V
Electricity, its I/O interface is used as ARM chip interfaces；Gate circuit with ternary output sends the logical of data as to digital channel machine
Road.Timing conversion and interface electricity are carried out to digital channel device communication interface data and ARM communication interface datas by CPLD chips
Level bridge connects, so as to realize the data transfer communications of ARM chips and digital channel machine.
This circuit design is continuing with the arm processors such as LPC1700 series, LPC4300 series as control chip, can
Existing software translating environment and hardware circuit design experience are effectively utilized, greatly shorten the R＆D cycle, save R＆D costs,
And can preferably ensure the reliability of equipment.
The utility model is adopted the technical scheme that：A kind of digital channel machine interface circuit based on CPLD, its feature exists
In：The gate circuit chip of CPLD chips and model 74LV1T125 including model 5M40ZE64I5 with ternary output；Institute
The I/O Bank1 parts energization pins VCCIO1 connections DC3.3V for stating CPLD chips powers, I/O Bank2 parts energization pins
VCCIO2 connections DC1.8V powers；1 pin of CPLD chip Is/O Bank1 parts, 2 pins, 3 pins, 4 pins, 5 pins difference
Connect SSI bus frame synchronization SSP0_FSYNC pins, SSI bus clock SSP0_SCK pins, the SSI bus datas of ARM chips
SSP0_MOSI pins, SSI bus data SSP0_MISO pins, row data communication is entered with ARM chips；CPLD chip Is/O
63 pins of Bank2 parts, 42 pins, 62 pins connect the SSI bus frame synchronization of digital channel machine external control interface respectively
SSI_FSYNC pins, SSI bus clock SSI_SCK pins, SSI bus data SSI_MOSI pins；The I/O of CPLD chips
60 pins of the parts of Bank 2 connect the OE pins of three-state output gate circuit chip, control gate circuit output state；Ternary output
61 pins of input pin A connections CPLD chip Is/O Bank2 parts of gate circuit chip, three-state output gate circuit chip it is defeated
Go out the SSI bus data SSI_MISO pins that pin Y connects digital channel machine external control interface, it is logical as data transfer
Road.
The beneficial effects of the utility model are：Realize the arm processor chips such as LPC1700 series, LPC4300 series with
The data communication of the digital channel machine communication such as XIR M6600 series and XIR M8200 series, so as in the digitlization of railway communication
During preferably using i.e. have technical conditions, preferably ensure equipment dependability while shorten railway 400MHz numeral
The R＆D cycle of communication station, save R＆D costs.
Brief description of the drawings
Fig. 1 is the utility model principle schematic；
Fig. 2 is the utility model data time sequence transition diagram.
Specific embodiment
Understand the utility model in order to clearer, described in detail below in conjunction with drawings and Examples.
As shown in Figure 1 and Figure 2, a kind of digital channel machine interface circuit based on CPLD includes CPLD chips and with tri-state
The gate circuit chip of output, wherein CPLD chips use 5M40ZE64I5N chips, and the gate circuit chip with ternary output is used
74LV1T125 chips.
The I/O Bank1 parts energization pins VCCIO1 connections DC3.3V of CPLD chips powers, and I/O Bank2 parts power
Pin VCCIO2 connections DC1.8V powers；CPLD chip Is/1 pin of O Bank1 parts, 2 pins, 3 pins, 4 pins, 5 pins
SSI bus frame synchronization SSP0_FSYNC pins, SSI bus clock SSP0_SCK pins, the SSI buses of ARM chips are connected respectively
Data SSP0_MOSI pins, SSI bus data SSP0_MISO pins, row data communication is entered with ARM chips；CPLD chip Is/O
63 pins of Bank2 parts, 42 pins, 62 pins connect the SSI bus frame synchronization of digital channel machine external control interface respectively
SSI_FSYNC pins, SSI bus clock SSI_SCK pins, SSI bus data SSI_MOSI pins；The I/O of CPLD chips
60 pins of the parts of Bank 2 connect the OE pins of three-state output gate circuit chip, control gate circuit output state；Ternary output
61 pins of input pin A connections CPLD chip Is/O Bank2 parts of gate circuit chip, three-state output gate circuit chip it is defeated
Go out the SSI bus data SSI_MISO pins that pin Y connects digital channel machine external control interface, it is logical as data transfer
Road.
The design operation principle is described in detail referring to Fig. 1, Fig. 2：The I/O Bank1 parts energization pins of CPLD chips
VCCIO1 connections DC 3.3V power, and the signal level of I/O Bank1 parts I/O pins is 3.3V, and the I/O pins of the part are made
For connection arm processor chip is used；The I/O Bank2 parts energization pins VCCIO2 connection DC 1.8V of CPLD chips are supplied
Electricity, the signal level of I/O Bank2 parts I/O pins is 1.8V, and the I/O pins of the part communicate as connection digital channel machine
Interface is used, so as to realize the signal level bridge joint of arm processor chip and digital channel device communication interface.
In the SSI buses that digital channel machine and arm processor enter row data communication, digital channel machine is main equipment, ARM
Processor is slave unit.The pin 63 of CPLD chips is used as input I/O interface connection digital channel machine communication interface SSI buses
Frame synchronizing signal pin SSI_FSYNC, pin 1,2 is defeated as the external interrupt that output I/O interfaces connect ARM process chips respectively
Enter pin INT0 and SSI bus frame synchronizing signal pin SSP0_FSYNC.CPLD chips carry out the SSI_FSYNC signals of input
The INT0 pins of arm processor are arrived in output after level conversion, used as frame synchronizing signal；Simultaneously in SSI_FSYNC basis of signals
Increase by 7 useful signals in each cycle, the SSI_FSYNC signal periods are divided into 8 parts, that is, corresponding to each time slot has one together
Step signal, output after level conversion to the SSP0_ FSYNC pins of arm processor chip is carried out by the signal, same as time slot
Step signal；The pin 42 of CPLD chips as input clock signal interface connection digital channel machine communication interface SSI buses when
Clock signal pins SSI_SCK, pin 3 connects the SSI bus clock signal pins of ARM process chips as output I/O interfaces
SSP0_SCK.CPLD chips will be input into SSI_SCK signals as itself work clock, while SSI_SCK signals are carried out into electricity
Flat turn exports the SSP0_SCK pins to arm processor after changing, used as SSI bus clock signals.
The pin 62 of CPLD chips is sent out as the data of input I/O interface connection digital channel machine communication interface SSI buses
Pin SSI_MOSI, pin 4 is sent to receive pin SSP0_ as the SSI bus datas of output I/O interface connection ARM process chips
MOSI.Output is drawn to the SSP0_ MOSI of arm processor after the SSI_MOSI data-signals of input are carried out level conversion by CPLD
Pin.
The pin 61,60 of CPLD chips connects the gate circuit chip with ternary output respectively as output I/O interfaces
Input pin A and enable pin OE, pin 5 sends as the SSI bus datas of input I/O interface connection ARM process chips and draws
Pin SSP0_MISO；Gate circuit chip output pin Y connection digital channel machine communication interface SSI buses with ternary output
Data receiver pin SSI_MISO.Door is arrived in output after the SSP0_MISO data-signals of input are carried out level conversion by CPLD chips
The input pin A of circuit chip, at the same every frame SSI bus datas enable pin OE from preceding 2 time slots to gate circuit chip
Output low level signal, gate circuit is output as high-impedance state when making time slot 1, time slot 2, it is to avoid to digital channel device SSI buses when
Gap 1, the data of time slot 2 are interfered；It is defeated to the enable pin OE of gate circuit chip in rear 6 time slots of every frame SSI bus datas
Go out high level signal, time slot 3 to gate circuit during time slot 8 is drawn the data penetration transmission of input to the SSI_MISO of digital channel machine
Pin.
SSI bus configurations are 16 BITBUS networks by arm processor chip, and the frame synchronizing signal using INT0 pins is total to SSI
Data on line carry out framing treatment, you can realize leading to the data of digital channel machine external communication interface by this interface circuit
Letter.
Claims (1)
1. a kind of digital channel machine interface circuit based on CPLD, it is characterised in that：CPLD including model 5M40ZE64I5
The gate circuit chip of chip and model 74LV1T125 with ternary output；The I/O Bank1 parts of the CPLD chips supply
Electric pin VCCIO1 connections DC3.3V powers, and I/O Bank2 parts energization pins VCCIO2 connections DC1.8V powers；CPLD chips
1 pin of I/O Bank1 parts, 2 pins, 3 pins, 4 pins, 5 pins connect the SSI bus frame synchronization of ARM chips respectively
SSP0_FSYNC pins, SSI bus clock SSP0_SCK pins, SSI bus data SSP0_MOSI pins, SSI bus datas
SSP0_MISO pins, row data communication is entered with ARM chips；
CPLD chip Is/63 pins of O Bank2 parts, 42 pins, 62 pins connect digital channel machine external control interface respectively
SSI bus frame synchronization SSI_FSYNC pins, SSI bus clock SSI_SCK pins, SSI bus data SSI_MOSI pins；
60 pins of the parts of I/O Bank 2 of CPLD chips connect the OE pins of three-state output gate circuit chip, control gate circuit
Output state；61 pins of the input pin A connection CPLD chip Is/O Bank2 parts of three-state output gate circuit chip, tri-state
The output pin Y of out-gate circuit chip connects the SSI bus data SSI_MISO pins of digital channel machine external control interface,
As data transmission channel.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201621358045.7U CN206258694U (en) | 2016-12-12 | 2016-12-12 | Digital channel machine interface circuit based on CPLD |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201621358045.7U CN206258694U (en) | 2016-12-12 | 2016-12-12 | Digital channel machine interface circuit based on CPLD |
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| Publication Number | Publication Date |
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| CN206258694U true CN206258694U (en) | 2017-06-16 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201621358045.7U Active CN206258694U (en) | 2016-12-12 | 2016-12-12 | Digital channel machine interface circuit based on CPLD |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106773944A (en) * | 2016-12-12 | 2017-05-31 | 天津七二通信广播股份有限公司 | A kind of digital channel machine interface circuit based on CPLD |
-
2016
- 2016-12-12 CN CN201621358045.7U patent/CN206258694U/en active Active
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106773944A (en) * | 2016-12-12 | 2017-05-31 | 天津七二通信广播股份有限公司 | A kind of digital channel machine interface circuit based on CPLD |
| CN106773944B (en) * | 2016-12-12 | 2023-12-12 | 天津七一二通信广播股份有限公司 | Digital channel machine interface circuit based on CPLD |
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| GR01 | Patent grant | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20210707 Address after: 300140 No. 185, new great road, Tianjin, Hebei District Patentee after: TIANJIN 712 MOBILE COMMUNICATIONS Co.,Ltd. Address before: 300462 Tianjin Binhai New Area Economic and Technological Development Zone West District North Street 141 Patentee before: TIANJIN 712 COMMUNICATION & BROADCASTING Co.,Ltd. |
|
| TR01 | Transfer of patent right | ||
| CP03 | Change of name, title or address |
Address after: 300140 No. 185, new great road, Tianjin, Hebei District Patentee after: Tianjin 712 Mobile Communication Co.,Ltd. Country or region after: China Address before: 300140 No. 185, new great road, Tianjin, Hebei District Patentee before: TIANJIN 712 MOBILE COMMUNICATIONS Co.,Ltd. Country or region before: China |
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| CP03 | Change of name, title or address |