CN104821275A - 半导体元件及其形成方法 - Google Patents

半导体元件及其形成方法 Download PDF

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CN104821275A
CN104821275A CN201510092494.5A CN201510092494A CN104821275A CN 104821275 A CN104821275 A CN 104821275A CN 201510092494 A CN201510092494 A CN 201510092494A CN 104821275 A CN104821275 A CN 104821275A
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CN104821275B (zh
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吴仓聚
章勋明
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

本发明提供半导体元件及其形成方法。一种半导体元件，包括一基底、一金属间介电层覆盖于该基底上、以及一含氮四乙氧基硅烷氧化层或一富含氧四乙氧基硅烷氧化层覆盖于该金属间介电层上。在该富含氧四乙氧基硅烷氧化层中氧的分子比率大于70百分比。该金属间介电层包括一超低介电常数层。一种形成半导体元件的方法，包括：提供一基底；沉积一金属间介电层于该基底上；以及沉积一含氮或富含氧四乙氧基硅烷氧化层于该金属间介电层上。

Description

半导体元件及其形成方法
本申请是中国专利申请200610003186.1的分案申请，原申请CN200610003186.1的申请日是2006年2月22日，发明名称是“半导体元件及其形成方法”。
技术领域
本发明有关于半导体元件，特别有关于一种使用抗水气氧化物覆盖于介电层上的双镶嵌结构，以及其制造方法。
背景技术
在半导体集成电路中常包括数层金属，提供集成电路中各元件间的接触以及集成电路与外部电路的接触。金属间介电层在金属层间使得金属层相互隔离，当金属接点埋置于金属间介电层中并且研磨成一平面结构，该平面结构称为镶嵌结构。当金属间介电层中有金属接点和金属层间内连线(或导孔)形成，此结构称为双镶嵌结构。
具有低介电常数或超低介电常数(ELK)的材料作为金属间介电层时可降低金属层间耦合效应，但是超低介电常数材料有低抗水气问题，在制程中水气被超低介电常数层吸收并使得电子元件效能降低。图1A－图1C说明形成一镶嵌结构100的方法，该结构具有一碳化硅(SiC)层用以保护超低介电常数材料避免水气侵入。
在图1A中，提供一基底102，基底102可包括一形成有元件或电路的半导体基底，第一金属层104形成于基底102上并且埋置于第一介电层106中，蚀刻终止层(ESL)108形成于第一金属层104和第一介电层106上，超低介电常数层110形成于蚀刻终止层108上，第一四乙氧基硅烷(TEOS)氧化层112形成于超低介电常数 层110上，碳化硅层114形成于第一四乙氧基硅烷氧化层112上，第二四乙氧基硅烷氧化层116形成于碳化硅层114上。
在图1B中，第二四乙氧基硅烷氧化层116、碳化硅层114、第一四乙氧基硅烷氧化层112及超低介电常数层110被蚀刻形成一沟槽118，金属阻障层120和金属层122接着沉积于第二四乙氧基硅烷氧化层116上以及沟槽118内，金属阻障层120包括介电质或金属，用以避免金属层122中的金属扩散至下面的其他层，金属层122包括可用作接点的任何适合的金属，例如铜。
在图1C中，使用一化学机械研磨(CMP)步骤移除全部的第二四乙氧基硅烷氧化层116和碳化硅层114，以及部分的第一四乙氧基硅烷氧化层112、金属阻障层120和金属层122。结果在沟槽118内形成第二金属层124和金属阻障126，成为镶嵌结构100。
具有镶嵌结构100的基底102可再进行其他道制程，形成更多的元件或电路。
如上述镶嵌结构100中，四乙氧基硅烷氧化层112和116提供均匀覆盖并且平滑的表面。四乙氧基硅烷氧化层可由化学气相沉积法(CVD)或等离子体增强气相沉积法(PECVD)形成，所使用气体源包括四乙氧基硅烷、氧气及氦气。典型的四乙氧基硅烷的流率大约为560标准立方厘米每分钟(sccm)，氧气的流率大约为840标准立方厘米每分钟，氦气作为载体运输四乙氧基硅烷。化学气相沉积法或等离子体增强气相沉积法的电源功率(source power)大约为375瓦(W)，基底102底部提供的无线电频(RF)功率，即基板偏压功率(bottom power)大约为83瓦。
因为四乙氧基硅烷的抗水气性较差，无法保护超低介电常数层110避免水气侵入，因此采用具有较佳抗水气性的碳化硅114覆盖于四乙氧基硅烷氧化层112和超低介电常数层110上避免水气侵入。然而，碳化硅具有较高介电常数，必须在化学机械研磨步骤 中移除以降低金属层间电容耦合效应。因此，在化学机械研磨步骤之后的制程中，超低介电常数层110无法受到保护，水气还是可能会侵入超低介电常数层110，并且使得元件效能降低。此外，制造四乙氧基硅烷/碳化硅/四乙氧基硅烷(112/114/116)多层结构的制程较为复杂，且碳化硅较难研磨及蚀刻。
发明内容
本发明提供一种半导体元件，包括一基底、一金属间介电层(inter－metal dielectric,IMD)于该基底上以及一含氮四乙氧基硅烷氧化层于该金属间介电层上。
本发明提供另一种半导体元件，包括一基底、一金属间介电层于该基底上以及一富含氧四乙氧基硅烷(tetraethoxysilane,TEOS)氧化层于该金属间介电层上。在该富含氧四乙氧基硅烷氧化层中氧的分子比率(molecular ratio)大于70百分比。
本发明的半导体元件中，该基底包括一形成有元件或电路的半导体基底。
本发明的半导体元件中，该金属间介电层包括一超低介电常数层(extra－low－dielectric－constant,ELK)。
本发明的半导体元件，还包括一金属层覆盖在该基底上，其中该金属间介电层覆盖在该金属层上。
本发明的半导体元件，还包括一沟槽在该含氮或富含氧四乙氧基硅烷氧化层和该金属间介电层中，以及一金属层覆盖在该含氮或富含氧四乙氧基硅烷氧化层上和该沟槽内。
本发明的半导体元件，还包括一金属阻障层在该金属层和该含氮或富含氧四乙氧基硅烷氧化层间，以及该金属层和该金属间介电层间。
本发明还提供一种形成半导体元件的方法，包括：提供一基 底；沉积一金属间介电层于该基底上；以及沉积一含氮或富含氧四乙氧基硅烷氧化层于该金属间介电层上。
本发明的形成半导体元件的方法中，该基底包括一形成有元件或电路的半导体基底。
本发明的形成半导体元件的方法中，该金属间介电层包括一超低介电常数层。
本发明的形成半导体元件的方法，还包括形成一金属层在该基底上，且该金属间介电层覆盖在该金属层上。
本发明的形成半导体元件的方法，还包括蚀刻该含氮或富含氧四乙氧基硅烷氧化层和该金属间介电层形成一沟槽；以及形成一金属层覆盖于该含氮或富含氧四乙氧基硅烷氧化层上和该沟槽内。
本发明的形成半导体元件的方法，还包括形成一金属阻障层在该含氮或富含氧四乙氧基硅烷氧化层上和该沟槽内，且该金属层覆盖于该金属阻障层上。
本发明的形成半导体元件的方法，还包括研磨该金属层、该金属阻障层以及该含氮或富含氧四乙氧基硅烷氧化层。
本发明的形成半导体元件的方法中，沉积该含氮或富含氧四乙氧基硅烷氧化层包括实施一化学气相沉积法(chemical vapor deposition,CVD)或一等离子体增强化学气相沉积法(plasma－enhanced CVD,PECVD)，且沉积该含氮四乙氧基硅烷氧化层使用在氦气载体中的四乙氧基硅烷和氧化亚氮(N2O)为气体源；沉积该富含氧四乙氧基硅烷氧化层使用在氦气载体中的四乙氧基硅烷和氧气为气体源。
本发明的形成半导体元件的方法中，沉积该含氮四乙氧基硅烷氧化层使用的四乙氧基硅烷的流率大约为350标准立方厘米每分钟(sccm)，氧化亚氮的流率大约为1150标准立方厘米每分钟， 电源功率大约为185瓦(W)，基板偏压功率大约为145瓦；沉积该富含氧四乙氧基硅烷氧化层使用的四乙氧基硅烷的流率大约为300标准立方厘米每分钟(sccm)，氧气的流率大约为510标准立方厘米每分钟，电源功率大约为450瓦(W)，基板偏压功率大约为75瓦。
本发明的特征及优点将如以下实施方式所述是显而易见的，或可由本发明的实施已知，本发明的特征及优点可由元件的装置了解并获得，特别是在权利要求书中所指出。
以上简述及以下实施例中详细的说明是作为示范及解释用，本发明更进一步的说明将如权利要求书所示。
附图说明
为了让本发明的上述目的、特征、及优点能更明显易懂，以下配合附图，作详细说明如下：
图1A至图1C所示为一已知具有镶嵌结构的半导体元件其形成的方法。
图2所示为本发明实施例的镶嵌结构。
图3A至图3B所示为本发明实施例的镶嵌结构其形成的方法。
具体实施方式
本发明实施例详细说明如下，其范例如附图所示。在提到相同或相似的部分时，会使用附图中相同的参照数字。
本发明实施例提供一镶嵌结构，包括一高抗水气四乙氧基硅烷氧化物覆盖于一超低介电常数层上。当使用该高抗水气四乙氧基硅烷氧化物时，本发明实施例的镶嵌结构不需要沉积如图1A至图1C所示的四乙氧基硅烷/碳化硅/四乙氧基硅烷(TEOS/SiC/TEOS)多层结构，因此，本发明实施例的镶嵌结构 其制程较简单。
图2所示为本发明实施例的镶嵌结构200，如图2所示，镶嵌结构200形成在一基底202上。基底202可包括一形成有元件或电路的半导体基底。镶嵌结构200包括一第一金属层204形成于基底202上并埋置于一层间介电层(ILD)206内，一蚀刻终止层(ESL)208形成于第一金属层204和层间介电层206上，一超低介电常数层(ELK)210形成于蚀刻终止层208上，超低介电常数层210可作为金属间介电层(IMD)。一四乙氧基硅烷氧化层212形成于超低介电常数层210上，一第二金属层214埋置于四乙氧基硅烷氧化层212和超低介电常数层210内，一金属阻障层216位于第二金属层214和四乙氧基硅烷氧化层212之间，以及第二金属层214和超低介电常数层210之间。金属阻障层216包括介电质或金属，用以避免第二金属层214中的金属扩散至底下数层中。第一金属层204和第二金属层214可包括任何适合做接点用的金属，例如铜。超低介电常数层210可包括介电常数小于2.5，由化学气相沉积法或旋转涂布法形成的材料，例如掺杂碳的二氧化硅(carbon－doped silicon oxide)。
本发明实施例的四乙氧基硅烷氧化层212，相对于传统四乙氧基硅烷具有较高抗水气性，该四乙氧基硅烷氧化层212含氮或含有分子比率超过百分之70的氧。
图3A至图3B说明本发明实施例的镶嵌结构200其形成方法。
在图3A中提供一基底202，沉积一介电层于基底202上形成层间介电层206，在层间介电层206中形成一沟槽(未标号)提供给第一金属层204用。接着，先沉积一层金属然后研磨其表面，第一金属层204就形成于层间介电层206中的沟槽内。蚀刻终止层208形成于第一金属层204和层间介电层206上，超低介电常数层210形成于蚀刻终止层208上，然后四乙氧基硅烷氧化层212沉积于超 低介电常数层210上。
以化学气相沉积法(CVD)或等离子体增强化学气相沉积法(PECVD)，使用在氦气载体中的四乙氧基硅烷(TEOS)和氧化亚氮(N2O)作为气体源，可形成含氮四乙氧基硅烷氧化层作为氧化层212。在气体源中，四乙氧基硅烷的流率大约为350标准立方厘米每分钟(sccm)，氧化亚氮的流率大约为1150标准立方厘米每分钟，化学气相沉积法或等离子体增强化学气相沉积法的电源功率(source power)大约为185瓦，基板偏压功率(bottom power)约为145瓦。
另外，以化学气相沉积法或等离子体增强化学气相沉积法，使用在氦气载体中的四乙氧基硅烷和氧气作为气体源，可形成富含氧四乙氧基硅烷氧化层作为氧化层212。在气体源中，四乙氧基硅烷的流率大约为300标准立方厘米每分钟(sccm)，氧气的流率大约为510标准立方厘米每分钟，化学气相沉积法或等离子体增强化学气相沉积法的电源功率大约为450瓦，基板偏压功率约为75瓦。另外，在富含氧四乙氧基硅烷氧化层212中氧的分子比率大于70百分比。
在图3B中，四乙氧基硅烷氧化层212和超低介电常数层210被蚀刻形成沟槽218，金属阻障层220和金属层222接着沉积于四乙氧基硅烷氧化层212上和沟槽218内。
接着使用化学机械研磨(CMP)步骤，使得四乙氧基硅烷氧化层212、金属阻障层220以及金属层222部分被移除，形成第二金属层214和金属阻障层216在沟槽218内，如图2所示。
由本发明实施例的方法所形成的四乙氧基硅烷氧化层212，不是含氮就是富含氧，并且具有高抗水气性。使用红外线光谱来比较本发明实施例的镶嵌结构与已知镶嵌结构(如上述的镶嵌结构100)，已知镶嵌结构显示出在数个共振频率的水气吸收波峰，包 括：例如3650cm–1[对应氢氧化硅键结键(Si－OH)]以及960cm–1[对应氢氧化硅(Si－OH)与水分子(H2O)键结键]。相反的，本发明实施例的含氮或富含氧四乙氧基硅烷氧化层就没有象征水气吸收的波峰。
本发明实施例置换掉已知镶嵌结构中TEOS/SiC/TEOS多层结构，简化镶嵌结构形成方法并形成同样的结构，降低了镶嵌结构的半导体元件制造成本。
以上所述仅为本发明较佳实施例，然其并非用以限定本发明的范围，任何熟悉本项技术的人员，在不脱离本发明的精神和范围内，可在此基础上做进一步的改进和变化，因此本发明的保护范围当以本申请的权利要求书所界定的范围为准。
附图中符号的简单说明如下：
100、200：镶嵌结构
102、202：半导体基底
104、204：第一金属层
106：第一介电层 
206：层间介电层 
108、208：蚀刻终止层
110、210：超低介电常数层
112：第一四乙氧基硅烷氧化层
212：四乙氧基硅烷氧化层
114：碳化硅层 
116：第二四乙氧基硅烷氧化层
118、218：沟槽
120、220：金属阻障层
122、222：金属层
124、214：第二金属层
126、216：金属阻障。

Claims (15)

1.一种半导体元件，包含：
一基底；
一介电常数小于2.5的金属间介电层于该基底上，其中该金属间介电层的材料包括二氧化硅；
一富含氧四乙氧基硅烷氧化层于该金属间介电层上，其中该富含氧四乙氧基硅烷氧化层中氧的分子比率大于70百分比，该富含氧四乙氧基硅烷氧化层由四乙氧基硅烷和氧气形成；以及
一金属层设置于该富含氧四乙氧基硅烷氧化层及该金属间介电层内，其中该金属层不贯穿该金属间介电层，且该金属层的顶端表面与该富含氧四乙氧基硅烷氧化层的顶端表面共平面。
2.根据权利要求1所述的半导体元件，其中该基底包括一形成有元件或电路的半导体基底。
3.根据权利要求1所述的半导体元件，其中该金属间介电层包括一超低介电常数层，且该超低介电常数层的材料包括掺杂碳的二氧化硅。
4.根据权利要求1所述的半导体元件，还包括一金属层覆盖在该基底上，其中该金属间介电层覆盖在该金属层上。
5.根据权利要求1所述的半导体元件，还包括一沟槽在该富含氧四乙氧基硅烷氧化层和该金属间介电层中，且该金属层覆盖在该富含氧四乙氧基硅烷氧化层上和该沟槽内。
6.根据权利要求5所述的半导体元件，还包括一金属阻障层在该金属层和该富含氧四乙氧基硅烷氧化层间，以及该金属层和该金属间介电层间。
7.一种形成半导体元件的方法，包括：
提供一基底；
沉积一介电常数小于2.5的金属间介电层于该基底上，其中该金属间介电层的材料包括二氧化硅；
沉积一富含氧四乙氧基硅烷氧化层于该金属间介电层上，其中该富含氧四乙氧基硅烷氧化层中氧的分子比率大于70百分比，该富含氧四乙氧基硅烷氧化层由四乙氧基硅烷和氧气形成；以及
形成一金属层在该富含氧四乙氧基硅烷氧化层及该金属间介电层内，其中该金属层不贯穿该金属间介电层，且该金属层的顶端表面与该富含氧四乙氧基硅烷氧化层的顶端表面共平面。
8.根据权利要求7所述的形成半导体元件的方法，其中该基底包括一形成有元件或电路的半导体基底。
9.根据权利要求7所述的形成半导体元件的方法，其中该金属间介电层包括一超低介电常数层，且该超低介电常数层的材料包括掺杂碳的二氧化硅。
10.根据权利要求7所述的形成半导体元件的方法，还包括形成一金属层在该基底上，且该金属间介电层覆盖在该金属层上。
11.根据权利要求7所述的形成半导体元件的方法，还包括蚀刻该富含氧四乙氧基硅烷氧化层和该金属间介电层形成一沟槽，且该金属层覆盖于该富含氧四乙氧基硅烷氧化层上和该沟槽内。
12.根据权利要求11所述的形成半导体元件的方法，还包括形成一金属阻障层在该富含氧四乙氧基硅烷氧化层上和该沟槽内，且该金属层覆盖于该金属阻障层上。
13.根据权利要求12所述的形成半导体元件的方法，还包括研磨该金属层、该金属阻障层以及该富含氧四乙氧基硅烷氧化层。
14.根据权利要求7所述的形成半导体元件的方法，其中沉积该富含氧四乙氧基硅烷氧化层包括实施一化学气相沉积法或一等离子体增强化学气相沉积法，且沉积该富含氧四乙氧基硅烷氧化层使用在氦气载体中的四乙氧基硅烷和氧气为气体源。
15.根据权利要求14所述的形成半导体元件的方法，其中沉积该富含氧四乙氧基硅烷氧化层使用的四乙氧基硅烷的流率为300标准立方厘米每分钟，氧气的流率为510标准立方厘米每分钟，电源功率为450瓦，基板偏压功率为75瓦。
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