CN104765650B

CN104765650B - Data processing equipment

Info

Publication number: CN104765650B
Application number: CN201510009451.6A
Authority: CN
Inventors: 坪井幸利; 长野英生
Original assignee: Renesas Electronics Corp
Current assignee: Renesas Electronics Corp
Priority date: 2014-01-08
Filing date: 2015-01-08
Publication date: 2019-11-29
Anticipated expiration: 2035-01-08
Also published as: EP2894566A1; US20180212629A1; US20170222664A1; JP2015130085A; US10230402B2; US20150194984A1; CN104765650A; KR20150083028A; JP6212396B2; US9935658B2; US9647693B2

Abstract

The present invention relates to a kind of data processing equipments.Data processing equipment including processor and memory has parity check bit/ECC encoder circuit and parity check bit/ECC decoder circuit.Parity check bit/ECC encoder circuit is arranged in the signal path for writing data into, it is written in memory including the parity check bit generating circuit for generating multiple parity check bits from the data to be written, and by parity check bit generated together with the data.Parity check bit/ECC decoder circuit is arranged in for from the signal path of memory read data, and including parity check bit verification unit.Parity check bit generating circuit is configured so that each of the multiple positions for constituting data facilitate the generation of at least two parity check bits.Therefore, parity check bit verification unit can detect two bit-errors at high speed.

Description

Data processing equipment

Cross reference to related applications

The disclosure for the Japanese patent application No.2014-001426 that on January 8th, 2014 submits, including it is specification, attached Figure and abstract are entirely incorporated herein by reference.

Technical field

The present invention relates to a kind of data processing equipments, and more particularly, to can suitable for request high speed operation and The technology of the MCU system of functional safety.

Background technique

In some cases, request MCU (micro controller unit) system meets high speed operation and functional safety.For example, In automobile application field, for the automatic Pilot for realizing advanced driving assistance system (ADAS), judgement MCU (brain core is used Piece).It realizes the extremely high speed operation of high speed processing even if request determines that MCU meets and is operated due to soft error etc. in circuit In the case of, also guarantee the functional safety of the safety of whole system.

Can be executed by combination be more than 1GHz high speed operation CPU (central processing unit) and be such as closely coupled to The high-speed memory of the TCM (tightly-coupled-memory) of CPU or cache memory, constitutes this MCU system.For function Safety can be mounted in the case where there is soft error in high-speed memory, and detection seems in the data as caused by the soft error The mistake of appearance and the mechanism for correcting the mistake.

Patent document 1 discloses the performance equipment with the processor to execution pipeline process and applies the soft of small influence The cache memory device of error correction method.When writing data into data array, adds parity check bit check bit and entangle Error code (ECC) and at the time of reading progress even-odd check bit check.When detecting error in data, pause assembly line, and Interval executes error correction.Patent document 2 discloses the method for the mistake in correcting register file.This method has mistake inspection Survey step and error correction step.When detecting mistake in error detection step, interrupts arithmetic processing and execute error correction step. Patent document 3 discloses single error detection/correction method and patent document 4 discloses error correction device.Detecting odd even In the case where verifying bit-errors, error correction is carried out.Patent document 5 discloses the single error correction of the mistake that can correct even big word length/bis- The error correction circuit of error-detecting method (SEC-DED).Non-patent literature 1 describes for suppression circuit scale while guaranteeing to entangle The generator matrix and check matrix of mistake/detection performance SEC-DEC.

Relevant technical literature

Patent document

Patent document 1: Japanese Unexamined Patent Application Publication No.2011-257966

Patent document 2: International Publication WO 2008/152728

Patent document 3: 1 (1989) -175041 Japanese Unexamined Patent Application Publication No.Hei

Patent document 4: Japanese Unexamined Patent Application Publication No.2013-70122

Patent document 5: 10 (1998) -27139 Japanese Unexamined Patent Application Publication No.Hei

Non-patent literature

Non-patent literature 1:M.Y.Hsiao, " A Class of Optimal Minimum Odd-weight-column SEC-DEC Codes ", IBM Journal of Research and Development, volume 14, the 4th phase, IBM is issued, In July, 1970

Summary of the invention

Present inventor has studied patent document 1 to 5 and non-patent literature 1, thus, it is found that following newly ask Topic.

The error correction being generally used in 1 error correction/2 error correction detection (SEC-DEC) method in above-mentioned known technology etc. The complicated circuit that processing (ECC) circuit is unsuitable for high speed operation or is realized by multistage assembly line.Therefore, such as in patent text It offers described in 1 to 4, proposes when memory is written from processor in data, by the way that in addition to error correcting code (ECC), also addition exists Data are written in parity check bit, carry out even-odd check bit check at the time of reading, and only just execute in the case where mistake occurs The technology of correction process.The even-odd check bit check for being able to achieve high speed operation is only executed when inerrancy occurs by the technology Then it is enough.Due to mistake to actually occur frequency not high, inhibit to cause interference in a pipeline by correction process Frequency.

The parity check bit for being added to error correcting code (ECC) can detect a bit-errors.However, when there are two bit-errors, Parity check bit makes faultless mistake and determines (mistake judgement).When the situation for only detecting mistake in even-odd check bit check Under, when executing 1 error correction/2 dislocation error detection (SEC-DED) methods correction process, it cannot detect the generation of 2 bit-errors. That is, in the presence of in the case where 2 bit-errors occur, by even-odd check bit check, the problem of generation cannot be detected.To solve this Problem, before correction process, instead of parity check bit, it is necessary to execute the error detection processing that can detect 2 bit-errors.However, by In correction process itself be 1 error correction/2 dislocation error detection (SEC-DED) methods, so passing through complicated as correction process Circuit realizes the mechanism of preceding 2 dislocation error detection.In addition, the general parity check position of byte (8) unit the case where Under, the exclusive or for receiving 9 inputs of 8 data and 1 bit parity check position is necessary even-odd check bit check.It was found that the skill Art is not enough to the high speed operation for solving to exceed such as 1GHz.

It finally found that and executed in the MCU system of high speed operation for being more than 1GHz in request, in 1 error correction/2 dislocation erroneous detections Before the correction process of (SEC-DED) method of survey, error detection is executed, it can be in the level-one of such as assembly line, that is, a clock week The 2 bit-errors detection circuit of high speed of interim operation is necessary.

Hereinafter, the means for description being used to solve these problems.From the description of the description and the appended drawings, other problems and Novel feature will become obvious.

Embodiment is as follows.

Embodiment be related to include processor and from processor access memory data processing equipment, and configure such as Under.

The device include be arranged in for by multiple data from processor write-in memory signal path in and By the data being written, the parity check bit generating circuit and parity check bit/ECC of multiple parity check bits are generated Encoder circuit, for memory to be written in data and parity check bit generated.The device be additionally provided with parity check bit/ ECC decoder circuit is arranged in the signal path for being used to, from memory, data be read in processor, and including odd even Check bit verification unit.

Parity check bit generating circuit is configured so that, each for constituting data facilitates at least two odd even schools The generation of position is tested, and parity check bit verification unit is configured to detect the data read from memory and parity check bit In one or two bit-errors in the presence/absence of.

The effect obtained by the embodiment will be summarized as follows.

The present invention provides 2 bit-errors detection circuits, 2 bit-errors mistakenly will not be determined as inerrancy, and can be with The higher speed operation of than 1 error correction/2 dislocation error detection (SEC-DEC) methods correction process, and can be in the side SEC-DEC Error detection is executed before the correction process of method.

Detailed description of the invention

Fig. 1 is the block diagram for showing the configuration example of data processing equipment 100 according to first embodiment.

Fig. 2 is the block diagram for indicating the configuration example of ECC generative circuit 1.

Fig. 3 shows the generator matrix (G) of the ECC realized by ECC generative circuit 1.

Fig. 4 is the block diagram for indicating the configuration example of parity check bit generating circuit 11.

Fig. 5 shows the generator matrix for the parity check bit realized by parity check bit generating circuit 11.

Fig. 6 is the block diagram for indicating parity check bit/ECC decoder circuit 31 configuration example.

Fig. 7 is the block diagram for indicating the more detailed configuration example of ECC decoder circuit 3.

Fig. 8 shows the check matrix (H) of the ECC in ECC decoder circuit 3.

Fig. 9 is the parity check bit/ECC encoder circuit indicated in data processing equipment 100 according to the second embodiment The block diagram of 53 configuration example.

Figure 10 shows the generation for the parity check bit realized by parity check bit generating circuit 54 according to the second embodiment Device matrix.

Figure 11 is the explanatory diagram for showing the concept of the configuration of generator matrix of parity check bit shown in Fig. 10.

Figure 12 is will to be used as part based on the parity check bit of the generator matrix of Figure 10 and generate saying for the state of ECC Bright figure.

Figure 13 is the block diagram for indicating the configuration example of data processing equipment 100 according to the third embodiment.

Figure 14 is the block diagram for indicating parity check bit/ECC encoder circuit 13 configuration example.

Figure 15 shows the generation for the parity check bit realized by parity check bit generating circuit 14 according to the third embodiment Device matrix.

Figure 16 is the explanatory diagram for showing the concept of another configuration of generator matrix of parity check bit shown in Figure 15.

Figure 17 is will to be used as part based on the parity check bit of the generator matrix of Figure 15 and generate saying for the state of ECC Bright figure.

Figure 18 is the block diagram for indicating parity check bit/ECC decoder circuit 22 configuration example.

Figure 19 is the block diagram configured in more detail for indicating ECC decoder circuit 41.

Figure 20 is the block diagram for indicating the configuration example of the data processing equipment 100 according to fourth embodiment.

Figure 21 is shown under the premise of identical with 3rd embodiment, the generator square of applicable another parity check bit Battle array.

Figure 22 shows another example of the generator matrix for the parity check bit that can be used in each of embodiment.

Figure 23 corresponds to the block diagram of the parity check bit generating circuit of the generator matrix of the parity check bit of Figure 22.

Figure 24 shows the another example of the generator matrix for the parity check bit that can be used in each of embodiment.

Figure 25 shows the another example of the generator matrix for the parity check bit that can be used in each of embodiment.

Figure 26 is the explanatory diagram for showing the concept of the configuration of generator matrix of parity check bit shown in Figure 25.

Figure 27 is will to be used as part based on the parity check bit of the generator matrix of Figure 25 and generate saying for the state of ECC Bright figure.

The life of the parity check bit for number of types being used in each embodiment, minimizing parity check bit that Figure 28 is shown It grows up to be a useful person matrix.

Figure 29 is the explanatory diagram for showing the concept of the configuration of generator matrix of parity check bit shown in Figure 28.

Figure 30, which is shown, can wherein be used in each embodiment, another even-odd check of the number of types of minimum parity check bit The generator matrix of position.

Figure 31 is the explanatory diagram for showing the concept of the configuration of generator matrix of parity check bit shown in Figure 30.

Specific embodiment

1. the general introduction of embodiment

Firstly, the general introduction that representative embodiment disclosed herein will be described.It is retouched in the general introduction of representative embodiment The appended drawing reference in figure quoted in the bracket stated only is shown includes in the principle for the component that appended drawing reference is assigned to Content.

[1] the parity check bit addition of 2 bit-errors can be detected

Data processing equipment (100,90) according to disclosed representative embodiment in this application includes processor (30) With memory (51,29a, 29b) and constitute it is as follows.Data processing equipment has the even-odd check of setting in the signal path Position/ECC encoder circuit (13,38e, 52,53), for memory to be written from processor in multiple data and including surprise Even parity bit generative circuit (11,14,20,37e, 54).Data processing equipment further has the surprise of setting in the signal path Even parity bit/ECC decoder circuit (22,31,38d), for will read data from memory reading to processor in, and wrap Include parity check bit verification unit (23,37d, 48).

Parity check bit generating circuit is generated multiple parity check bits by write-in data, and parity check bit is connected With write-in data be written in memory, and constitute write-in data each be configured to facilitate multiple odd even schools Test the generation of at least two parity check bits in position.

Parity check bit verification unit is configured to detect the even-odd check of the reading data and position that read from memory Position one or two mistake in the presence/absence of.

Pass through the configuration, before the error correction of 1 error correction/2 dislocation error detection (SEC-DEC) methods, 2 bit-errors detection circuits It can be operated with speed more higher than error correction to execute error detection.The ability of 2 bit-errors of correction can be provided for error correction.

[2] waiting signal of CPU core

In entry 1, parity check bit/ECC encoder circuit is added to the error correcting code that will correct 1 bit-errors to be write Enter data ECC generative circuit (1,15,55) and parity check bit/ECC decoder circuit have error correction unit (3 to 6, 41,42) it, as executing on the basis of reading data and corresponding to the error correcting code of the reading data, corrects and reads in data The ECC decoder circuit of the correction process of mistake.

Parity check bit/ECC decoder circuit, which is configured to work as, detects the presence of mistake by parity check bit verification unit When, waiting signal can be provided, processor is waited, data are read for receiving, until completing correction process.

By the configuration, when there is an error, it is only possible to produce the expense for correction process.

[3] assembly line is suspended by waiting signal

In entry 2, processor suspends pile line operation on the basis of waiting signal.

Therefore, the operation of processor can safely be stopped.

[4] parallel processing of error detection and error correction

In entry 2, be performed in parallel by parity check bit verification unit, detect mistake in the presence/absence of processing With the correction process by error correction unit.

By the configuration, energy minimization is used for the expense of correction process.

[5] mistake not recoverable (mistake output)

In entry 2, error correction unit, which is configured to can determine that, reads whether the digit of the mistake in data is one or two Position executes correction process, and when the digit of mistake is two when the digit of mistake is one, and error correction is impossible Actual notice processor.

By the configuration, processor can detect the appearance of the mistake in memory beyond error correcting capability (one), and hold Row abnormality processing appropriate.

[6] error correction incapability is interrupted

In entry 5, inform that the impossible fact of error correction is the interrupt requests of processor.

By the configuration, when detecting the mistake for occurring exceeding error correcting capability (one), processor can be executed in appropriate Disconnected processing.

[7] increase the speed (being generated by the parity check bit of the data of a small amount of position) of even-odd check bit check

In entry 1, the two or three-digit of data is written by constituting for parity check bit generating circuit, generates the even-odd check of position Each of position.

By the configuration, parity check bit verification unit can detect at high speed mistake in the presence/absence of.

[8] increase (level-one of XOR) of even-odd check bit check speed

In entry 7, parity check bit generating circuit includes the two or three-digit by constituting write-in data, generates each of position The XOR gate ((12a to 12z, 12A to 12F etc.) of parity check bit.

According to the configuration, by constituting parity check bit verification unit including 3-4 input XOR circuit in parallel, and And can detect at high speed mistake in the presence/absence of.

[9] part and generative circuit are shared in error detection and error correction

In entry 1, parity check bit/ECC encoder circuit has the error correcting code addition for the mistake that will correct one To write-in data ECC generative circuit (1,15,55), and parity check bit/ECC decoder circuit have read data and On the basis of the error correcting code for reading data, the error correction unit (3 for the wrong correction process that correction is read in data is executed To 6,41,42).

ECC generative circuit is configured to by being generated by parity check bit by from the write-in data of memory to be written Multiple parity check bits of circuit evolving are used as part and generate error correcting code.

Parity check bit generating circuit is collectively served as by the circuit of the configuration, a part as ECC generative circuit, because This, saves the scale of necessary circuitry.

[10] in the different memory of two physics, storing data and parity check bit

In entry 1, memory includes the first memory (29a) and parity check bit quilt that data are written and are written into The second memory (29b) of write-in.

By the configuration, in data and parity check bit corresponding to the data, while there is the probability energy of soft error It is regarded as essentially 0.

[11] addition can detect the parity check bit of 2 bit-errors

Data processing equipment (100,90) according to disclosed representative embodiment in this application includes processor (30) With memory (51,29a, 29b) and constitute it is as follows.Data processing equipment include: parity check bit generating circuit (11,14, 20,37e, 54), be arranged on for by multiple write-in data from the signal path of processor write-in memory；And Parity check bit verification unit (23,37d, 48) is arranged on the letter that processor is read for that will read data from memory In number path.

Parity check bit generating circuit generates multiple parity check bits from write-in data, and by the even-odd check Position together with write-in data be written in memory, and constitute write-in data each of multiple be configured to facilitate it is more The generation of at least two parity check bits in a parity check bit.

Parity check bit verification unit is configured to detect the even-odd check of the reading data and position that read from memory Position in, one or 2 mistake in the presence/absence of.

By the configuration, 2 bit-errors detection circuits of energy high speed operation can be provided.

[12] cache memory

In entry 11, data processing equipment further comprises main storage device (39), and the memory is from main memory Store up the cache memory (32) that equipment reads data and interim storing data.

Parity check bit verification unit is configured to detect the mistake from the reading data that cache memory is read Accidentally in the presence/absence of, in the presence of mistake, from main storage device read correspond to read data data and by its It rewrites in the cache.

By the configuration, when occurring soft error in the cache, provides and restore dress instead of the data of error correction It sets.

[13] instruction cache

In entry 12, main storage device is nonvolatile memory (39).

It,, can be high from instruction instead of the Data Recapture Unit of error correction as in the case where soft error occurs by the configuration In speed buffering nonvolatile memory, again from nonvolatile memory speed buffering instruction code.Can provide as a result, has more The system of high security.

2. the details of embodiment

Embodiment will be described in further detail.

First embodiment

Attached drawing will be referred to, the configuration and operation of data processing equipment according to first embodiment are described.

Fig. 1 is the block diagram for showing the configuration of data processing equipment according to first embodiment.Number according to first embodiment Include the exemplary CPU core 30 as processor and the example as memory according to processing unit 100 and closely couples To the high-speed memory (TCM) of CPU core 30.In fig. 1 it is illustrated that the interface circuit of CPU core 30 and TCM51.CPU core 30 With address port, enabling/control port, the port W-DATA, the port R-DATA and the port WAIT-IN, as accessing TCM 51 special purpose interface, and the port CLK-IN that further there is clock (CLK) signal to be provided to and interrupt request singal quilt The port IRQm provided.From CPU core 30 to TCM 51, provide the position n from address port address signal (n indicate from So number) and from enabling/control port memory control signal.Memory control signal is the access for for example enabling TCM 51 Enable signal and indicate read or write-in access type signal.From the port W-DATA, TCM 51 will be written from CPU core 30 Data be outputted as 32 input data d0 to d31.To the port R-DATA, the data read from TCM 31 are provided as 32 The output data d'0 to d'31 of position.In the case where not completing data access in a clock cycle, WAIT signal is supplied to The port WAIT-IN.

Between the above-mentioned special purpose interface 30 and TCM 51 of CPU core, the processing circuit for being suitble to functional safety is provided (circuit related with ECC and parity check bit).TCM 51 includes such as SRAM (static random access memory), including is had (2^n) a address space of the data width of 71 positions.In the number of the data write-in TCM 51 for will be exported from CPU core 30 According in line, providing the parity check bit including parity check bit generating circuit 11 and ECC generative circuit 1/ECC encoder circuit 52.Parity check bit/ECC encoder circuit 52 is by parity check bit generating circuit 11, from input data d0 to d31, generates 32 parity check bit X0 to X31, from input data d0 to d31, generate the ECC of seven positions by ECC generative circuit 11 E0 to E6, and TCM 51 will be supplied to together with the write-in data of 71 positions in total input data D0 to D31.For from TCM51 provides parity check bit/ECC decoder circuit in the data line of the port R-DATA of reading data to CPU core 30 31.By TCM 51, read by the data D0 to D31 of 32 positions, parity check bit X0 to X31 and seven position of 32 positions Reading data of 71 positions in total caused by ECC E0 to E6.From parity check bit/ECC decoder circuit 31, number will be exported The port R-DATA of CPU core 30 is output to according to d'0 to d'31.Parity check bit/ECC decoder circuit 31 by waiting signal and Mistake output signal is respectively outputted to the port WAIN-IN and the port IRQm of CPU core 30.It is odd although being not shown in Fig. 1 Even parity bit/ECC decoder circuit 31 include corresponding to parity check bit generating circuit 11 parity check bit checking circuit and Error correction circuit corresponding to ECC generative circuit 1.Clock signal (CLK signal) is commonly provided to CPU core 30, TCM 51 and surprise Even parity bit/ECC decoder circuit 31.Shown in the digit of signal be example and can suitably change.

The operation of data processing equipment 100 will be described.CPU core 30 is inputted high frequency (such as beyond 1GHz) Each clock cycle of CLK signal, it is sequentially performed the processor circuit of the high speed operation of instruction.CPU core 30 has dedicated In the interface of the memory for the data access in a shortest clock cycle, completing and (reading or be written), and first In the data processing equipment 100 of embodiment, TCM (high-speed memory) 51 is coupled.When CPU core 50 requests TCM 51 that data are written When d0 to d31, parity check bit/ECC encoder circuit 52 from input data d0 to d31, generate parity check bit X0 to X31 and ECC E0 to E6, and TCM 51 is written into together with write-in data D0 to D31 in they.When CPU core 30 requests to read from TCM 51 Access according to d'0 to d'31 when, parity check bit/ECC decoder circuit 31 from TCM 51 read the reading data D0 to D31 and Corresponding to reading the parity check bit X0 that stores of data D0 to D31 to X31 and ECC E0 to E6, and carry out parity check bit school It tests.According to even-odd check bit check result, it is necessary to execute correction process, and output data d'0 to d'31 is output to The port R-DATA of CPU core 30.For some reason, the data access to TCM 51 is not completed within a clock cycle In the case where, with wherein from 30 side output address signal of CPU core and memory control signal the same clock cycle in, from Parity check bit/ECC decoder circuit 31 exports waiting signal.When exporting waiting signal, the pause of CPU core 30 is wherein asserted Assembly line in the period of waiting signal, and the process is restarted from the non-clock cycle.Thus, for example, when from TCM 51 During reading data, when only asserting waiting signal in a clock cycle, CPU core 30 is in following clock cycle, from TCM 51 obtain reading data, therefore, the processing of reading data are executed in two clock cycle.

Parity check bit/ECC encoder circuit 52 concrete configuration example will be described.

Fig. 2 is the block diagram for indicating the configuration example of ECC generative circuit 1.ECC generative circuit 1 is according to generator matrix (G), from input data d0 to d31, error correcting code ECC E0 to E6 is generated as to the circuit of the redundant digit of the error correction of pre-defined algorithm.It is logical It crosses using 7 exclusive or (XOR) circuit 2a-2g, constitutes ECC generative circuit 1.Circuit 2a-2e is 14 input XOR circuits, and 2f and 2g is 13 input XOR circuits.Fig. 3 shows the generator matrix (G) of the ECC realized by ECC generative circuit 1.It is can pass through by The ECC of seven positions is added to 32 data, realizes 1 error correction/2 dislocation error detections and can be with (39,32) of SEC-DED code Check matrix (H) (being shown in Fig. 4 of non-patent literature 1) pairing generator matrix (G) example.In generator column Each column correspond to the position of the position and every a line of input data corresponding to the ECC that will be generated.When by input data d0 to d31 As column vector, when executing matrix multiplication, the column vector of ECC E0 to E6 is generated.

It is expert in each of E0 to E4, including 14 elements " 1 ", is expert in each of E5 and E6, including 13 members Plain " 1 ", and in blank parts, there are element " 0 ".3 elements " 1 " are included in each of column d0 to d31.Due to There are 7 elements in each column, so there are element " 0 " in remaining four blank.It include for element by minimizing The principle of the quantity of " 1 " constitutes generator matrix.32 modes are selected from 35 modes, wherein 3 members in 7 elements Element is " 1 " and four elements are " 0 " and distribute to each column.Not used mode is three modes (1,1,1,0,0,0,0), (0,0,0,1,0,1,1), and (0,0,0,0,1,1,1).

ECC generative circuit 1 is from multiple input datas of the element " 1 " corresponded in generator matrix, by different Or (XOR), each of the position of ECC is generated to generate ECC E0 to E6 from input data d0 to d31 according to generator matrix Circuit.Specifically, by 14 input XOR circuit 2a to 2e, E0 to E4 is generated, and passes through 13 input XOR circuit 2f respectively And 2g, generate E5 and E6.For example, checking the row E0 of the first trip as generator matrix, it should be noted that corresponding to includes element " 1 " 14 column input datas be d0, d1, d2, d3, d4, d5, d6, d7, d14, d19, d22, d24, d30, and d31.To correspond to Its form, by input data d0, the input port for generating the 14 input XOR circuit 2a of E0 is coupled in position those of into d31.

Fig. 4 is the block diagram for indicating the configuration example of parity check bit generating circuit 11.Parity check bit generating circuit 11 wraps Include 32 2 input XOR circuit 12a to 12z and 12A to 12F.Parity check bit generating circuit 11 is for the input number from 32 According to d0 to d31, the circuit of 32 kind of 1 bit parity check position X0 to X31 is generated.Fig. 5 shows the life of 32 kinds of parity check bit X0 to X31 It grows up to be a useful person matrix.It is, from 2 data, to generate showing for the generator matrix of 1 parity check bit with 32 kinds of various combinations Example, that is, 32 parity check bits in total.Position and every a line of each column corresponding to input data in generator matrix Position corresponding to 32 kinds of parity check bits generated.When by input data d0 to d31 be used as generator matrix on column vector, When executing matrix multiplication, the column vector of parity check bit X0 to X31 is generated.

It is expert in each of X0 to X31, including two " 1 " elements and blank parts correspond to depositing for element " 0 " In.By rectangle, it is simple in the form of constituted generator matrix so that in each of column d0 to d31, including two " 1 " elements.

Parity check bit generating circuit 11 be from correspond to generator matrix in element " 1 " two input datas, Each of parity check bit is generated by xor operation from input data d0 to d31, to generate odd according to generator matrix Even parity bit X0 to X31, and specifically, respectively by 2 input XOR circuit 12a to 12F, generate X0 to X31.For example, checking The row X31 of last line as generator matrix, it should be noted that corresponding to the input data that two including element " 1 " arrange is D31 and d0.In the form of corresponding to it, two (d31 and d0) in input data are coupled to the 2 input XOR electricity for generating X31 The input port of road 12F.

Parity check bit/ECC decoder circuit 31 concrete configuration example will be described.

Fig. 6 is the block diagram for indicating parity check bit/ECC decoder circuit 31 configuration example.Parity check bit/ECC solution Code device circuit 31 includes ECC decoder circuit 3, parity check bit checking circuit 48, waits control circuit 19, data switching circuit 46 and AND circuit 47.Parity check bit/ECC decoder circuit 31 receives 32 reading data D0 to D31, ECC from TCM 51 E0 to E6 and parity check bit X0 to X31 and by 32 output data d'0 to d'31, waiting signal and wrong output signal It is output to CPU core 30.ECC E0 to E6 corresponds to read the error correcting code (ECC) of seven positions of data D0 to D31.Odd even school The parity check bit that an X0 to X31 is 32 in total is tested, as 32 kind of 1 bit parity check for corresponding to reading data D0 to D31 Position.Parity check bit/ECC decoder circuit 31 is only it is necessary to generate 32 output data d'0 to d'31, The processing of 1 error correction/2 dislocation error detections is executed on reading data D0 to D31.It later will description error detection and correction process Details.

Parity check bit checking circuit 48 includes such as 32 3 input XOR circuit 49a to 49z and 49A to 49F, and AND circuit 50 (AND circuit that NOT (negative) logic is added to all input ports) with 32 input inversions.With correspond to The form of the check matrix (not shown) of the pairing of parity check bit generator matrix shown in Fig. 5, from reading data D0 to D31 With parity check bit X0 to X31,32 kinds of parity check bit check results y0 to y31 are generated, and generates and is coming from all odd evens The reading data D0 of check bit check results in the case that dislocation-free accidentally occurs, becomes the nerr (inerrancy) of " 1 " into D31 Signal.

Waiting control circuit 19 includes trigger (register) circuit 27a and 27b and the AND circuit with 2 input INV 28.In the first order, nerr (inerrancy) signal is supplied to flip-flop circuit 27a, by the anti-phase output (/Q) and nerr of signal (inerrancy) signal is supplied to the AND circuit with 2 input INV, and generates waiting signal.In the second level, by waiting signal It is supplied to flip-flop circuit 27b, and by the output (Q) of flip-flop circuit 27b, controls data switching circuit 46 and AND circuit 47.When the output (Q) of flip-flop circuit 27b is " 1 " (height), the output of data switching circuit 46 is corrected by ECC decoder circuit 3 Data d'0 to d'31, and when export (Q) be " 0 " (low) when, will from TCM 51 read and bypass ECC decoder circuit 3 Reading data D0 to D31 output be parity check bit/ECC decoder circuit 31 output data d'0 to d'31.Work as trigger When the output (Q) of circuit 27b is " 1 " (height), AND circuit 47 will be exported from the wrong output signal of ECC decoder circuit output For the wrong output signal of parity check bit/ECC decoder circuit 31, and when exporting (Q) is " 0 " (low), mistake is shielded Output signal.

ECC decoder circuit 3 includes syndrome generative circuit 4, syndrome decoding circuit 5 and error correction circuit 6.When detecting When reading data D0 to D31 and ECC E0 into E6 includes 1 bit-errors, by using ECC E0 to E6, data are being read Correction process is executed on D0 to D31, and exports output data d'0 to d'31.When detect read data D0 to D31 and When ECC E0 includes 2 bit-errors into D6, output error output signal.The detailed configuration of ECC decoder circuit 3 will be described later Example and operation.Parity check bit/ECC decoder circuit 31 be only from 32 reading data D0 to D31, correspond to the reading The ECC E0 of seven positions of evidence of fetching to E6 and in total 32 parity check bit X0 to X31 as 32 kinds 1 even-odd check In the case that position becomes necessary to, the output data d'0 to d'31 of 1 error correction/2 dislocation error detections and generation 32 is just executed Circuit.The processing of 1 error correction/2 detection is executed by ECC decoder circuit 3, and (is used via 2 system data switching circuits In 32 data) 46, export the output data of ECC decoder circuit 3.In wherein faultless situation, the switching of 2 system datas Circuit 46 selects the initial read data of itself and exports it.Due to not can be carried out the correction of 2 bit-errors, so detecting In the case where this 2 bit-errors, wrong output signal is output to CPU core 30.In fact, the signal is shielded, only to exist In appropriate situation, exported by 2 input AND circuits 47, and wrong output signal is coupled to the specific interruption of CPU core 30 Input port IRQm (see Fig. 1).

Fig. 7 is the block diagram for showing the configuration of ECC decoder circuit 3.ECC decoder circuit 3 includes syndrome generative circuit 4, syndrome decoding circuit 5, error correction circuit 6 and error signal generating circuit 7.Syndrome generative circuit 4 includes 5 15 inputs XOR circuit 8a to 8e and 2 14 input XOR circuit 8f and 8g and by syndrome code s0 to s6 be supplied to syndrome decoding Circuit 5.Syndrome decoding circuit 5 includes 32 7 importation INV (NOT logic is added only to four input ports) AND circuits Input INV (NOT logic is added to all input ports) the AND circuit 9G of 9a to 9z and 9A to 9F and 7, and by 32 tunnels Errors present mark c0 to c31 is supplied to error correction circuit 6.Error correction circuit 6 includes 32 2 input XOR circuit 10a to 10z and 10A To 10F and error signal generating circuit 7.

Syndrome generative circuit 4 in the first order in ECC decoder circuit 3 is from data D0 is read to D31 and ECC E0 to E6 generates the circuit of correction subcode s0 to s6.Fig. 8 shows the check matrix of ECC.The school of (39,32) SEC-DED code is shown Matrix (H) (shown in Fig. 4 of non-patent literature 1) is tested, the ECC for 32 data and seven positions from 40 in total generates seven A correction subcode, and match ECC generator matrix (G) shown in Fig. 3.Each column of check matrix, which correspond to, reads number According to the position for corresponding to the correction subcode to be generated with each and every a line in ECC.By the way that data D0 to D31 will be read It is used as column vector with ECC E0 to E6, matrix multiplication is executed on check matrix, generates the column vector of correction subcode s0 to s6.

In the check matrix of Fig. 8, from column D0 to the arrangement of the element of column D31 and the generator matrix as a pair of Fig. 3 In column d0 to column d31 element figure it is identical.In the check matrix of Fig. 8, the recognition matrix that 7 rows and 7 are arranged is on right side On, it is added to column E6 from column E0.Therefore, 15 " 1 " elements are included in each of row s0 to s4 and 14 " 1 " first Element is included in each of row s5 and s6.Syndrome generative circuit 4 is from multiple reading data and to correspond to verification The ECC of " 1 " element in matrix generates the circuit of the position of correction subcode by xor operation, so as to according to check matrix, from reading Access, to D31 and ECC E0 to E6, generates correction subcode s0 to s6 according to D0.Specifically, syndrome generative circuit 4 passes through 15 respectively The XOR circuit 8a to 8e of input generates s0 to s4, and generates s5 and s6 by 14 input XOR circuit 8f and 8g respectively.

Syndrome decoding circuit 5 is for verifying the correction subcode s0 to s6 with the output as syndrome generative circuit 4 The circuit of the mode of column in check matrix matched, shown in fig. 8.Pass through the 7 input AND electricity with part INV respectively Road 9a to 9F generates the errors present mark c0 to c31 on 32 tunnels.For example, the mode as first the column D0 in check matrix For (1,0,0,0,0,1,1).In the form of the corresponding mode, in syndrome decoding circuit 5, by syndrome code s1, s2, s3 and S4 be coupled to generation error tick lables c0, with part INV 7 input AND circuit 9a input port in have INV Four input ports, and syndrome code s0, s5 and s6 are coupled to remaining three input ports of not INV.In the presence of Only one of the errors present mark c0 into c31 becomes " 1 ", and means in the corresponding position for reading data D0 to D31, The situation of (that is, value of this of reverse phase) occurs for 1 bit-errors.

In addition, also generating another inerrancy mark cxx by the 7 input AND circuit 9G with INV.For verifying all schools Positive subcode s0 to s6 is " 0 ".In the case where reading data D0 to D31 and ECC E0 does not have bit-errors into E6, Inerrancy mark cxx becomes " 1 ".Naturally, cxx be " 1 " under normal conditions, all checksum location mark c0 on 32 tunnels are extremely C31 becomes " 0 ".If 2 bit-errors occur, then all error bits in any combination of position for reading data D0 to D31 Setting mark c0 to c3 and inerrancy mark cxx becomes " 0 ".

The error correction circuit 6 of afterbody be according to the errors present mark c0 of the output as syndrome decoding circuit 5 extremely The circuit of bit-errors of the data D0 into D31 is read in c31 and inerrancy mark cxx, correction, and in 2 dislocations that cannot be corrected In the case where accidentally occurring, generation error output signal.By accordingly reading corresponding positions and 2 input XOR electricity of the data D0 into D31 Road 10a to 10z and 10A to 10F makes the errors present mark c0 to c31 on 32 tunnels by XOR operation.Reading data D0 to D31 Position in there are 1 bit-errors in the case where, the value reverse phase of position can be made to reset to original calibration value.By all errors present marks Will c0 to c31 and inerrancy mark cxx is both provided to error signal generating circuit 7 and in the case that all values is " 0 ", will " 1 " output is the wrong output signal for notifying 2 bit-errors to occur.Error signal generating circuit 7 can be defeated by such as 33 with INV Enter AND circuit and realizes (NOT logic is added to all input ports).

Read data D0 into D31 dislocation-free accidentally occur in the case where, parity check bit checking circuit 48 by using With the check matrix (not shown) of the pairing of parity check bit generator matrix shown in Fig. 5, the nerr (nothing for becoming " 1 " is generated Mistake) signal.Each column of check matrix correspond to each for reading data and parity check bit, and every a line, which corresponds to, gives birth to At parity check bit check results each, and by by 32 rows and 32 arrange recognition matrix be added to generator matrix Right side, obtain check matrix.Parity check bit checking circuit 48 is from any position of the element " 1 " corresponded in check matrix 2 reading data and 1 parity check bit in setting generate 32 kinds of parity check bit check results by XOR operation Circuit specifically respectively by the XOR circuit 49a to 49F of 3 inputs, generates y0 to y31.For example, being used as odd even school to generating Test the y0 of bit check result 3 input XOR circuit 49a input port, couple read data D0 and D1 and correspond to read The parity check bit X0 of data.

1 bit-errors occur in each of the 2 reading data covered by corresponding parity check bit X0 to X31 In the case where, each of 32 kinds of parity check bit check results y0 to y31 generated becomes " 1 " (that is, the value of position is anti- Phase), and in the case where dislocation-free accidentally occurs, become " 0 ".32 kinds of parity check bit check results y0 to y31 is provided To 32 inputs AND circuit 50 with INV (NOT logic is added to all input ports).The case where all values are " 0 " Under, " 1 " output is indicated that dislocation-free misses the nerr signal occurred.If in 2 readings covered by any parity check bit Access occurs bit-errors (2 bit-errors) in, or if in any one of two readings data 1 bit-errors of appearance, And at the same time occurring bit-errors (1 bit-errors) in one corresponding parity check bit, then parity check bit check results become "0".Therefore, the situation that the situation accidentally occurs with dislocation-free cannot only be distinguished from single parity check bit check results. However, two kinds of parity check bits due to the parity check bit X0 by 32 kinds into X31, the position of data D0 to D31 is read in covering Each, so even if 2 bit-errors as described above etc. hair cannot be verified only from single parity check bit check results It is raw, the generation of 1 bit-errors can be detected by another parity check bit check results.

Such as from Fig. 7 it is understood that can be when the output and 2 14 inputs that can determine that all 5 15 inputs XOR circuit 8a to 8e The output of XOR circuit 8f and 8g, and determine and correct 7 input AND that subcode s0 is provided to s6, with INV with 7 The time point when output of circuit 9g can detect what dislocation-free of the reading data D0 in ECC decoder circuit 3 into D31 was missed Occur.In general, by the way that wherein with the tree-shaped of multistage, multi input XOR circuit is realized in the configurations of 2 input XOR circuits of coupling, so that, Until the processing delay time of the point is considerably long.In the case where 1 bit-errors occur and correct, or occur in 2 bit-errors In the case of, generation error output signal will be for this purpose, will take more time.

On the other hand, parity check bit checking circuit 48 (see Fig. 6) can determine 32 3 input XOR circuit 49a extremely working as 32 inputs that all outputs of 49F and determining 32 parity check bit check results y0 are provided to y31, with INV Time point when the output nerr of AND circuit 50 can detect that reading data D0 dislocation-free into D31 accidentally occurs.3 input XOR The processing delay time of circuit is shorter than the processing delay time of 15 input XOR circuits.Even if due to when the AND circuit with INV 7 inputs when becoming 32 input, so the increase of processing delay time is also fairly small, parity check bit checking circuit 48 can be made In, the detection moment that dislocation-free accidentally occurs is enough earlier than ECC decoder circuit 3.That is, in the CLK letter where the operation of CPU core 30 In one clock cycle of number (being greater than 1GHz) high frequency, it can detect that the dislocation-free for reading data D0 to D31 accidentally occurs.

By the nerr signal " 1 " of the output as parity check bit checking circuit 48, indicate to read data D0 nothing into D31 Bit-errors occur.On the contrary, the nerr signal " 0 " at that time point indicates that reading data D0 occurs 1 bit-errors or 2 into D31 Mistake.Therefore, when 1 bit-errors occur, it is necessary to corrects bit errors.When 2 bit-errors occur, 2 bit-errors are can not correction bit The notice of mistake must be sent to CPU core 30.These processing are executed by ECC decoder circuit 3.Due to processing delay time Shorter than 2 clock cycle, but it is longer than 1 clock cycle, therefore, the processing of CPU core 30 has to postpone only one clock week Phase.

Waiting control circuit 19 is the circuit for generating the waiting signal for waiting the processing of CPU core 30.By surprise Even parity bit checking circuit 48, which detects, there are 1 bit-errors or 2 bit-errors and as the defeated of parity check bit checking circuit 48 In the case that nerr signal out becomes " 0 ", in the same clock cycle, generates until the rising of next CLK signal, be The positive pulse signal of " 1 " and to export be waiting signal.By the input of trigger (register) circuit 27a and 2 with INV AND Circuit 28 is realized.Therefore, CPU core 30 only suspends a clock cycle and restarts the processing in following clock cycle.Therefore, In following clock cycle, by executing the correction output data d'0 to d'31 or conduct that 1 error correction obtains on reading data The wrong output signal of the result of 2 dislocation error detections must be accurately transmitted to CPU core 30.Trigger (register) can be passed through Circuit 27b makes waiting signal only postpone the signal of clock cycle acquisition, the path of 2 system data switching circuits 46 is cut The outlet side of ECC decoder circuit 3 is changed to, and via 2 input AND circuits 47, control will be exported from ECC decoder circuit 3 Signal realize.

As described above, according to first embodiment, by provide in total 32 kinds of parity check bits will pass through 2 kinds of even-odd checks Position, covers each of 32 data, is able to achieve 2 dislocations similar with 1 error correction/2 dislocation error detections of seven position ECC are passed through Error detection.It, can be by using Xiang Qiti by will be from each of minimum number of bits (specifically, 2) increased parity check bit Even-odd check bit check is realized for 32 XOR circuits of a small amount of (specifically, 3) signal, and is able to achieve speed increase.

Second embodiment

Attached drawing will be referred to, the configuration and operation of data processing equipment according to the second embodiment are described.

By by the ECC generative circuit 1 and surprise in the data processing equipment 100 by first embodiment according to figure 1 Even parity bit generative circuit 11 constitute parity check bit/ECC encoder circuit 52 configuration change at integral type odd even Check bit/ECC encoder circuit 53 obtains data processing equipment 100 according to the second embodiment.Parity check bit/ECC decoding Device 31 is substantially the same.

Fig. 9 is the block diagram for indicating parity check bit/ECC encoder circuit 53 configuration example.Parity check bit/ECC is compiled Code device circuit 53 includes parity check bit generating circuit 54 and ECC generative circuit 55.Parity check bit generating circuit 54 includes 16 A 2 input XOR circuit 56a to 56p, 15 2 XOR circuit 57a to 57o and 12 input XOR circuits 58 of input.ECC is generated Circuit 55 includes 77 input XOR circuit 59a to 59g.

Parity check bit/ECC encoder circuit 53 is by parity check bit generating circuit 54, from 32 input datas D0 to d31 generates 32 kind of 1 bit parity check position X0 to X31 and by using parity check bit X0 to X31, generates electricity by ECC Road 55 generates the circuit of seven position ECC E0 to E6.Generator matrix shown in Fig. 3 (G) and ECC check square shown in fig. 8 Battle array (H) mutual corresponding main points are identical with the first embodiment.Although providing the main points and first embodiment of 32 kinds of parity check bits It is identical, but in a second embodiment, use the parity check bit generator matrix for being different from first embodiment shown in Fig. 5.

Figure 10 shows the parity check bit generator matrix of the parity check bit generating circuit 54 in second embodiment.Odd even Check bit generator is configured to that 2 " 1 " elements are included in each of row X0 to X31 and two " 1 " elements are wrapped It includes in each of column d0 to d31, but is different from shown in Fig. 5 and used in first embodiment.32 kinds of parity check bits X0 to X31 is divided into 3 groups: 16 kinds of parity check bit X0 to X15 (first group), 15 kinds of parity check bit X16 to X30 (second group) With a kind of parity check bit X31 (third group).

Parity check bit generating circuit 54 is led to from 2 input datas of the element " 1 " corresponded in generator matrix XOR operation is crossed, parity check bit each is generated, from input data d0 to d31, to generate odd according to generator matrix The circuit of even parity bit X0 to X31.Specifically, parity check bit generating circuit 54 passes through 2 input XOR circuit 56a to 56p, 57a To 57o and 58, X0 to X31 each is generated.Three groups of division is shown.For example, checking as from the top of generator matrix The row X1 for the second row that portion rises, it is to be understood that, the input data for corresponding to two column including element " 1 " is d2 and d5.To correspond to 2 same input data d2 and d5 are coupled to the input port for generating the 2 input XOR circuit 56b of X1 by its form.

ECC generative circuit 55 be for generate correspond to Fig. 3 shown in generator matrix ECC E0 to E6, but just by The parity check bit X0 to X31 that parity check bit generating circuit 54 generates is used as the part and this point that generate ECC, no It is same as first embodiment.To realize it, it is contemplated that the configuration of parity check bit generator matrix shown in Fig. 10.The principle of the configuration As shown in figure 11.The position of the element " 1 " of ECC generator matrix shown in Fig. 3, write-in are indicated by corresponding to the defeated of the position Enter the symbol X0 to X31 for 32 kinds of parity check bit X0 to X31 that the positions of data uses.As first group indicated by bold box Two X0 to X15 include being expert in any two row of E0 to E6.It include being expert at E0 extremely as second group of two X16 to X30 In any one row of E6.In addition, an X31 as third group is included in each of predetermined two row (specifically, row E5 and column d28 and row E6 and column d31).

It understands from Figure 11 by the way that parity check bit X0 to X31 is used as part and ECC E0 to E6 can be generated.ECC is raw It is to pass through XOR operation, phase for from parity check bit X0 to X30 (not including X31) and input data d28 and d31 at circuit 55 Generate the circuit of each of ECC with answering.Figure 12 shows generation state in the matrix form.The matrix is that every a line corresponds to surprise Even parity bit each and it is each column correspond to ECC generated the matrix of each.Readily understand the square of Figure 12 Battle array is arranged in parity check bit generator matrix shown in Fig. 10 side.Specifically, XOR circuit 59a to 59g are inputted by 7 respectively, Generate E0 to E6.7 kind parity check bits of the parity check bit X0 into X30 are coupled to 57 inputs for generating ECC E0 to E4 The input port of XOR circuit 59a to 59e.On the other hand, predetermined parity check bit is coupled to 27 for generating ECC E5 and E6 6 input ports in the input port of XOR circuit 59f and 59g are inputted, and predetermined input data is coupled to residue one Port (d31 of the input of the d28 and 7 XOR circuit 59g of 7 input XOR circuit 59f).

Corresponding to above-mentioned parity check bit/ECC encoder circuit 53 parity check bit/ECC decoder circuit have with In first embodiment, the identical configuration of parity check bit shown in fig. 6/ECC decoder circuit 31, but will just read data D0 extremely It is coupled to difference for the input port of 3 input XOR circuit 49a to 49F of parity check bit checking circuit 48 in position in D31. Coupling corresponds in parity check bit generating circuit 54, and 32 kinds of 2 input XOR circuit 56a are to 56p, 57a to the coupling of 57o and 58 It closes.Wait other configurations and the operation of control circuit 19 and ECC decoder circuit 3 identical as in the case of first embodiment.

According to above-mentioned second embodiment, in the mode similar with first embodiment, by providing 32 kinds of even-odd checks in total Position so as to covered by 2 kinds of parity check bits 32 data each, be able to achieve through seven position ECC, with 1 error correction/2 dislocations 2 similar dislocation error detections of error detection.By generating each parity check bit from less bits (specific, 2) addition, by making With 32 XOR circuits for providing it a small amount of (specifically, 3) signal, even-odd check bit check is realized, and be able to achieve speed increasing Add.

In addition, by the way that 32 kinds of parity check bits generated to be used as part and generate ECC E0 to E6, can reduce ECC The circuit scale of generative circuit 55, and can be shortened processing delay time.

3rd embodiment

Attached drawing will be referred to, the configuration and operation of data processing equipment according to the third embodiment are described.

With regard to parity check bit generated to be used as to the part for generating ECC with for, 3rd embodiment and second embodiment Identical, but be changed to from input data, only one and the parity bit types number generated in ECC is reduced to 25 from 32 kinds Kind.

Figure 13 is the block diagram for indicating the configuration example of data processing equipment according to the third embodiment.According to third embodiment Data processing equipment 100 include as the exemplary CPU core 30 of processor, as the example of memory, closely couple To CPU core 30 high-speed memory (TCM) 29a and 29b, parity check bit/ECC encoder circuit 13 and parity check bit/ ECC decoder circuit 22.Although memory includes a TCM 51 in the data processing equipment 100 of first embodiment, In 3rd embodiment, memory includes two TCM 29a and 29b.TCM 29a is 32 for keeping being handled by CPU core 30 The memory of the data of position (write-in data and read data) itself, and TCM 29b is ECC for keeping seven positions and adjoint The memory of 25 parity check bits of the data.By from CPU 30 address signal and memory control signal mention jointly Supply TCM 29a and 29b.Each of memory is the SRAM of the data width with 32 and (2^n) a address space.Example Such as, TCM 29a and 29b includes the memory with the physics different memory cell array for distributing to same address space.

Figure 14 is the block diagram for indicating parity check bit/ECC encoder circuit 13 configuration example.Parity check bit/ECC is compiled Code device circuit 13 includes parity check bit generating circuit 14 and ECC generative circuit 15.Parity check bit generating circuit 14 includes 6 2 XOR circuit 16a to 16p and 72 input XOR circuit 17a to 17i of input.ECC generative circuit 15 includes 67 input XOR Circuit 18a to 18f and 1 13 input XOR circuit 18g.

Parity check bit/ECC encoder circuit 13 is for passing through parity check bit using parity check bit X0 to X24 Generative circuit 14 generates the circuit of 25 kind of 1 bit parity check position X0 to X24 by 32 input data d0 to d31.Correspond to ECC generator matrix shown in Fig. 3 (G (and the main points of ECC check matrix shown in fig. 8 (H) are implemented with first and second Example is identical.For using the main points of 25 kinds of parity check bits, 3rd embodiment is different from the first and second embodiments.

Figure 15 shows the generator matrix of 25 kinds of parity check bits in 3rd embodiment.Generator matrix is configured to two A " 1 " element include be expert at X0 to X24 each in and substantially, two " 1 " elements include column d0 to d31 it is each In a.As exception, only at the bottom from generator matrix into 14 column that upward arrow indicates (specifically, arrange d0, d1, D3, d4, d8, d9, d10, d11, d17, d20, d23, d25, d27 and d31), the quantity of element " 1 " is 1.By 25 kinds of even-odd checks Position X0 to X24 is divided into 2 groups, and first group is made of 16 kinds of parity check bit X0 to X15 and second group by 9 kinds of parity check bits X16 to X24 composition.

Parity check bit generating circuit 14 be from correspond to generator matrix in element " 1 " two input datas, By XOR operation, each of parity check bit is generated from input data d0 to d31, to generate odd according to generator matrix The circuit of even parity bit X0 to X24.Specifically, by 2 input XOR circuit 16a to 16p, first group of parity check bit X0 is generated To X15, and by 2 input XOR circuit 17a to 17i, generate second group of parity check bit X16 to X24.It makes a living for example, regarding as Grow up to be a useful person matrix first trip row X0, it is to be understood that, correspond to including element " 1 " two column input datas be d0 and d14.With correspondence In its form, two (d0 and d14) in input data are coupled to the input terminal for generating the 2 input XOR circuit 16a of X0 Mouthful.

ECC generative circuit 15 is the circuit for generating the ECC E0 to E6 for corresponding to generator matrix shown in Fig. 3, But the parity check bit X0 to X24 just generated by parity check bit generating circuit 13 is used as wanting for the part sum for generating ECC For point, it is different from first embodiment.To realize it, the configuration of parity check bit generator matrix shown in design drawing 15. The number of types of parity check bit and parity check bit is used, the method for generating ECC is different from second embodiment and Figure 16 and shows The principle of 3rd embodiment.In the position of the element " 1 " of ECC generator matrix shown in Fig. 3, write-in indicates to be somebody's turn to do by corresponding to The symbol X0 to X24 for 25 kinds of parity check bit X0 to X24 that the position of the input data of position uses.As what is indicated by bold box First group of two X0 to X15 include being expert in any two row of E0 to E5.Two X16 to X24 as second group include In any a line of E0 to E5 of being expert at.As exception, X0 to X24 does not occur, but primitive element " 1 " is still expert in E6, similar Ground, primitive element " 1 " are still expert in E5 and column d20.

From Figure 16 it is understood that by the way that parity check bit X0 to X24 to be used as part and generate ECC E0 to E5 and (remove E6 Outside).ECC generative circuit 15 includes for from parity check bit X0 to X24 and input data d20, by XOR operation, correspondingly It generates the circuit of each of ECC and for a part from input data d0 to d31, generates the circuit of ECC E6.Figure 17 shows Generation state in the matrix form out.Matrix is each and each column correspondence that wherein every a line corresponds to parity check bit In the matrix of each of ECC generated.The arranged in matrix for readily understanding Figure 17 is raw in parity check bit shown in figure 15 It grows up to be a useful person matrix side.Specifically, E0 to E5 is generated by 7 input XOR circuit 18a to 18f respectively.Parity check bit X0 is into X24 7 kinds of parity check bits be coupled to the input port for generating 5 kind 7 of ECC E0 to E4 input XOR circuit 18a to 18e.Predetermined surprise Even parity bit is coupled to 6 input ports in the input port for generating the 7 input XOR circuit 18f of ECC E5, and input number It is coupled to remaining a port according to d20.Pass through 13 inputs in the ECC generative circuit 1 with first embodiment shown in Fig. 2 The identical 13 input XOR circuit 18g of XOR circuit 2g only generates ECC E6 directly from a part of input data d0 to d31.

Figure 18 is the block diagram for indicating parity check bit/ECC decoder circuit 22 configuration example.Parity check bit/ECC solution Code device circuit 22, which has, corresponds to above-mentioned parity check bit/ECC encoder circuit 13 function.With regard to parity check bit/ECC decoding Device circuit 22 includes surprise for the main points of ECC decoder circuit 41, parity check bit checking circuit 23 and waiting control circuit 19 Parity check bit/ECC decoder circuit 31 shown in Fig. 6 in even parity bit/ECC decoder circuit 22 and first embodiment Configuration it is similar, but according to the shielding control method and mistake of the difference of parity bit types number and output data d'0 to d'31 It is with missing the difference section of output signal different.

According to the third embodiment includes the even-odd check bit check electricity in parity check bit/ECC decoder circuit 22 Road 23 corresponds to the check matrix (not shown) matched with parity check bit generator matrix shown in figure 15.Parity check bit school Electrical verification road 23 generates 25 kinds of parity check bit check results y0 extremely from data D0 to D31 and parity check bit X0 to X24 is read Y24, and given birth to from all parity check bit check results in the case where into D31, dislocation-free mistake occurs reading data D0 At nerr (inerrancy) signal for becoming " 1 ".Parity check bit checking circuit 23 is from the element corresponded in check matrix 2 reading data and 1 bit parity check position in any position of " 1 " generate 25 kinds of parity check bits by XOR operation The circuit of check results.Specifically, y0 to y24 is generated by 3 input XOR circuit 24a to 24p and 25a to 25i respectively.Example Such as, to the input port of the 3 input XOR circuit 24a of the y0 generated as parity check bit check results, coupling corresponds to data Reading data D0 and D14 and parity check bit X0.

In any one of the 2 reading data covered by corresponding parity check bit X0 to X24, there are 1 bit-errors In the case where, each of 25 kinds of parity check bit check results y0 to y24 generated becomes " 1 ", and misses in dislocation-free Become " 0 " in the case where appearance.25 kinds of parity check bit check results y0 to y24 is supplied to the 25 input AND electricity with INV Road.In the case where all values are " 0 ", " 1 " output is indicated that dislocation-free misses the nerr signal occurred.

If occurring bit-errors (2 bit-errors), odd even in 2 covered by any parity check bit reading data Check bit check results become " 0 ".Therefore, the situation and dislocation-free cannot only be missed from single parity check bit check results The situation of appearance distinguishes.However, due to covering at least any one of 2 reading data by another parity check bit (as exception, the input data d20 and d23 for only covering parity check bit X11 are not covered by another parity check bit).Cause This can be by another odd even even if 2 bit-errors as described above etc. that cannot only detect from single parity check bit inspection occur Check bit check results detect the appearance of 1 bit-errors.

The data and parity check bit X0 to X24 that reading data D0 to D31 is held in TCM 29a are another In TCM 29b, the data that are kept together with ECC E0 to E6.Therefore, the 2 reading data covered by any parity check bit Any one occur 1 bit-errors in (TCM 29a) and occur, meanwhile, there is dislocation in corresponding one parity check bit Accidentally the probability of (1 bit-errors) is considered as essentially 0.

In embodiment, as described above, the input data d20 and d23 that are just coated with parity check bit X11 cover unexceptionally Cover another type of parity check bit.Therefore, although it will be apparent that probability of occurrence is extremely low, exists and only protected in identical TCM 29a D20 and D23 of the reading data D0 held into D31 cannot be by odd even schools in bit-errors (2 bit-errors) occurrent situation Test the weakness that bit check circuit 23 detects 2 bit-errors.However, in fact, being easy to avoid the weakness.

For example, by by one in the position of input data d20 and d23, and selected from input data d0 to d31 another 2 input datas of one generation, it is sufficient to generate another parity check bit X25, and correspond to the generation, in addition use 26th kind of parity check bit check results y25, for generating nerr (inerrancy) letter in parity check bit checking circuit 25 Number.Alternatively, (that is, by three while generation removes any one of 24 kinds of parity check bits for parity check bit X11 Input data only generates the parity check bit), it is sufficient to it is used as extra order for any one of input data d20 and d23.

Wait the configuration and operation of control circuit 19 similar with situation in the first embodiment, except in 3rd embodiment In, the control signal for 2 system data switching circuits 46 being supplied in Fig. 6 is (by making waiting signal only postpone a clock week The signal that phase obtains) it is used as DEC-EN signal to be supplied in ECC decoder circuit 41 independent syndrome decoding circuit.

Figure 19 is the block diagram for indicating the more detailed configuration example of ECC decoder circuit 41.It is real with according to figure 7 second The ECC decoder circuit 3 for applying example is similar, ECC decoder circuit 41 include syndrome generative circuit 4, syndrome decoding circuit 42, Error correction circuit 6 and error signal generating circuit 7.Syndrome generative circuit 4, error correction circuit 6 and error signal generating circuit 7 it is every One same as shown in Figure 7.Syndrome decoding circuit 42 include 32 with part INV 8 input AND circuit 43a to 43z and 43A to 43F (NOT logic is only added to four input ports), (NOT logic is added to institute to the 7 input AND circuits with INV Have input port), INV (NOT) circuit 44 and 2 input OR circuit 45.

DEC-EN signal is supplied to syndrome decoding circuit 42 from waiting control circuit 19.Only when value is " 1 ", make 32 The errors present mark c0 to c31 and inerrancy mark cxx on road are meaningful data.When value is " 0 ", make all errors presents Indicate that c0 to c31 masking is " 0 ", and inerrancy mark cxx is made to be fixed to " 1 ".By the configuration, error correction circuit 6 is only must Operation needed for wanting the moment to execute, so that 2 system data switching circuits 46 and 2 in first embodiment shown in Fig. 6 input AND Circuit 47 becomes unnecessary.

According to above-mentioned 3rd embodiment, in the mode similar with the first and second embodiments, by providing 25 kinds of surprises in total Even parity bit and passes through seven positions so that cover each (being partially exception) of 32 data by 2 kinds of parity check bits ECC, 2 similar dislocation error detections of 1 error correction/2 dislocation error detections become possible.It will be from a few-bit (specifically, 2 by generating Position) addition each parity check bit, can realize odd even school by using 25 XOR of a small number of (specifically, 3) signals are provided Bit check is tested, and is able to achieve speed increase.

In addition, by the way that 25 kinds of parity check bits generated to be used as part and generate ECC (only except E6), can reduce For generating the circuit scale of the circuit of ECC, and it can be shortened processing delay time.

Although in the first and second embodiment using the configuration for increasing by 32 kinds of parity check bits, 3rd embodiment is used The configuration of parity check bit with the number of types for being reduced to 25.Therefore, the capacity of high-speed memory (TCM) can be inhibited, executed The circuit scale and processing delay time for the circuit that even-odd check bit check and parity check bit generate.

Fourth embodiment

The configuration and operation of the data processing equipment according to fourth embodiment will be described with reference to figure.

Figure 20 is the block diagram for indicating the configuration example of the data processing equipment according to fourth embodiment.According to fourth embodiment Data processing equipment be MCU system 90, wherein the error correction method described in first to 3rd embodiment and circuit are answered respectively For high speed operation CPU core and be closely coupled to connecing between CPU core and the TCM (high-speed memory) of speed buffering Mouth circuit.MCU system 90 includes CPU core 30, high-speed memory (TCM) 29a and 29b, command high speed buffer 32, data high-speed Buffering 33, flash memory (code flash memory) 396, general SRAM34, signal processing engine 35 and various peripheral (I/O) circuits.It is general SRAM 34, signal processing engine 35 and various peripheral (I/O) circuits 36 are coupled to CPU 30 via internal bus 40.

Between 29a and 29b, odd even identical with 3rd embodiment school is provided in CPU core 30 and high-speed memory (TCM) Test position/ECC encoder circuit 13 and parity check bit/ECC decoder circuit 22.

It is stored in code flash memory 39 by the instruction code that CPU core 30 sequentially executes.However, being accessed from code flash memory 39 (reading) data costs time so that, provide as can with CPU core 3.0 operate where same high frequency (for example, being more than In one clock cycle of CLK signal 1GHz), the instruction buffer 32 of the high-speed memory of reading data processing is executed.In CPU Between kernel 30 and command high speed buffer 32, provide as the parity check bit generating circuit 37e of interface circuit and even-odd check Bit check circuit 37d.Parity check bit generating circuit 37e is to detect a variety of of 2 bit-errors for generating in addition to 1 bit-errors The circuit of parity check bit, and operate identical as the parity check bit generating circuit 11 in first embodiment shown in Fig. 4 (its parity check bit generator matrix is same as shown in Figure 5).Parity check bit checking circuit 37d is for from parity check bit Type, detect the circuit of the appearance of 1 bit-errors or 2 bit-errors, and its configuration and operation and first embodiment shown in fig. 6 In parity check bit/ECC decoder circuit 31 in parity check bit checking circuit 48 it is identical.In command high speed buffer 32 Instruction code in, in the case that 1 bit-errors or 2 bit-errors occur, be output to CPU core from parity check bit checking circuit 48 30 nerr (inerrancy) signal (not shown) becomes " 0 " and CPU core 30 reads correct finger from code flash memory 39 again It enables code and stores it in command high speed buffer 32 again, thus eliminate the influence of bit-errors.

Can be through internal bus 40, the general SRAM 34 for accessing and (read or be written) data is used as by CPU core 30 The working storage area of processing.However, the time that data access takes a number of clock periods.Therefore it provides as can be at one Clock cycle high speed accesses the data high-speed buffering 33 of the high-speed memory of data.In CPU core 30 and data speed buffering Between 33, the parity check bit as interface circuit/ECC encoder circuit 38e and parity check bit/ECC decoder electricity are provided Road 38d.Odd even school in 3rd embodiment shown in parity check bit/ECC encoder circuit 38c configuration and operation and Figure 14 Test identical (the corresponding parity check bit generator matrix such as Figure 15 of parity check bit generating circuit 14 of position/ECC encoder circuit 13 It is shown).Odd even school in 3rd embodiment shown in parity check bit/ECC decoder circuit 38d configuration and operation and Figure 18 It is identical to test position/ECC decoder circuit.In the case where there are 1 bit-errors in the data stored in data high-speed buffering 33, only In a clock cycle, it is output to CPU core 30 using waiting signal (not shown) as positive pulse signal, and pass through odd even Check bit/ECC decoder circuit 38d, corrects bit errors.In the case where 2 bit-errors occur, wrong output signal (is not shown It is output to CPU core 30 out).

Signal processing engine 35 is the hardware accelerator circuit for the processing for being used to help CPU core 30.Various peripheries (I/O) Circuit 36 is for controlling in MCU system 90, to/various the control circuits from external various input/output end ports.As A kind of circuit is also provided for managing the fault management modules of the various error conditions occurred in the MCU system 90 in lump (not It shows).Therefore, the wrong output signal exported from parity check bit/ECC decoder circuit 22 and 38d is supplied to wrong pipe Manage module.

Other embodiments

It will be described other embodiments (deformation) with reference to figure.

In the first and second embodiment, on condition that the TCM (high-speed memory) for being closely coupled to CPU core includes single Memory.In the first embodiment, unrelated with ECC is generated, generate 32 kinds of parity check bits.In a second embodiment, it is generating After 32 kinds of parity check bits, parity check bit is used as part and generates ECC.In the third embodiment, on condition that close-coupled TCM (high-speed memory) to CPU core includes 2 memories, in one of memory, keeps 32 data, and In another memory, save ECC and the parity check bit with the data, and generate 25 kinds of parity check bits, herein it Afterwards, parity check bit is used as part and generates ECC.Under the premise of identical with 3rd embodiment, moreover it is possible to generate ECC without It closes, generates parity check bit.

Figure 21 shows the example of parity check bit generator matrix.From any two of input data d0 into d31, generate Parity check bit, and 24 kinds of parity check bits in total are provided.With the half of the position of two kinds of parity check bit covering input datas (specifically, d0, d2, d4, d6, d8, d10, d12, d14, d16, d18, d20, d22, d24, d26, d28 and d30), and with only A kind of parity check bit is covered from one subluxation of residue of the bottom of generator matrix indicated to upward arrow.With the simple shape of rectangle Formula constitutes generator matrix, so that other positions for latter parity check bit are covered by another parity check bit.

Even if in 2 covered by any parity check bit reading data while occurring bit-errors (2 bit-errors), by Another parity check bit covers at least one, therefore, 2 bit-errors can be detected by parity check bit checking circuit.Principle with 3rd embodiment is identical.Although by the way that parity check bit to be used as part and generate in the 3rd embodiment of ECC, 25 kinds of odd evens Check bit is necessary, but for the main points that fewer than 25 kinds 1 24 kinds of parity check bits are then enough, and the present embodiment is different.

Figure 22 shows another example of parity check bit generator matrix.22 kinds of parity check bits in total are provided, so as to from Any three of input data d0 to d31 generate parity check bit.Input data d0 to d31 is covered by two kinds of parity check bits In any main points be identical with the first embodiment.However, providing through two kinds of parity check bits, cover by generator matrix Under " * " parity check bit X21 of column d30 for indicating covered by the upward arrow under generator matrix by three kinds of parity check bits Each for only two column (specifically, arranging d0 and d21) that head indicates.Figure 23 is the block diagram of parity check bit generating circuit 20.In In Figure 23, parity check bit generating circuit 20 includes 22 3 input XOR circuit 21a to 21v.Odd even school corresponding to the circuit Testing bit check circuit (not shown) includes 22 4 input XOR circuits and 1 22 input AND circuit with INV.

Figure 24 shows the another example of parity check bit generator matrix, for by appointing from input data d0 into d31 Meaning 3 or 2, generates each parity check bit, provides 28 kinds of parity check bits in total.By two kinds of parity check bits, covering input Each of data d0 into d31.Parity check bit generating circuit (not shown) includes that 83 input XOR circuits and 20 are 2 defeated Enter XOR circuit.Parity check bit checking circuit (not shown) corresponding to circuit includes 84 input XOR circuits, 20 3 inputs XOR circuit and 1 28 input AND circuit with INV.

Figure 25 shows the parity check bit life that parity check bit is generated for any 3 from input data d0 into d31 Grow up to be a useful person the another example of matrix, and by 18 kinds of parity check bits in total generated be used as part and, generate seven position ECC E0 to E6.Based on principle identical with second and third embodiments, and the principle is shown in FIG. 26.ECC shown in Fig. 3 In the position of the element " 1 " of generator matrix, write-in indicates the 18 kinds of odd evens used by the position for the input data for corresponding to position The symbol X0 to X17 of check bit X0 to X17.It include any of E0 to E6 of being expert at as each of first group of 3 X0 to X9 In two rows.It include being expert in any a line of E0 to E6 as each of second group of 3 X10 to X17.It is raw as exception 12 elements (row E4 and column d1 for being surrounded by circle etc.) grown up to be a useful person in matrix remain as " 1 ", as original value.

Understanding from Figure 26 can be by using parity check bit X0 to X17 as part and generation ECC E0 to E6.Figure 27 shows Out in the form of the matrix in ECC circuit (not shown), the generation state of ECC.The arranged in matrix for readily understanding Figure 27 is being schemed Parity check bit generator matrix side shown in 25.Therefore, ECC circuit (not shown) includes 56 input XOR circuits and 25 Input XOR circuit.Parity check bit generating circuit (not shown) includes 18 3 input XOR circuits and even-odd check bit check Circuit (not shown) includes 18 4 input XOR circuits and 1 18 input AND circuit with INV.

In each of above-described embodiment, from a small amount of position in input data, such as two or three-digit is generated relatively a variety of Parity check bit, such as 32 kinds, 28 kinds, 25 kinds, 24 kinds, 22 kinds or 18 kinds simultaneously use.Due to parity check bit checking circuit The XOR circuit of the first order can be by having a small amount of input, and the XOR circuit of such as 3 to 4 inputs is constituted, and priority is given, to shorten Processing delay time.In general, have a large amount of inputs in rear stage, such as 32 to 18 inputs, the processing of AND circuit with INV are prolonged The slow time is not significant, and therefore, the mode of thinking is suitable for increasing the speed of even-odd check bit check.Although shortening parity check bit school The processing delay time on electrical verification road is critically important, but by being reduced as far as even-odd check bit class, reduces and keep even-odd check The capacity of the TCM (high-speed memory) of position is also critically important, and priority is given to the situation of the latter in the presence of request.To solve this One demand, when covering each of input data with 2 kinds or more parity check bits, it is necessary to minimize the kind of parity check bit Class number.

Figure 28 shows the example for realizing above-mentioned parity check bit generator matrix.In this example, from input data d0 to Any 6 or 5 in d31, generate 12 kinds of parity check bits.Figure 29 shows the principle for constituting parity check bit generator matrix. Under the premise of each in the input data for covering 32 with two kinds of parity check bits, using by horizontal parity-check bit and Vertical check position covers the principle of each.By the way that in the two-dimensional array that m row multiplies n column, arrangement input data d0 is extremely D31 generates horizontal parity-check bit, and multiple positions by arranging in each column by the multiple positions arranged in each row, Vertical check position is generated, input data each is covered by two kinds of parity check bits.

Since input data is constituted by 32, it is necessary to meet relationship m × n >=32.Respectively by combining horizontal parity check The number of types for the parity check bit that position and vertical check position obtain is (m+n) kind.Effectively always combination is the possibility of m and n Following five kinds.As m=2 and n=16 (m × n=32), the number of types of parity check bit is 18.As m=3 and n=11 (m × n =33) when, the number of types of parity check bit is 14.As m=4 and n=8 (m × n=32), the number of types of parity check bit is 12.As m=5 and n=7 (m × n=35), the number of types of parity check bit is 12.As m=6 and n=6 (m × n=36), The number of types of parity check bit is 12.There are three kinds of combinations, wherein the number of types of parity check bit is 12 as minimum number Kind.Due to also critically important by each parity check bit of digit generation as few as possible, m=6 and n=6 (m × n will be combined =36) it is considered as best.Arranging arrangement input data d0 to d31 by 6 rows 6, obtaining in Figure 29 in a manner of corresponding to the combination Shown in two-dimensional array.Due to do not have the bit allocation in input data to 2 dimension arrays 36 elements in 4 elements, The position of these elements is sky.From Figure 29, the 6 kinds of horizontal parity-check bit X0 to X5 generated respectively by 6 or 5 can be constituted and divided The 6 kinds of vertical check position X6 to X11 not generated by 6 or 5.Figure 28 is shown in the form of parity check bit generator matrix Out.In this way, the number of types of energy minimization parity check bit.

Under the premise of being made of TCM (high-speed memory) single memory, by covering defeated with 2 kinds of parity check bits Enter each of data, realizes the above-mentioned principle for minimizing the type of parity check bit.Similar principle can also apply to such as exist In 3rd embodiment, TCM (high-speed memory) is constituted by two memories, 32 data are kept in one of memory, And the premise of the parity check bit with the data is kept in another memory.

Figure 30 shows the example for realizing the parity check bit generator matrix of the principle.It is included within odd even shown in Figure 28 Appropriate one of the element " 1 " of position position of the row X0 into X11 in check bit generator matrix is changed to blank so that only by Under generator matrix each of position indicated to upward arrow be covered with a kind of only parity check bit.Figure 31 is shown with this Mode constitutes the principle of parity check bit generator matrix.Since there are 6 kinds of horizontal parity-check bits and 6 kinds of vertical parity schools Position is tested, to all parity check bits, the digit for reducing the input data for generating parity check bit by turn is considered optimal. Therefore, although two-dimensional array seems identical as shown in Figure 29, make to distribute to the bold box table in the two-dimensional array by Figure 31 Each of the input data of the element shown is used for horizontal parity-check bit or vertical check position.From the row in two-dimensional array With column each, reduce and be used for one of parity check bit.Figure 30 is shown in the form of parity check bit generator matrix Array.Despite the presence of only covering the position of its each input data by a kind of parity check bit, but it is used to generate even-odd check All other position of position is covered by other types of parity check bit, it is thus impossible to miss 2 bit-errors.

Although ECC generator matrix shown in Fig. 3 and ECC check matrix shown in fig. 8 (H) are used in above-described embodiment Each in, but the present invention can be applied similarly to the situation using the generator matrix and check matrix different from them. " 1 " can be added to the appropriate location (for example, position of d24) in the E5 and E6 in Fig. 3, therefore, 14 " 1 " are included in In each of all rows of ECC generator matrix.

It present invention may be equally applicable to the situation of any value of the anti-phase input data d0 into d31, after this, generate ECC.It, can be with after the value of any position (for example, d0 and d1) in the input data that reverse phase corresponds to the column of ECC generator matrix Use ECC generator matrix.In this case, in the corresponding way, then it is enough using ECC check matrix.

As shown in figure 13, in the third embodiment, be made of TCM (high-speed memory) two memories: holding will be by CPU The memory 29a of the data (write-in data and read data) of 32 of the processing of kernel 30 itself and keep with the data seven The memory 29b of a ECC and 25 bit parity check positions (in total 32).For covering treatment delay time, until by odd even school Until the ECC generative circuit 15 tested in position/ECC encoder circuit 13 generates ECC E0 to E6, it will be supplied to by delay latter The CLK signal of TCM 29b, the high speed moment.Due within 2 clock cycle, it is sufficient to complete parity check bit/ECC decoder The processing of ECC decoder circuit 41 in circuit 22, accordingly, there exist time enough.It should be noted, however, that parity check bit/ The processing in parity check bit checking circuit 23 and waiting control circuit 19 in ECC decoder circuit 22 must be in a clock It is completed in period.

On the basis of embodiment, the present invention realized by inventor has been specifically described.It may be evident, however, that this Invention is not limited to these embodiments, but without departing substantially from spirit, can differently it change.

For example, the data processing equipment 100 of MCU system 90 etc. can be integrated by what is formed in single semiconductor substrate Circuit (LSI: large scale integrated circuit) is constituted.CPU core 30 can be the processor of any framework, or can change into access Another bus master controller equipment (for example, DMA controller) of memory or cache controller.

Logic circuit shown in for example, is only example, and can be changed to another circuit that can execute equivalent logic operation. Positive logic or negative logic can arbitrarily be used.

Claims

1. a kind of data processing equipment, comprising:

Processor；

Memory；

Parity check bit/ECC encoder circuit, the parity check bit/ECC encoder circuit are arranged on for by multiple positions Write-in data from the signal path that the memory is written in the processor, and including parity check bit generating circuit； And

Parity check bit/ECC decoder circuit, the parity check bit/ECC decoder circuit are arranged on for that will read number According to from the signal path that the memory reads the processor, and including parity check bit verification unit,

Wherein, the parity check bit generating circuit generates the odd even being made of the position of multiple even-odd checks from said write data Check bit, and the parity check bit is written in the memory together with said write data, constitute said write number According to each of multiple positions be configured to facilitate the positions of at least two even-odd checks in the parity check bit It generates, and

Wherein, the parity check bit verification unit is configured to, and is able to detect the reading number read from the memory According to one or two in the parity check bit with the multiple position mistake in the presence/absence of,

Wherein, the parity check bit/ECC encoder circuit includes ECC generative circuit, and the ECC generative circuit will execute 1 The error correcting code of position error correction is added to said write data, and the parity check bit/ECC decoder circuit includes error correction unit, institute Error correction unit is stated based on the reading data and corresponding to the error correcting code for reading data to execute for correcting the reading The correction process of mistake in data,

Wherein, the parity check bit/ECC decoder circuit is configured to, and is detected when by the parity check bit verification unit To mistake there are when, be capable of providing waiting signal to make the reading data to be received such as described processor, until completing institute Until stating correction process,

Be performed in parallel by the parity check bit verification unit carry out detection mistake in the presence/absence of processing and by institute The correction process of error correction unit progress is stated, and

Wherein the parity check bit/ECC decoder circuit is configured to detect two mistakes.

2. data processing equipment according to claim 1, wherein

The processor is based on the waiting signal, to suspend pile line operation.

3. data processing equipment according to claim 1, wherein

The parity check bit generating circuit is by two or three in said write data, to generate the surprise of the multiple position Each of even parity bit.

4. data processing equipment according to claim 3, wherein

The parity check bit generating circuit includes XOR gate, and the XOR gate is from two or three next life in said write data At the parity check bit of each the multiple position.

5. data processing equipment according to claim 1,

Wherein, the parity check bit/ECC encoder circuit has ECC generative circuit, which will correct The error correcting code of one mistake is added to said write data, and the parity check bit/ECC decoder circuit includes error correction list Member, the error correction unit execute the correction reading number based on the reading data and corresponding to the error correcting code for reading data The correction process of mistake in, and

Wherein, the ECC generative circuit is configured to, can be by will be by the parity check bit generating circuit from institute to be written The position for stating the write-in data even-odd check generated of memory is used as partially and to generate the error correcting code.

6. data processing equipment according to claim 1, wherein

The memory includes being written into the first memory of said write data and being written into the parity check bit Second memory.

7. data processing equipment according to claim 1,

Wherein, the parity check bit generating circuit provides the parity check bit, will pass through at least two odd even schools Position is tested to cover each position in said write data.

8. data processing equipment according to claim 1,

Wherein, the parity check bit generating circuit provides the parity check bit, will pass through at least two odd even schools Position is tested to cover each position in said write data, and

Wherein, the parity check bit generating circuit includes XOR gate, and the XOR gate is from least two in said write data A position is come each of the parity check bit that generates multiple.

9. a kind of data processing equipment, comprising:

Processor；

Memory；

Wherein, the parity check bit/ECC decoder circuit is configured to, and is detected when by the parity check bit verification unit To mistake there are when, be capable of providing waiting signal to make the reading data to be received such as described processor, until completing institute Until stating correction process, and

Wherein, the error correction unit is configured to, and can determine that the digit of the mistake in the reading data is one or two Position executes the correction process when the digit of the mistake is one, when the digit of the mistake is two, by error correction Impossible true informing processor.

10. data processing equipment according to claim 9, wherein

The informing of the impossible fact of error correction is the interrupt requests to the processor.

11. a kind of data processing equipment, comprising:

Processor；

Memory；

Parity check bit generating circuit, the parity check bit generating circuit be arranged on for by multiple write-in data from The processor is written in the signal path of the memory；And

Parity check bit verification unit, the parity check bit verification unit are arranged on for that will read data from the storage Device is read in the signal path of the processor,

Wherein, the parity check bit generating circuit generates the surprise being made of the position of multiple even-odd checks from said write data Even parity bit, and the parity check bit is written in the memory together with said write data, and described in composition Each of multiple positions of write-in data are configured to facilitate at least two even-odd checks in the parity check bit The generation of position, and

Wherein, be performed in parallel by the parity check bit verification unit carry out detection mistake in the presence/absence of processing With the correction process carried out by the error correction unit, and

12. data processing equipment according to claim 11 further comprises main storage device,

Wherein, the memory be for data are read from the main storage device and temporarily store the data high speed it is slow Rush memory；And

Wherein, the parity check bit verification unit is configured to, and is able to detect read from the cache memory Be read in data mistake in the presence/absence of, in the presence of mistake, from the main storage device reading correspond to The data for being read data and by the rewriting data in the cache.

13. data processing equipment according to claim 12, wherein the main storage device is nonvolatile memory.

14. data processing equipment according to claim 11,

The parity check bit generating circuit provides the parity check bit, will pass through at least two parity check bits Cover each position in said write data.

15. a kind of data processing equipment, comprising:

Processor；

Memory；

First circuit is arranged on the letter for multiple write-in data to be written to the memory from the processor In number path, and it includes parity check bit generating circuits and error correcting code (ECC) generative circuit；And

Second circuit is arranged on the signal path that the processor is read for that will read data from the memory In, and it includes parity check bit checking circuit and ECC decoder circuit,

Wherein, the parity check bit generating circuit generates the surprise being made of the position of multiple odd-even checks from said write data Even parity bit,

Wherein, each of the multiple positions for constituting said write data are configured to facilitate in the parity check bit extremely The generation of the position of few two even-odd checks,

Wherein, the ECC generative circuit generates ECC from said write data, and the ECC is able to carry out single bit error correction and two Dislocation error detection,

Wherein, the parity check bit and the ECC are written in the memory together with said write data,

Wherein, the reading data and the odd even school that the parity check bit checking circuit detection is read from the memory Test one or two in position mistake in the presence/absence of, to generate the first error signal, and

Wherein, indicate that there are first error signals of the mistake when outputing from the parity check bit checking circuit When, the ECC decoder circuit is wherein executed based on the reading data and the ECC read from the memory to export The second error signal of the reading data or output of single bit error correction, second error signal are indicated described It reads in data and detects two bit-errors.

16. data processing equipment according to claim 15,

Wherein, the second circuit further includes waiting for control circuit, and the waiting control circuit is in response to indicating presence First error signal of the mistake and generate waiting signal, and

Wherein, the processor is based on the waiting signal and suspends pile line operation.

17. data processing equipment according to claim 15,

Wherein, the second circuit further comprises data switching circuit, and the data switching circuit exports the reading data Or the reading data of single bit error correction are wherein performed, and

Wherein, the data switching circuit in response to indicate that there are the corresponding letters of first error signal of the mistake Number select the reading signal for wherein performing single bit error correction.

18. data processing equipment according to claim 15,