JP5510107B2 - Error correction test method - Google Patents

Description

  The present invention relates to an error correction test method.

  A DIMM (Dual Inline Memory Module) is a memory module that can be attached to and detached from a computer via a socket. Some memory modules are compatible with an ECC (Error Correcting Code) function. The ECC-compatible memory module performs error detection and error correction of stored information by cooperating with the ECC-compatible memory controller. In order to verify the operation of the error detection and error correction function, it is necessary to generate a data error in a pseudo manner. Therefore, a predetermined 1 bit in the read data output from the DIMM is clamped to the ground potential. Thereby, the value of the original data can be changed and a data error can be generated in a pseudo manner. By utilizing this pseudo data error, it is possible to test the 2-bit error detection and 1-bit error correction functions of the computer.

  As an example of the ECC inspection using such a pseudo data error, for example, in a memory simulated fault injection apparatus, an adapter that is inserted and connected between a memory control circuit and a memory unit is provided. It has been proposed to include a first circuit that receives an error injection instruction from and a second circuit that injects a data error to the memory unit in accordance with the instruction received by the first circuit.

  In the simulated fault generation device, a match circuit that detects a match between the address of the main memory held in the simulated fault address register and an address that accesses the main memory, and a match between the addresses of the match circuit are detected. It has been proposed to have a pseudo fault generating means for generating a pseudo fault by the output.

  Further, in the storage device, a simulated fault register for setting a simulated fault, an error count set register for indicating the number of occurrences of an error, an output signal of the simulated fault register, and a write / read operation from the system controller An AND gate for obtaining a logical product with the instruction signal, [(maximum error count) -1] multiple diagnostic registers with AND gates connected in series, and an output signal of the error count set register (Maximum number of errors) -1] It is proposed to include an error number selection circuit for selecting one of the output signals, and an error detection circuit for detecting an error from the output signal of the simulated fault register. Has been.

  In addition, in the failure simulation apparatus, an apparatus for testing a digital processing system having tolerance for a failure, and means for detecting an event that is connected to the system and is expected to occur in the system; It has been proposed to include means for injecting a predetermined fault condition into the system in response to the means for detecting.

JP 2004-021922 A JP 60-239838 A JP-A-62-047750 JP 63-027931 A

  As described above, in the error detection and error correction function test of a computer, a data error is generated in a pseudo manner by connecting a predetermined bit in the data output from the memory to the ground potential. Let Therefore, in order to accurately test the error detection and error correction functions of a computer, it is required to generate an accurate data error according to the high-speed operation of the memory.

  An object of the present invention is to execute an error correction test method based on an accurate data error.

The disclosed error correction test method is an error correction test method for a computer having a memory corresponding to error correction, a memory controller having an error correction circuit, and a pseudo failure tool between the memory and the memory controller. In the error correction test method disclosed, the computer writes first data which the first value is set to a particular bit in the first address of the memory, and the said specific bit first The second data set with a second value different from the value is written to the second address of the memory that is continuous with the first address, and the pseudo-fault tool is used to specify the specified data. clamped to the electrode of the memory corresponding to the bit indicating the second value, the computer reads from the memory, successively the first data and the second data, the computer The error correction circuit confirms that the error of the first data is corrected.

  According to the disclosed error correction test method, an accurate data error can be generated even when the operation speed of the memory is high, and the error detection and error correction functions of the computer can be accurately tested. .

It is a figure which shows an example of a structure of a memory test | inspection apparatus. It is explanatory drawing of pseudo generation | occurrence | production of a data error. It is explanatory drawing of pseudo generation | occurrence | production of a data error. It is explanatory drawing of the clamp in the pseudo occurrence of a data error. It is explanatory drawing of a process of a data error. It is a flowchart of a data error simulation generation process. It is explanatory drawing of the pseudo generation | occurrence | production of the data error which this inventor examined. It is explanatory drawing of the process of the data error which this inventor examined. It is explanatory drawing of the pseudo generation | occurrence | production of the data error which this inventor examined. It is explanatory drawing of the process of the data error which this inventor examined. It is explanatory drawing of the pseudo generation | occurrence | production of the data error which this inventor examined. It is explanatory drawing of the process of the data error which this inventor examined. It is explanatory drawing of the pseudo generation | occurrence | production of the data error which this inventor examined.

  The present inventor has examined the case where a conventional error correction test method using a pseudo data error is applied to a DDR SDRAM (Double-Data-Rate Synchronous DRAM). According to the study of the present inventor, when a conventional error correction test method using a pseudo data error is applied to a DDR SDRAM, a pseudo fault is generated as shown in FIGS. .

  7 and 8 show 2-bit error detection and 1-bit error correction when one bit in the read data is not clamped to the ground potential, in other words, when there is no bit clamping operation.

  Actually, FIGS. 7 and 8 show 2-bit error detection and 1-bit error correction when a soft error does not occur when the computer is shipped to the market and actually operated. .

  As shown in FIG. 7, in the burst transfer of the DDR SDRAM, the data string # 11 to the data string # 14 are continuously output at a timing synchronized with the half cycle of the memory clock. At this time, the half cycle of the memory clock and one cycle of data output are shifted by a further half of the cycle of data output. In the period of two memory clocks (two memory clock cycles), four data are output.

  Thereby, in the burst transfer of the DDR SDRAM, the four data strings # 11 to # 14 can be read at both the rising edge of the memory clock and the falling edge of the memory clock. Specifically, the data string # 11 is read in synchronization with the rising edge of the first memory clock, and the data string # 12 is read in synchronization with the falling edge of the first memory clock. The data string # 13 is read in synchronization with the rising edge of the second memory clock, and the data string # 14 is read in synchronization with the falling edge of the second memory clock. The four data strings # 11 to # 14 are continuously read out.

  In FIG. 7, data string # 11 to data string # 14 are represented as “read data”. In FIG. 7, each of data string # 11 to data string # 14 includes 64-bit data and data including 8-bit ECC data.

  As shown in FIG. 8, each of the data strings # 11 to # 14 read from the DIMM is input to the simulated fault tool. In the data sequence # 11 to the data sequence # 14, 64-bit data is represented as “64 bits”, ECC data is represented as “ECC”, and 64-bit data and ECC data is represented as “64 bits + ECC”. . Each of the data string # 11 to the data string # 14 is represented as “64 bits + ECC”. Data string # 21 to data string # 24 are data string # 11 to data string # 14 input to the simulated fault tool.

  If there is no bit clamping operation by the simulated fault tool, the data string # 21 to the data string # 24 are input as they are to the memory controller of the motherboard. Data string # 31 to data string # 34 are data string # 21 to data string # 24 input to the memory controller. The memory controller performs 2-bit error detection and 1-bit error correction using the ECC data included in each of the data strings # 31 to # 34, and 64-bit data in which errors are corrected. Is input to a CPU (Central Processing Unit). Data string # 41 to data string # 44 are data string # 31 to data string # 34 input to the CPU. Data sequence # 41 to data sequence # 44 excludes ECC data and includes only 64-bit data.

  FIGS. 9 and 10 show 2-bit error detection and 1-bit error correction when there is a bit clamp operation for the cases shown in FIGS. In other words, FIG. 9 and FIG. 10 show a case where there is a bit clamp operation for one bit in the read data.

  In practice, FIGS. 9 and 10 show tests performed at the manufacturer before the computer is shipped to the market. This test is one of the evaluations of memory errors in a computer. “One error correction is made for soft errors (only one error) and one error log is reported”. It is a test to confirm.

  As shown in FIG. 9, in the burst transfer of the DDR SDRAM, four data strings # 11 to # 14 are continuously read at both the rising edge of the memory clock and the falling edge of the memory clock. Each of data string # 11 to data string # 14 includes 64-bit data and 8-bit ECC data.

  On the other hand, for example, one predetermined bit in the read data string # 11 is clamped to the ground potential by the bus switch. The 1-bit clamping is performed, for example, by connecting a signal line through which the 1-bit signal in the data bus passes to the ground potential using a bus switch only during the clamping period. As shown in FIG. 9, the clamp period substantially coincides with the period in which the data string # 11 is output. In FIG. 9, the ground potential is indicated by a bold line.

  By this clamping operation, one predetermined bit of the data string # 21 after the clamping operation is set to the ground potential, in other words, “0” regardless of the original value. On the other hand, since the clamp period ends before the next data string # 12 is read, the other data strings # 22 to # 24 are not affected. The data string # 21 to the data string # 24 are illustrated in FIG.

  In FIG. 9, the data after the clamping operation is expressed as “read data after clamping”. In FIG. 9, the read data includes 64-bit data and 8-bit ECC data (64 bits + ECC), whereas the read data after clamping includes the data string # 21 to the data string # 24. , Only a predetermined 1-bit value that has been clamped is shown. In other words, the read data after clamping in FIG. 9 shows only the value of a predetermined 1-bit signal that has passed through the signal line clamped to the ground potential by the bus switch.

  As shown in FIG. 10, each of the data strings # 11 to # 14 read from the DIMM is input to the simulated fault tool. Data string # 21 to data string # 24 are data string # 11 to data string # 14 input to the simulated fault tool.

  Here, as described above, the bit clamping operation by the simulated fault tool is executed. Specifically, for example, in the first data string # 21, as shown in the read data after clamping in FIG. 9, one predetermined bit is clamped to the ground potential regardless of the original data value. The As a result, the data string # 21 includes a 1-bit bit error. In other words, the data string # 21 is simulated fault data including a 1-bit bit error.

  On the other hand, the remaining data strings # 22 to # 24 are read after the end of the clamp period, as shown in the clamp period of FIG. Therefore, the remaining data string # 22 to data string # 24 are not clamped and remain at the original data values as shown in the read data after clamping in FIG. In other words, the remaining data string # 22 to data string # 24 are directly input to the memory controller of the motherboard.

  The memory controller performs 2-bit error detection and 1-bit error correction using the ECC data included in each of the data strings # 31 to # 34, and 64-bit data in which errors are corrected. Is input to the CPU. In other words, the memory controller corrects the 1-bit bit error included in the data string # 31 and generates a corrected data string # 31 '.

  The memory controller inputs the corrected data string # 31 'and data string # 32 to data string # 34 to the CPU. Further, the memory controller reports ECC error # 51 to, for example, a basic input output system (BIOS). In other words, the memory controller reports that the 1-bit bit error of the data string # 31 has been corrected. The BIOS holds the report received from the memory controller as an error log. As a result, as described above, it is confirmed that "one error correction is performed for a soft error (one error only) and one error log is reported" is correctly executed. Is done.

  However, according to the study of the present inventor, when error detection is reproduced by using a conventional pseudo-fault tool in a memory having a higher speed, problems as shown in FIGS. 11 to 13 occur.

  In the states of FIGS. 11 to 13, due to the increase in the memory clock speed, the on / off operation of the bus switch may not be within the output period of the data string # 11 at the current bus switch switching speed. Occurs due to being.

  As shown in FIG. 11, in the burst transfer of the DDR SDRAM, four data strings # 11 to # 14 are continuously read at both the rising edge of the memory clock and the falling edge of the memory clock. On the other hand, for example, one predetermined bit in the read data string # 11 is clamped to the ground potential by the bus switch. By this clamping operation, one predetermined bit of the data string # 21 after the clamping operation is set to the ground potential, in other words, “0” regardless of the original value.

  However, the clamp period is longer than the period during which the data string # 11 is output, as shown in FIG. In FIG. 11, the ground potential is indicated by a bold line. For this reason, the clamp period does not end even when the next data string # 12 is output, in other words, the timing of reading the data string # 22. As a result, also in the data string # 22 read after the data string # 21, a predetermined 1 bit is clamped to the ground potential by the bus switch. By this clamping operation, one predetermined bit of the data string # 22 after the clamping operation is set to the ground potential, in other words, “0” regardless of the original value.

  In FIG. 11, the data after the clamping operation is expressed as “read data after clamping”. In FIG. 11, the read data is data (64 bits + ECC) including 64-bit data and 8-bit ECC data, whereas the read data after clamping is data string # 21 to data string #. At 24, only a predetermined 1-bit value clamped is shown.

  As shown in FIG. 12, each of the data strings # 11 to # 14 read from the DIMM is input to the simulated fault tool. Data string # 21 to data string # 24 are data string # 11 to data string # 14 input to the simulated fault tool.

  Here, as described above, the bit clamping operation by the simulated fault tool is executed. Specifically, for example, in the first data string # 21, as shown in the read data after clamping in FIG. 11, one predetermined bit is clamped to the ground potential. As a result, the data string # 21 includes a 1-bit bit error.

  However, as described above, the clamp period is longer than the period during which the data string # 11 is output, as shown in FIG. 11, and therefore, in the data string # 22 read after the data string # 21, as shown in FIG. As shown in the read data after clamping, one predetermined bit is clamped to the ground potential. As a result, the two data strings # 21 and # 22 contain a 1-bit bit error.

  Therefore, the memory controller corrects the 1-bit bit error included in the data string # 31 and the data string # 32, and generates the corrected data string # 31 'and data string # 32'. Further, the memory controller reports ECC error # 51 and ECC error # 52 to, for example, the BIOS.

  FIG. 13 shows an example of the data string # 11 to data string # 14 read out in the above-described test, and shows a state in which the data string # 11 to data string # 14 are changed by the processing shown in FIGS.

  In FIG. 13, it is assumed that the first 1 bit in the first address of data string # 11 to data string # 14 is clamped to “0”. In FIG. 13, “1” indicates that the data value is high level, “0” indicates that the data value is low level, and “d” indicates that the data value is don't care, In other words, it indicates that the value may be either “1” or “0”.

  In the data string # 11 to the data string # 14, for example, it is assumed that the value of the first 1 bit at the head addresses of the data string # 11 and the data string # 12 is “1”.

  The simulated fault tool clamps the leading 1 bit in the leading address of the data string # 11 to “0” and generates an error only once, in other words, the simulated fault data string # 21. However, as described above, since the operation speed of the bus switch is slow, the first bit in the first address of the data string # 12 is also clamped to “0”. As a result, a simulated fault data string # 22 is generated.

  In response to this, the memory controller detects a bit error for both the data string # 31 and the data string # 32, corrects the detected bit error, and corrects the corrected data string # 31 ′ and data string # 32 ′. Is generated. The memory controller also reports the occurrence of two errors to the BIOS.

  For example, the switching speed of the bus switch is 2.0 to 4.0 ns (nanoseconds), which is the minimum value of the bus enable time. On the other hand, in a DDR SDRAM called so-called DDR3, the frequency of the memory clock is 1066 to 533 MHz. Therefore, one period is 0.9 ns. Therefore, at the normal bus switch switching speed, as shown in FIG. 11, the clamp period by one bus switch exceeds the output period of the data string # 11.

  For this reason, as described above, two bit errors actually occur, and two ECC errors are reported to the BIOS.

  The disclosed error correction test method can generate an accurate data error even when the operation speed of the memory is high, and can accurately test the error detection and error correction functions of the computer.

  FIG. 1 is a diagram illustrating an example of a configuration of a memory inspection device.

  The memory inspection device includes a server 1 and a simulated fault tool 3. The server 1 may be a personal computer, for example. The server 1 has, for example, a DIMM 4 as its main memory. In this embodiment, the DIMM 4 is composed of a plurality of DDR SDRAMs.

  The DIMM 4 is attached to a memory socket on the motherboard of the server 1.

  In FIG. 1, a simulated fault tool 3 is connected between the server 1 and the DIMM 4. Therefore, in this case, the data bus 21, the address bus 22, and the control bus 23 connect the server 1 and the DIMM 4 via the simulated fault tool 3. The control bus 23 is a bus other than the data bus 21 and the address bus 22.

  In the example of FIG. 1, the data bus 21 has a bit width of 64 + 8 = 72 bits, as will be described later. Therefore, data read from the DIMM 4 is 72-bit data. The bit width of data is not limited to this, and may be various values.

  The server 1 includes a CPU 11, a memory controller 17, and a cache memory 19. The CPU 11, memory controller 17 and cache memory 19 are provided on the motherboard of the server 1. The CPU 11 executes an OS (Operating System) 12 and a simulated fault processing program.

  The server 1 includes a disk 5 such as a hard disk device. The disk 5 is provided outside the motherboard of the server 1. The disk 5 stores test data 51. Test data 51 is stored in the disk 5 in advance. The test data 51 has a predetermined bit pattern as will be described later with reference to FIG.

  Test data 51 stored in the disk 5 is stored in the storage area 41 of the DIMM 4. The storage area 41 is a continuous area having a plurality of predetermined addresses. While the OS 12 is operating, various data are stored in the DIMM 4, but such data cannot be used for memory inspection. Therefore, test data 51 having a predetermined bit pattern is stored at a predetermined address. As a result, a test can be executed using the test data 51 having a predetermined bit pattern.

  In the DIMM 4, a program for realizing the OS 12 is stored in the storage area 42. The storage area 42 is a dedicated area for storing a program for realizing the OS 12. In the DIMM 4, the simulated fault processing program is stored in the storage area 43. The storage area 43 is an area for storing various application programs.

  The simulated fault tool 3 generates a simulated fault in the data read from the DIMM 4. The simulated fault tool 3 includes a bus switch 31 and an address determination unit 32. The bus switch 31 is inserted into the data bus 21. A control bus 23 is connected to the bus switch 31. An address bus 22 and a control bus 23 are connected to the address determination unit 32. The address bus 22 and the control bus 23 are connected to the server 1 and the DIMM 4.

  The address determination unit 32 holds, for example, a write command and a read command in advance, compares these with a signal output on the control bus 23, and detects the write command and the read command. For example, the bus switch 31 holds a write command and a read command in advance, and compares these with a signal output on the control bus 23 to detect the write command and the read command.

  When a write command is output from the server 1 to the DIMM 4 via the control bus 23, the address determination unit 32 detects the write command and does not perform address determination. In addition, when a write command is output from the server 1 to the DIMM 4 via the control bus 23, the bus switch 31 detects the write command and sets a switch corresponding to a predetermined bit position to a passing state. Do not clamp. The switches corresponding to the other bit positions are also passed and not clamped. Therefore, in this case, the data written to the DIMM 4 passes through the bus switch 31 and is input to the DIMM 4 as it is.

  When a read command is output from the server 1 to the DIMM 4 via the control bus 23, the address determination unit 32 detects the read command and performs address determination. Further, the bus switch 31 puts a switch corresponding to a predetermined bit position in a clamped state according to the result of the address determination in the address determining unit 32, and does not pass it. Accordingly, in this case, the data read from the DIMM 4, for example, the test data 51 is input to the memory controller 17 with the value of a predetermined bit position changed by clamping.

  The bus switch 31 is connected to the DIMM 4 and includes a switch group. This switch group includes a plurality of switches provided for each bit of data read from the DIMM 4. The plurality of switches will be described later with reference to FIG. Accordingly, the bus switch 31 includes a switch corresponding to a predetermined bit position.

  Each switch is in a clamped state or a passed state. The clamp state is a state in which the output of the switch is clamped to a first value, for example, a second value that is opposite to “1”, for example, “0”. The passing state is a state in which the input of the switch is output as it is.

  The address determination unit 32 holds a predetermined address. The predetermined address is a fixed address. The fixed address is fixedly set in, for example, a register included in the address determination unit 32. As the fixed address, for example, “address 0” is used. The address “address 0” corresponds to the head address in the data string # 11 shown in FIG. The predetermined address may be set from the outside of the simulated fault tool 3 by using, for example, a dip switch.

  When the address determination unit 32 detects a read command, the address determination unit 32 takes in the address output on the address bus 22 in synchronization with the rising edge of the memory clock. The address determination unit 32 detects whether or not the address is a predetermined address by comparing the predetermined address with the fetched address.

  When the address determination unit 32 detects a read command for a predetermined address, the control signal of each switch is sent to the bus switch 31 at a predetermined timing synchronized with the memory clock transferred on the control bus 23. Enter. Thereby, in the bus switch 31, the switch corresponding to the predetermined bit position is switched to the clamped state, and the switch corresponding to the bit position other than the predetermined bit position is kept in the passing state.

  In addition, when the address determination unit 32 does not detect a predetermined address, the control signal of each switch is sent to the bus switch 31 at a predetermined timing synchronized with the memory clock transferred on the control bus 23. input. Thereby, in the bus switch 31, the switch corresponding to the predetermined bit position is switched to the passing state, and the switch corresponding to the bit position other than the predetermined bit position is left in the passing state.

  Here, since the DIMM 4 is composed of the DDR SDRAM, the DIMM 4 synchronizes with the rising edge of the memory clock at a timing delayed by a predetermined time from the memory clock fetching the read command and the address. Starts output.

  On the other hand, when the output of the test data 51 is started from the DIMM 4, as described above, the next data string (second data string # 2) is synchronized with the falling edge of the memory clock at which the output of the test data 51 is started. 12) is output. For this reason, a switch corresponding to a predetermined bit position is set in a clamped state in an output period of a certain data string (data string # 11), and further, prior to output of the next data string (data string # 12). Thus, the switch corresponding to the predetermined bit position cannot be switched to the passing state. This is because the response speed of the switch of the bus switch 31 is slow. The above will be described later with reference to FIG.

  When the power of the server 1 is turned on, the CPU 11 activates the OS 12 and activates the simulated fault processing program.

The CPU 11 loads the test data 51 stored in the disk 5 into the DIMM 4 as the main memory according to the simulated fault processing program. The test data 51 is data having a predetermined data pattern. The load destination address is a predetermined address, in other words, the address of the storage area 41. As a result, test data 51 having a specific data pattern at a specific address is stored in the DIMM 4.
After storing the test data 51, the data string # 11 and the data string # 12 to the data string # 14 stored in the cache memory 19 are expelled from the cache memory 19. Specifically, a predetermined amount of data of the DIMM 4 other than the address storing the test data 51 is referred to.

  Further, the CPU 11 reads the data string # 11 to the data string # 14 from the DIMM 4 via the simulated fault tool 3 according to the simulated fault processing program.

  The CPU 11 requests the memory controller 17 to read data from the DIMM 4 by designating the address of the storage area 41 that is a predetermined address to the memory controller 17 according to the simulated fault processing program. In response to this, the memory controller 17 forms a control signal and an address signal, transmits the control signal to the DIMM 4 via the control bus 23, and transmits the address signal to the DIMM 4 via the address bus 22.

  In response to this, the DIMM 4 reads the test data from the storage area 41 that is the designated address, and transmits it to the memory controller 17 via the data bus 21. At this time, the test data is input to the simulated fault tool 3.

  The simulated fault tool 3 switches the switch corresponding to a predetermined bit position in the bus switch 31 to the clamped state. As a result, the simulated fault tool 3 uses the bus switch 31 to change the first value of a predetermined bit position, for example “1”, into the second value, for example “0”, in the read data string # 11. To generate false fault data for the data string # 11.

  Further, the simulated fault tool 3 switches the switch corresponding to a predetermined bit position in the bus switch 31 from the clamped state to the passing state in parallel with the reading of the data row # 12 to the data row # 14. As a result, the simulated fault tool 3 uses the bus switch 31 to determine in advance when the switch corresponding to the predetermined bit position is in the clamped state in the read data string # 12 to data string # 14. The second value of the assigned bit position, eg “0”, is clamped to the second value, eg “0”. Further, when the switch corresponding to the predetermined bit position is in the passing state, the simulated fault tool 3 passes the second value of the predetermined bit position, for example, “0” as it is. As a result, data string # 12 to data string # 14 are output.

  Specifically, when the address determination unit 32 detects a predetermined address, the bus switch 31 switches the switch corresponding to the predetermined bit position to the clamped state. Thereby, simulated fault data is generated.

  On the other hand, when the address determination unit 32 does not detect a predetermined address, the address determination unit 32 switches the switch corresponding to the predetermined bit position to the passing state. As a result, simulated fault data is not generated. As a result, the data output from the DIMM 4 is input to the memory controller 17 as it is.

  The memory controller 17 executes 2-bit error detection and 1-bit error correction based on the received data in the ECC circuit 18 and inputs the error-corrected data to the CPU 11. Further, the memory controller 17 reports the result of executing 2-bit error detection and 1-bit error correction to, for example, the BIOS 13.

  FIG. 2 is an explanatory diagram of pseudo occurrence of a data error. FIG. 2 shows an example of test data including the data string # 11 to the data string # 14 read in the above-described test, and shows a state in which the data string # 11 to the data string # 14 change. In FIG. 2, “1” indicates that the data value is high level, “0” indicates that the data value is low level, and “d” indicates that the data value is don't care. For example, it indicates that the value may be either “1” or “0”.

  The test data 51 is stored in the DIMM 4 as described above. Test data 51 includes a plurality of data strings # 11 to # 14. Each of the plurality of data strings # 11 to # 14 includes a plurality of bits read in parallel.

  The test data 51 has a predetermined bit pattern. That is, among the plurality of data strings # 11 to # 14, the first data string # 11 has a predetermined first value at a predetermined bit position. Further, among the plurality of data strings # 11 to # 14, at least the second data string # 12 next to the first data string # 11 has the second value at a predetermined bit position. Have.

  The first value is, for example, “1” in binary data, in other words, a high level. The second value is a value obtained by inverting the first value. The second value is, for example, “0” in binary data, in other words, low level.

  The test data 51 includes a data string # 11 that is a first data string, and a data string # 12 to a data string # 14 that are a plurality of second data strings. The data string # 11 is data including a plurality of bits for error detection or error correction, and has a first value, for example, “1” at a predetermined bit position. Each of the data string # 12 to data string # 14 is data that is read after the data string # 11, and includes data including a plurality of bits for error detection or error correction, and is a predetermined bit. The position has a second value, for example “0”.

  For example, the data string # 11 is stored at a predetermined address of the DIMM 4. Data string # 12 to data string # 14 are continuously stored in data string # 11 in DIMM4. In other words, the data string # 11 to the data string # 14 are continuously stored in one predetermined storage area 41.

  Each of the data string # 11 to data string # 14 is written by 8 bits, in other words, 1 byte. An address is assigned for each byte. Therefore, if the address of the first byte of the data string # 11 is “0 address”, the address of the last 1 byte of the data string # 11 is “7 address”. In the data string # 12, the address of the first 1 byte is “8th address”, and the address of the last 1 byte is “15th address”. Since each of the data string # 11 to data string # 14 shown in FIG. 2 is 64 bits, it is data excluding ECC data. Data string # 11 is the first data string and is the data read first. Data string # 12 to data string # 14 are the second data string, and are data read after data string # 11.

  Note that the first bit in the first address of the data string # 11 may be clamped to the power supply potential, in other words, “1 (high level)”. In other words, what is necessary is just to fix to any one value of the binary signal in the server 1.

  The 1 bit clamped to “0” is not limited to the first 1 bit in the first address. Accordingly, 1 bit clamped to “0” may exist at an address other than the head address, or may be 1 bit other than the head 1 bit at any address.

  The test data 51 stored in the DIMM 4 is read by the CPU 11 via the simulated fault tool 3. As a result, the test data 51 is input to the simulated fault tool 3.

  In the simulated fault tool 3, test data including a pseudo error is generated from the test data 51 read from the DIMM 4. In other words, as described below, the first value “1” of the predetermined bit position of the first data string # 11 is changed to the second value “0”.

  Specifically, as described above, in the data string # 11, the head address is a predetermined address. Accordingly, when reading of the data string # 11 is instructed, the address determination unit 32 detects a predetermined address, and the bus switch 31 switches the switch corresponding to the predetermined bit position to the clamped state. It is done. The switch switched from the passing state to the clamped state is again switched to the passing state at the earliest timing of switch switching.

  In the data string # 11 to the data string # 14, for example, in the leading data string # 11, the value of the leading 1 bit at the leading address is “1”, in other words, the value “0” after clamping is inverted. Value. In the data string # 12 to the data string # 14 read after the data string # 11, the value of the first 1 bit at the head address is “0”, in other words, the value equal to the value “0” after clamping. Is done.

  Note that the number of data in which the value of the first 1 bit in the first address is equal to the value “0” after clamping is not limited to three. When the operation speed of the bus switch 31 is about the data reading speed from the DIMM 4, only in the data string # 12 next to the data string # 11, the value of the leading 1 bit at the leading address is set to “0”. You should do so. Therefore, when the value of the leading 1 bit at the leading address in the data string # 11 is clamped to “0”, at least in the next one data string # 12 read continuously in the data string # 11, The value of the first 1 bit in the first address may be a value “0” after clamping.

  On the contrary, the data continuously read in the burst mode is not limited to the four data strings # 11 to # 14. In this case, when the operation speed of the bus switch 31 is considerably slower than the data reading speed from the DIMM 4, for example, in the 4 to 5 data read after the data string # 11, The value of the first 1 bit may be “0”.

  The simulated fault tool clamps the leading 1 bit in the leading address of the data string # 11 to “0” and generates an error only once, in other words, the simulated fault data string # 21. At this time, as described above, since the operation speed of the bus switch 31 is low, the leading 1 bit in the leading address of the data string # 12 is also clamped to “0”. However, the value of the leading 1 bit at the leading address of the data string # 12 is originally “0”. Therefore, even if it is clamped to “0”, the value of the first 1 bit in the first address of the data string # 12 does not change to “0”, and there is no influence of clamping.

  As a result, a simulated fault data string # 22 is generated. The generated simulated fault data string # 22 is equal to the original data string # 22. Therefore, the simulated fault data sequence # 22 is equivalent to not generated. In other words, no bit error is detected in the data string # 32 corresponding to the data string # 22.

  As described above, the test data 51 is read from the DIMM 4 and the value of the predetermined bit position of the first data string # 11 is changed. Thereafter, the test data 51 is input to the memory controller 17. As a result, the test on the DIMM 4 is executed using the test data 51 in the ECC circuit 18 of the memory controller 17.

  Specifically, the memory controller 17 detects a bit error only for the data string # 31, corrects the detected bit error, and generates a corrected data string # 31 '. Further, the memory controller 17 reports the occurrence of one error to the BIOS.

  As a result, even when the clamping period by one bus switch 31 exceeds the output period of the data string # 11, only one bit error occurs, and only one ECC error occurs in the BIOS. To be reported. Therefore, it can be confirmed that “one error correction is performed for a soft error (one error only) and one error log is reported” is correctly executed.

  After that, the error-corrected test data 51 is stored in the cache memory 19 by the read processing unit 15 of the simulated fault processing program. Thereafter, the error-corrected test data 51 stored in the cache memory 19 is evicted from the cache memory 19 by the cache processing unit 16 of the simulated fault processing program. Thereby, even when the read processing unit 15 of the simulated fault processing program executes the read command for the test data 51 again, the test data 51 can be read from the DIMM 4 instead of from the cache memory 19.

  FIG. 3 is an explanatory diagram of a pseudo occurrence of a data error.

  As shown in FIG. 3, in the burst transfer of the DDR SDRAM, four data strings # 11 to # 14 are continuously read out in synchronization with both the rising edge of the memory clock and the falling edge of the memory clock.

  One predetermined bit in the read data string # 11 is clamped to the ground potential by the bus switch 31. By this clamping operation, one predetermined bit of the data string # 21 after the clamping operation is set to the ground potential, in other words, “0” regardless of the original value.

  Note that the data read mode may be a read mode other than the burst transfer of the DDR SDRAM. Therefore, for example, a read mode in which data is read out in synchronization with only the rising edge or the falling edge of the memory clock may be used. Further, the memory that outputs data may be a memory other than the DIMM 4. Furthermore, the memory that outputs data may be a memory other than the DDR SDRAM.

  In the first data string # 11, as described above, the value of the first 1 bit in the first address is set to “1”. On the other hand, as described above, in the data string # 12 to data string # 14 read after the data string # 11, the value of the first 1 bit in the head address is set to “0”.

  Here, as shown in FIG. 3, the clamp period is longer than the period in which the data string # 11 is output. In FIG. 3, the ground potential is indicated by a bold line. For this reason, the clamp period does not end even when the next data string # 12 is output, in other words, the timing of reading the data string # 22. Therefore, the first 1 bit in the first address of the data string # 12 is also clamped to “0”. However, as described above, the value of the leading 1 bit in the leading address of the data string # 12 is originally “0”. Therefore, even if it is clamped to “0”, the value of the first 1 bit in the first address of the data string # 12 does not change to “0”, and there is no influence of clamping.

  In FIG. 3, the data after the clamping operation is expressed as “read data after clamping”. In FIG. 3, the read data is data (64 bits + ECC) including 64-bit data and 8-bit ECC data, whereas the read data after clamping is data string # 21 to data string #. At 24, only a predetermined 1-bit value clamped is shown.

  FIG. 4 is an explanatory diagram of the clamp in the pseudo occurrence of the data error.

  For example, as described above, the leading 1-bit value “1” in the leading address of the data string # 11 is clamped to “0” as shown in FIG. Therefore, the switch SW corresponding to the first bit in the first address of the data string # 11 in the bus switch 31 is connected to the ground potential, in other words, “0” via the pull-down resistor R. In other words, the switch SW corresponding to the first 1 bit in the first address of the data string # 11 is set to the clamped state. As a result, in the data string # 21, the value of the leading 1 bit at the leading address is set to “0”. The switch SW in the bus switch 31 is composed of, for example, one or a plurality of MOSFETs.

  In FIG. 4A, ECC data is omitted in the data string # 21. In FIG. 4A, the switch SW indicates only the switch corresponding to the first 1 bit in the first address and the switch corresponding to the last 1 bit in the last address in the data string # 21.

  Since the switching speed of the bus switch 31 is slow, as shown in FIG. 4B, the switch corresponding to the leading 1 bit in the leading address of the data string # 12 even when the timing of reading the data string # 12 is reached. SW is connected to the ground potential. As a result, also in the data string # 22, the value of the leading 1 bit at the leading address is set to “0”.

  Thereafter, in the bus switch 31, the switch SW corresponding to the first 1 bit in the first address of the data string # 12 is switched from the clamped state to a passing state in which the input of the switch SW is output as it is. As a result, the switch SW corresponding to the first bit in the first address of the data string # 12 outputs the input of the switch SW as it is.

  Therefore, for example, when the read timing of the data string # 11 is reached, the value of the leading 1 bit “0” at the leading address of the data string # 13 is clamped to “0” as shown in FIG. Instead, it passes through the switch SW as it is. As a result, in the data string # 23, the value of the first 1 bit at the first address remains “0”.

  FIG. 5 is an explanatory diagram of data error processing.

  As shown in FIG. 5, each of the data strings # 11 to # 14 read from the DIMM 4 is input to the simulated fault tool 3.

  Here, as described above, the bit clamping operation by the simulated fault tool 3 is executed. Specifically, for example, in the leading data string # 21, as shown in the read data after clamping in FIG. 3, the leading one bit of the leading address is set to the ground potential regardless of the original data value. Clamped. As a result, the data string # 21 includes a 1-bit bit error. In other words, the data string # 21 is simulated fault data including a 1-bit bit error. This 1-bit bit error is a pseudo error generated instead of an actual soft error.

  At this time, as shown in FIG. 3, the clamp period is longer than the period during which the data string # 11 is output. Therefore, in the data string # 22 read after the data string # 21, the read after clamping shown in FIG. As shown in the data, the first bit of the first address is clamped to the ground potential.

  However, as described above, the value of the leading 1 bit in the leading address of the data string # 12 is originally “0”. Therefore, even if it is clamped to “0”, the value of the first 1 bit in the first address of the data string # 12 does not change to “0”, and there is no influence of clamping. Therefore, in the data string # 22, the first 1 bit in the first address is clamped to “0”, but it does not include a 1-bit bit error. As a result, the simulated fault data sequence # 22 is generated, but the generated simulated fault data sequence # 22 is equal to the original data sequence # 22. Therefore, the simulated fault data sequence # 22 is equivalent to not generated.

  The remaining data string # 23 to data string # 24 are read after the end of the clamp period, as shown in the clamp period of FIG. Therefore, the remaining data string # 23 to data string # 24 are not clamped as shown in the read data after clamping in FIG. In other words, the remaining data string # 23 to data string # 24 are directly input to the memory controller of the motherboard.

  The memory controller 17 performs 2-bit error detection and 1-bit error correction using the ECC data included in each of the data string # 31 to data string # 34 in the ECC circuit 18, and corrects the error. The corrected 64-bit data is input to the CPU. In the example of FIG. 1, the memory controller 17 corrects a 1-bit bit error included in the data string # 31 in the ECC circuit 18 to generate a corrected data string # 31 '. On the other hand, since the data string # 32 does not include a bit error, the memory controller 17 does not correct the bit error for the data string # 32.

  The memory controller 17 inputs the corrected data string # 31 'and data string # 32 to data string # 34 to the CPU 11. Further, the memory controller 17 reports the ECC error # 51 to, for example, the BIOS 13. In other words, the memory controller 17 reports that the 1-bit bit error of the data string # 31 has been corrected. The BIOS 13 holds the report received from the memory controller 17 as an error log. As a result, as described above, it is confirmed that "one error correction is performed for a soft error (one error only) and one error log is reported" is correctly executed. Is done.

  FIG. 6 is a flowchart of the data error simulation generation process.

  The simulated fault processing program performs memory mapping on the storage area 41 having a predetermined physical address in the DIMM 4 which is the main memory (step S1), and then determines the storage area 41 having the physical address mapped in memory. The written test data 51 is written (step S2). As a result, the test data 51 is stored in the DIMM 4 at a predetermined address.

  The simulated fault processing program controls the cache processing unit 16 and acquires an area (virtual memory) having a size larger than the memory capacity of the cache memory 19 as a read area in the DIMM 4 (step S3).

  The contents of the acquired virtual memory are read and copied to an area (dummy area) on the cache memory 19 (step S4), and step 5 is repeated. As a result, the test data 51 copied to the cache memory 19 is evicted from the cache memory 19.

  The simulated fault processing program controls the reading processing unit 15 to read predetermined test data 51 from a predetermined physical address (step S5). Test data 51 is read from the DIMM 4 instead of the cache memory 19 from a predetermined address.

  The above is an example in which the memory controller 17 corrects a 1-bit bit error included in the data string # 31 and generates a corrected data string # 31 'in the ECC circuit 18.

  However, the memory controller 17 may execute 2-bit error detection using the ECC data included in the data string # 31 in the ECC circuit 18 and report the detected error to the BIOS.

  In this case, the data string # 11 that is the first data string has a first value, for example, “1” at two predetermined bit positions. The data string # 12 to data string # 14, which are the second data strings, have a second value, for example “0”, at two predetermined bit positions.

  Further, in the simulated fault tool 3, the switches corresponding to the two predetermined bit positions are switched to the clamped state.

  When the simulated fault processing program reads the data string # 11 from the DIMM 4, the simulated fault tool 3 sets the first values at two predetermined bit positions in the read data string # 11 to the second value, respectively. Clamp to a value, eg "0". Thereby, simulated fault data for the data string # 11 including a 2-bit bit error is generated.

  Thereafter, the simulated fault processing program reads data string # 12 to data string # 14, which are the second data string, from the DIMM 4. The simulated fault tool 3 switches the switches corresponding to a plurality of predetermined bit positions from the clamped state to the passing state in parallel with the reading of the data row # 12 to the data row # 14.

  As a result, the simulated fault tool 3 has two predetermined positions when the switches corresponding to the two predetermined bit positions are clamped in the read data string # 12 to data string # 14. If the second value “0” of each bit position is clamped to the second value “0”, and the switches corresponding to the two predetermined bit positions are in the passing state, the two positions The second value “0” of the predetermined bit position is passed as it is. As a result, data string # 12 to data string # 14 are output.

  As a result, the memory controller 17 can execute 2-bit error detection using the ECC data included in the data string # 31 in the ECC circuit 18 and report the detected error to the BIOS.

  Note that, in the data string # 11 to the data string # 14, the number of predetermined bit positions having the first value is not limited to two, and may be a plurality of three or more.

1 server 3 simulated fault tool 4 DIMM
5 disks 11 CPU
12 OS
13 BIOS
14 Pseudo Fault Processing Unit 15 Read Processing Unit 16 Cache Processing Unit 17 Memory Controller 18 ECC Circuit 19 Cache Memory 21 Data Bus 22 Address Bus 23 Control Bus 31 Bus Switch 32 Address Determination Unit 51 Test Data

Claims (2)

In an error correction test method for a computer having a memory corresponding to error correction, a memory controller having an error correction circuit, and a pseudo failure tool between the memory and the memory controller,
The computer writes first data which the first value is set to a particular bit in the first address of the memory, and the second value different from the first value to said particular bit Is written to the second address of the memory that is continuous with the first address ,
The imitation fault tool, clamped to the electrode of the memory corresponding to the particular bit indicates the second value,
The computer continuously reads the first data and the second data from the memory;
An error correction test method, wherein the computer confirms that the error correction circuit corrects an error in the first data. The computer further comprises a cache memory for the memory,
After the computer writes the first data and the second data in the memory, the computer, see predetermined amount the first data and the data other than the second data before texture in memory The error correction test method according to claim 1, wherein:

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