JP6003735B2 - DIMM simulated fault generation method and DIMM simulated fault generation apparatus - Google Patents

Description

  The present invention relates to a DIMM simulated fault generation method and a DIMM simulated fault generation apparatus.

  Techniques for causing a pseudo failure in a memory are disclosed (for example, see Patent Documents 1 to 4). Patent Document 4 discloses a technique for reproducing a memory failure by clamping an output signal of a memory in order to verify an error correction function of a memory controller.

JP 2011-138211 A JP 2010-2111344 A JP 2008-217848 A JP 2012-008620 A

  The operation speed of the clamp needs to follow the communication speed with the memory. However, with the recent improvement in communication speed, the operation speed of the conventional clamp cannot follow the communication speed with the memory. In particular, with respect to continuous read commands, there is a possibility that only the first read data is clamped but the next read data that is not desired to be clamped is clamped.

  The present invention has been made in view of the above problems, and an object thereof is to provide a DIMM simulated fault generation method and a DIMM simulated fault generation apparatus capable of realizing appropriate clamping.

  In order to solve the above-mentioned problem, the DIMM simulated fault generation method disclosed in the specification is a DIMM simulated fault generation method in which a simulated fault is generated in a DIMM from which read data is read after the CPU outputs a read command. Thus, the read command interval is determined, and clamping is prohibited when the read command is output a plurality of times within a predetermined interval.

  According to the DIMM simulated fault generation device and the DIMM simulated fault generation method disclosed in the specification, an appropriate clamp can be realized.

It is a figure for demonstrating a clamp. It is a figure for demonstrating a clamp. 1 is a block diagram of a DIMM simulated fault generator according to Embodiment 1. FIG. It is a figure showing the example of a read command and read data. It is a figure showing the example of a read command and read data. It is a figure showing the example of a read command and read data. It is a figure showing the example of a read command and read data. It is an example of the flowchart showing operation | movement of a DIMM simulated fault generator.

  Prior to the description of the embodiments, the clamp will be described. Many information processing apparatuses include a DIMM (Dual Inline Memory Module) connected to one or more CPUs (Central Processing Units). There are various types of DIMMs depending on differences in memory capacity, operation speed, mounting shape, operation method, data length, and the like. The memory capacity of the DIMM is determined by the capacity and quantity of the memory elements to be mounted. The operation speed of the DIMM is determined by the operable speed of the mounted memory element, the clock frequency supplied by the motherboard on which the CPU and DIMM are mounted, and the like. The mounting shape of the DIMM is determined by the type of connector mounted on the motherboard. The operation method of the DIMM is determined based on DDR2, DDR3, and SDRAM, which are operation standards of the memory element. The data length of the DIMM is 72 bits with ECC (Error Check and Correction) and 64 bits without ECC.

  DIMM mounted on motherboards that require high reliability is equipped with ECC, adds 8-bit ECC in addition to 64-bit read data, detects 1-bit errors and positions in 72-bit read, and detects 2 bits or more. Has a function to detect errors. In recent years, the continuous occurrence of 1-bit errors increases the possibility of 2-bit errors. Therefore, when the number of 1-bit errors generated per unit time exceeds a threshold, the corresponding DIMM is disconnected and the memory capacity is increased. The function to continue the stable operation by reducing the. This function is performed by the CPU that connects the DIMM or the dedicated circuit MAC (Memory Access Controller) and BIOS (Basic Input Output System) that control the DIMM. In product development, this function is tested to ensure correct operation. ing.

  The ECC function performs an operation test by inverting read data read from the DIMM from 1 to 0 by clamping. FIG. 1 is a diagram for explaining a clamp. Referring to FIG. 1, “1000” is read from the DIMM as read data for error testing. By clamping the period including the read data (2 ns in FIG. 1), only the first 1-bit data can be degenerated even if clamping is performed for a time longer than the time when 1-bit data is output.

  The operation speed of the DIMM is determined by supplying a clock at a speed at which the mounted memory element can operate from the motherboard. In recent years, the operating speed of memory elements has been increased, and the trend of increasing the speed has continued. When the clock frequency is increased by increasing the speed of the memory element, if the clamp period is fixed, the clamp period is extended relative to the read data as shown in FIG. The clamping period is determined by the operation speed of the semiconductor element that performs clamping, and is 2 ns as an example in FIG.

  In FIG. 2, (1) to (4) of the read data 1 for error test are prepared in advance and are “1000” as an example. Any one of the error test read data may be “1” and the others may be “0”. The read data 2 to be read next to the read data 1 is not prepared in advance, and (5) to (8) are data at address positions indicated by the CPU accessing the DIMM. In the example of FIG. 2, when the read data 1 is clamped from (1), the clamp period continues to (5) and (6) of the read data 2. In this case, if “1” is included in (5) and (6), the “1” becomes error data by inversion by clamping. As a result, error data should be generated once, but will be generated twice or more. That is, for the continuous read command, only the first read data is clamped, but the next read data that is not to be clamped is clamped.

  In the following embodiments, a DIMM simulated fault generation apparatus and a DIMM simulated fault generation method capable of realizing appropriate clamping will be described.

  FIG. 3 is a block diagram of the DIMM simulated fault generator 100 according to the first embodiment. Referring to FIG. 3, CPU-DIMM interface 200 is a DIMM connector mounted on a motherboard. The DIMM simulated fault generation apparatus 100 is configured by a logic circuit or the like, and is mounted on the CPU-DIMM interface 200. The DIMM simulated fault generation apparatus 100 includes a DIMM connector 10. The DIMM 300 is mounted on the DIMM connector 10.

  Further, the DIMM simulated fault generation apparatus 100 includes an address determination unit 20, a command determination unit 30, a command interval determination unit 40, a test control unit 50, a clamp execution unit 60, and a BUS switch 70. The address determination unit 20 determines whether the read command from the CPU is a desired address. For example, when the combination of the CS signal (CS #), the RAS signal (RAS #), the CAS signal (CAS #), and the WE signal (WE #) is “0101”, the command determination unit 30 It is determined that the data has been output.

  After the command determination unit 30 determines that the read command has been output, the command interval determination unit 40 measures a predetermined interval (4 clocks as an example in the present embodiment) by the number of clock signals (#CLK), and a plurality of intervals are provided between them. It is determined that no read command is output. The test control unit 50 confirms that the address determination unit 20 determines that the read command from the CPU is a desired address, and the command interval determination unit 40 confirms that a plurality of read commands are not output within the predetermined interval. . When the confirmation is made by the test control unit 50, the clamp execution unit 60 turns on the BUS switch 70 for a clamp period after a predetermined time has elapsed since the read command was output in accordance with an instruction from the test control unit 50. When the BUS switch 70 is turned on, clamping is performed by grounding a part of the read data (for example, 4 bits). In addition, the test control unit 50 causes the panel unit 400 to display information regarding the error test.

  Next, details of the operation of the DIMM simulated fault generator 100 will be described. As an example, the clock interval is set to 0.625 ns, the clamp period is set to 2 ns, the time width of the read command is set to 0.31 ns, and the predetermined time from when the read command is output until the read data is output is 5τ. Suppose that it is fixed.

  When the CPU reads data from the DIMM (when a read command is output), (CS #, RAS #, CAS #, WE #) represented by a combination of signals becomes “0101”. In the example of FIG. 4, read data a1 to a4 are output 5τ after the read command a is output. Further, the read command b is output 3τ after the read command a is output, and the read data b1 to b4 are output 5τ after the read command b is output. In the example of FIG. 4, the read command a has an address where a data error is desired.

  In this case, a read error of (a1, a2, a3, a4) = “1000” is clamped by the read command a, so that (a1, a2, a3, a4) = “0000” and a data error occurs. . In the example of FIG. 4, since the interval between the read command a and the read command b is smaller than the clamp period, a data error can also occur in the read data b1 to b4 as shown in FIG. However, in the present embodiment, when the command interval determination unit 40 determines that the read command is output a plurality of times within the clamp period, the clamp execution unit 60 does not execute the clamp as shown in FIG. This prevents a data error from occurring in the read data b1 to b4.

  In the example of FIG. 7, since the interval between the read command a and the read command b is larger than the clamp period, the read data b1 to b4 are not output within the clamp period. In this case, since the command interval determination unit 40 determines that the read command is output only once within the clamp period, the clamp execution unit 60 executes the clamp. As described above, when the read command b is output within the clamp period after the read command a is output from the CPU, the clamping is prohibited, and the read command a after the clamp period after the read command a is output from the CPU. When b is output, clamping is performed. Thus, according to the present embodiment, an appropriate clamp can be realized. As a result, even if the operation speed of the DIMM increases, it is possible to reliably generate a data error the specified number of times. Further, it is possible to easily check the data error detection / correction function and error frequency coefficient function of the motherboard.

  FIG. 8 is an example of a flowchart showing the operation of the DIMM simulated fault generator 100. Referring to FIG. 8, command determination unit 30 determines whether CS # is “0” (step S1). When it is determined “Yes” in Step S1, the command determination unit 30 determines whether or not RAS # is “1” (Step S2). When it is determined as “Yes” in Step S2, the command determination unit 30 determines whether CAS # is “0” (Step S3). When it is determined as “Yes” in Step S3, the command determination unit 30 determines whether or not WE # is “1” (Step S4). Whether or not a read command has been output can be determined by executing steps S1 to S4. In addition, when it determines with "No" by step S1-step S4, step S1 is performed again.

  If “Yes” is determined in step S4, the address determination unit 20 determines whether the address ADR of the read command is an address for which a data error is desired (step S5). If it is determined “No” in step S5, step S1 is executed again. If it is determined as “Yes” in step S5, the command interval determination unit 40 stores “4” in the parameter Timer (step S6). The parameter Timer is a parameter for counting the number of clocks.

  Next, the command interval determination unit 40 determines whether or not CLK # is “0” (step S7). By executing step S7, it can be determined whether or not one clock has elapsed. If it is determined “No” in step S7 (CLK # = 1), step S7 is executed again. If it is determined as “Yes” in step S7, the command interval determination unit 40 subtracts “1” from the parameter Timer (step S8).

  Next, the command interval determination unit 40 determines whether or not CS # is “0” (step S9). When it is determined “Yes” in step S9, the command interval determination unit 40 determines whether or not RAS # is “1” (step S10). When it is determined as “Yes” in Step S10, the command interval determination unit 40 determines whether CAS # is “0” (Step S11). If it is determined as “Yes” in Step S11, the command interval determination unit 40 determines whether or not WE # is “1” (Step S12). By executing steps S9 to S12, it is possible to determine whether or not the read command has been output again during 4 clocks.

  When it is determined as “Yes” in Step S12, the command interval determination unit 40 stores “4” in the parameter Timer (Step S13). Next, the command interval determination unit 40 determines whether or not CLK # is “0” (step S14). By executing step S14, it can be determined whether or not one clock has elapsed. If it is determined “No” in step S14, step S14 is executed again. When it is determined as “Yes” in Step S14, the command interval determination unit 40 subtracts “1” from the parameter Timer (Step S15). Next, the command interval determination unit 40 determines whether or not the parameter Timer is 1 or more (step S16). If it is determined “Yes” in step S16, step S14 is executed again. If it is determined “No” in step S16, step S1 is executed again.

  When it is determined “No” in Steps S9 to S12, the clamp execution unit 60 determines whether or not the parameter Timer is 1 or more (Step S17). If “Yes” is determined in step S17, step 7 is executed again. When it is determined “No” in step S17, the clamp execution unit 60 turns on the BUS switch 70 for the clamp period after a predetermined time has elapsed (for example, after 5τ) after the read command is output (step S18). Clamping is executed when a read command is output once in a period of 4 clocks by executing steps S17 and S18. Thereafter, the execution of the flowchart ends.

  Although the embodiments of the present invention have been described in detail above, the present invention is not limited to such specific embodiments, and various modifications and changes can be made within the scope of the gist of the present invention described in the claims. It can be changed.

DESCRIPTION OF SYMBOLS 10 DIMM connector 20 Address determination part 30 Command determination part 40 Command interval determination part 50 Test control part 60 Clamp execution part 70 BUS switch 100 DIMM simulated fault generator 200 CPU-DIMM interface 300 DIMM
400 Panel section

Claims (4)

A DIMM simulated fault generation method for generating a simulated fault in a DIMM from which read data is read after the CPU outputs a read command,
Determine the interval between read commands,
A DIMM simulated fault generation method, wherein clamping is prohibited when a read command is output a plurality of times within a predetermined interval.   2. The DIMM simulated fault generation method according to claim 1, wherein the predetermined interval is a period of one clamping.   3. The DIMM simulated fault generation method according to claim 1, wherein the read data includes one "1" and the other is "0". A DIMM simulated fault generator for generating a simulated fault for a DIMM from which read data is read after the CPU outputs a read command,
A command interval determining unit for determining an interval between read commands;
And a clamp execution unit that prohibits clamping when a read command is output a plurality of times within a predetermined interval.

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