JP6108478B2 - Computer device, address translation device, and program - Google Patents

Description

  The present invention relates to a computer device, an address conversion device, and a program.

  A rewritable nonvolatile memory can rewrite data and can store data for a long period of time regardless of the non-powered state. Therefore, rewritable nonvolatile memories are widely used in various fields today for storing application data or for storing programs in embedded products. In particular, flash memory has been commercialized in a large capacity.

  Among flash memories, a NAND flash memory (hereinafter referred to as a NAND flash) is suitable for increasing the capacity because of the internal structure of the device. However, in NAND flash, it is known that internal elements deteriorate due to a phenomenon called read disturb when data is read. The inside of the NAND flash is configured as a set of units called blocks, and a block including a bit from which a normal value cannot be read is marked as a bad block. In the NAND flash, a countermeasure is generally taken against deterioration such that the marked block is not used in the subsequent processing.

  On the other hand, NOR flash (hereinafter referred to as NOR flash) is structurally free from deterioration due to the above-described read disturb phenomenon. For this reason, the NOR flash is often used for data retention that requires high reliability, for example, for program storage. Based on this high reliability, the NOR flash does not have the concept of a bad block like the NAND flash.

  Although the reliability of NOR flash is high, correct data is not written if power is cut off during data rewriting. If this event occurs during rewriting of the program, the device will not operate normally. In order to avoid the malfunction of the NOR flash, the NOR flash may store a copy of the program in another area in the flash. As a result, the NOR flash confirms the normality of the original program and the duplicate program by verification using a checksum or the like. The NOR flash is controlled so that the apparatus is operated by a duplicate program if there is an abnormality in the original program. In this manner, in the NOR flash, a countermeasure against a write failure due to a power interruption during data rewriting is taken.

  Generally, a program is divided into a boot program and a system program. Further, the system program is activated after the boot program is activated. When the CPU starts up, it reads the boot program. Further, the CPU confirms the validity of the system program using the checksum as described above by processing of the boot program, and controls the normal program to operate. In other words, the countermeasure against writing failure due to power interruption during data rewriting by having the above-described replication program is effective for the system program.

  Here, it is also conceivable to store a duplicate program of the boot program at another address. However, an address (hereinafter referred to as a boot address) that the CPU accesses at startup is determined, and the boot program is always read from that address. If there is an abnormality in the boot program, the subsequent processing cannot be performed and the apparatus does not start.

  In general, a boot program performs basic hardware settings. Therefore, the boot program does not need to be updated for improving the function. Furthermore, the boot program is generally operated without updating in order not to induce a problem of writing failure due to power interruption during data rewriting. However, the data retention time of the nonvolatile memory is finite. For this reason, the nonvolatile memory may cause data abnormality due to aging. In order to extend the data retention time, it is recommended by the JEDEC Solid State Technology Association, which is a semiconductor technology standardization organization, to rewrite data in a nonvolatile memory at regular intervals. However, since there is a risk of data abnormality due to power interruption during rewriting, rewriting of data on the nonvolatile memory could not be easily realized.

  Patent Document 1 discloses storing a copy of a boot program on a nonvolatile memory. Specifically, when an abnormality occurs in the boot area where the boot program is stored, the duplicate boot program stored in the recovery area is copied to the boot area by manually switching the switch. Repair the boot area by copying the duplicate boot program. When the CPU does not notify the monitoring circuit of the normal activation within a certain period, the monitoring circuit determines that the CPU is not normally activated. In this case, the monitoring circuit controls to automatically copy the duplicate boot program in the recovery area to the boot area.

JP 2009-151384 A

  As described above, in Patent Document 1, when an abnormality occurs in the boot area, a process of copying the duplicate boot program stored in the recovery area to the boot area is performed. However, an abnormality in the boot area is mainly caused by a power interruption or the like during data rewriting in the boot area. For this reason, if a factor such as a power failure occurs during the process of copying the duplicate boot program to the boot area, the boot area abnormality is not repaired. Therefore, there is a problem that the normality of the boot area cannot be guaranteed even after the copy process of the duplicate boot program to the boot area.

  An object of the present invention is to provide a computer device, an address conversion device, and a program capable of reliably executing a startup process using a boot program in which no abnormality has occurred even when an abnormality has occurred in some boot programs. It is to provide.

  A computer apparatus according to a first aspect of the present invention includes a control unit that outputs a first boot program address signal, a memory that stores a boot program at a plurality of addresses, and the first boot program address signal. An address conversion unit that converts the second boot program address signal, which is an address of a memory in which the boot program is stored, and outputs the second boot program address signal to the memory, and reads from the memory And a program reading unit that detects an error in the plurality of boot programs and outputs the boot program in which the error is corrected to the control unit.

  In the address conversion device according to the second aspect of the present invention, the first boot program address signal output from the control unit is an address in a memory storing a plurality of boot programs, and stores the boot program. An address conversion unit that converts the address signal to a second boot program address signal indicating the location and outputs the second boot program address signal to the memory, and a plurality of boot program errors read from the memory And a program reading unit that outputs the boot program in which the error is corrected to the control unit.

  The program according to the third aspect of the present invention provides a first boot program address signal output from the control unit as an address in a memory that stores a plurality of boot programs, and a location for storing the boot program. The second boot program address signal is output, the second boot program address signal is output to the memory, the errors of the boot programs read from the memory are detected, and the errors are detected. The modified boot program is output to the control unit.

  According to the present invention, there are provided a computer device, an address translation device, and a program capable of reliably executing a boot process using a boot program in which no abnormality has occurred even when an abnormality has occurred in some boot programs. be able to.

1 is a configuration diagram of a computer apparatus according to a first embodiment; FIG. 3 is a configuration diagram of a computer apparatus according to a second embodiment. FIG. 6 is a configuration diagram of a conversion circuit according to a second embodiment. FIG. 10 is a diagram showing an arrangement of programs in a flash memory according to a second embodiment. FIG. 6 is a diagram illustrating a timing chart of signals according to the second embodiment.

(Embodiment 1)
Embodiments of the present invention will be described below with reference to the drawings. A configuration example of the computer apparatus 10 according to the first embodiment of the present invention will be described with reference to FIG. The computer apparatus 10 includes a control unit 11, an address conversion unit 12, a memory 13, and a program reading unit 14. The computer device 10 may be a mobile communication device such as a mobile phone terminal or a smartphone terminal, or may be a personal computer device or a server device.

  The control unit 11 may be a CPU, for example. The control unit 11 operates various functions by executing a program stored in the memory 13. The control unit 11 outputs a boot program address signal to the address conversion unit 12. Generally, the control unit 11 uses one boot program address in order to read a boot program.

  The memory 13 stores boot programs at a plurality of addresses. That is, the memory 13 has a plurality of boot programs. Each boot program has the same contents. The memory 13 is, for example, a ROM (Read Only Memory) or a flash memory. For example, the memory 13 may store the boot program at the boot program address set in the boot program address signal output by the control unit 11 and store a copy of the boot program at another address.

  The address conversion unit 12 receives the boot program address signal output from the control unit 11. The address conversion unit 12 rewrites the boot program address signal in the memory 13 with the boot program address signal in which the address where the boot program is stored is set. Here, the boot program address signal output from the control unit 11 is referred to as an original boot address, and the signal converted by the address conversion unit 12 is referred to as a post-conversion boot address. The address conversion unit 12 outputs the converted boot address signal to the memory 13.

  The memory 13 outputs the boot program stored at the address set in the boot address signal after conversion to the program reading unit 14. The program reading unit 14 detects errors in a plurality of boot programs output from the memory 13 and outputs a boot program in which the errors are corrected to the control unit 11.

  As described above, the computer apparatus 10 according to the first embodiment of the present invention has the address conversion unit 12 between the control unit 11 and the memory 13. When the address conversion unit 12 receives the original address signal from the control unit 11, the address conversion unit 12 can convert it into another address (post-conversion boot address) in which the boot program of the memory 13 is stored.

  Therefore, when the control unit 11 transmits an original boot signal to the address conversion unit 12, the program reading unit 14 can read a plurality of boot programs stored in the memory 13. Therefore, for example, even if an abnormality occurs in the boot program stored at the address set as the original boot address, the program reading unit 14 can read the boot program stored at another address. The program reading unit 14 outputs the correct boot program among the read boot programs to the control unit 11. Even if an abnormality has occurred in the boot program stored at the address set as the original boot address, the control unit 11 can read the boot program in the same manner as when no abnormality has occurred.

(Embodiment 2)
Next, a configuration example of the computer apparatus according to the second embodiment of the present invention will be described with reference to FIG. The computer apparatus of FIG. 2 includes a CPU 20, a flash memory 30, and a conversion circuit 40. The CPU 20 corresponds to the control unit 11 in FIG. The flash memory 30 corresponds to the memory 13 in FIG. The conversion circuit 40 corresponds to the address conversion unit 12 and the program reading unit 14 in FIG.

  The CPU 20 outputs a 20-bit ADDRESS [19: 0] signal, a CS (Chip Select) signal, an RD (Read) signal, and an 8-bit DATA [7: 0] signal to the flash memory 30 via the conversion circuit 40. To do. The CPU 20 outputs a WR (Write) signal to the flash memory 30 without passing through the conversion circuit 40.

  The ADDRESS [19: 0] signal indicates an address where data to be written or read in the flash memory 30 is stored. The RD signal is a signal used when the CPU 20 reads data stored in the flash memory 30. The WR signal is a signal used when the CPU 20 updates data stored in the flash memory 30 or writes new data.

  The CS signal is a signal used when the CPU 20 designates a device such as a flash memory to be accessed. The CPU 20 outputs a CS signal to the flash memory 30 when reading or writing data to the flash memory 30. Data [7: 0] is 8-bit data read from the flash memory 30 by the CPU 20. Here, the ADDRESS signal is 20 bits and the DATA signal is 8 bits, but the number of bits to be used may be changed based on the specifications of the device.

  Next, a configuration example of the conversion circuit 40 according to the second exemplary embodiment of the present invention will be described with reference to FIG. The conversion circuit 40 includes an address generation unit 41, a CS generation unit 42, an RD generation unit 43, a clock generation unit 44, a selector 45, a selector 46, an inverter 47, an XOR circuit 48, a shift register 49, an inverter 50, an XOR circuit 51, and a shift. A register 52 is provided. The address generation unit 41 corresponds to the address conversion unit 12 in FIG. The inverter 47, the XOR circuit 48, the shift register 49, the inverter 50, the XOR circuit 51, and the shift register 52 correspond to the program reading unit 14 in FIG.

  The address generation unit 41 receives an ADDRESS signal output from the CPU 20 and a CLK (clock) signal supplied from the outside of the conversion circuit 40. The ADDRESS signal is a signal indicating the address of the flash memory 30 in which the original boot program is stored. The address generation unit 41 converts the ADDRESS signal into a signal indicating an address storing the duplicate boot program. The address generator 41 may output the ADDRESS signal as it is when outputting the address storing the original boot program. The address generation unit 41 outputs a signal indicating the converted address at a predetermined timing using the CLK signal.

  The CS generation unit 42 receives the CS signal output from the CPU 20 and the CLK signal. The CS signal is a signal used when reading data from the flash memory 30 or writing data into the flash memory 30, for example. The CS generation unit 42 outputs the converted CS signal at a predetermined timing using the CLK signal.

  The RD generation unit 43 receives the RD signal output from the CPU 20 and the CLK signal. The RD signal is a signal used when reading data from the flash memory 30 or another memory. For example, the RD signal is used for reading a boot program stored in the flash memory 30. The RD generator 43 outputs the converted RD signal at a predetermined timing using the CLK signal.

  The clock generation unit 44 receives the CLK signal and the RD signal. Further, the clock generation unit 44 outputs an SFT_CLK (shift clock) signal used when operating the shift register 49 and the inverter 50 at a predetermined timing.

  The selector 45 selects either the ADDRESS signal output from the CPU 20 or the signal output from the address generation unit 41 and outputs the selected signal to the flash memory 30 as the F_ADDRESS signal. Furthermore, the selector 45 selects either the CS signal output from the CPU 20 or the converted CS signal output from the CS generation unit 42, and outputs the selected signal to the flash memory 30 as the F_CS signal. Further, the selector 45 selects either the RD signal output from the CPU 20 or the converted signal output from the RD generation unit 43, and outputs the selected signal to the flash memory 30 as the F_RD signal. For example, when a low level RD signal is input to the SEL terminal, the selector 45 selects each signal output from the address generation unit 41, the CS generation unit 42, and the RD generation unit 43.

  The shift register 49 receives the F_DATA signal output from the flash memory 30 at the DIN terminal. The F_DATA signal is a signal including a boot program output from the flash memory 30, for example. Further, the shift register 49 shifts F_DATA received at the DIN terminal in the order of the DATA_a terminal, the DATA_b terminal, and the DATA_c terminal in accordance with the SFT_CLK signal input to the CLKIN terminal.

  The DATA_a terminal, DATA_b terminal, and DATA_c terminal in the shift register 49 output the shifted F_DATA to the XOR circuit 48, respectively. The XOR circuit 48 performs an exclusive OR operation using data output from the DATA_a terminal, the DATA_b terminal, and the DATA_c terminal. The XOR circuit 48 outputs the execution result of the operation to the inverter 47. The inverter 47 inverts the data related to the execution result of the exclusive OR operation output from the XOR circuit 48 and outputs the inverted data to the selector 46. The inverter 50, the XOR circuit 51, and the shift register 52 perform the same operations as the inverter 47, the XOR circuit 48, and the shift register 49. The conversion circuit 40 may include an arbitrary number of inverters 47, an XOR circuit 48, and a shift register 49.

  The selector 46 selects either data output from the inverter 47 or F_DATA output from the flash memory 30. The selector 46 outputs the selected data to the CPU 20. Further, the selector 46 selects either data output from the inverter 50 or F_DATA output from the flash memory 30. The selector 46 outputs the selected data to the CPU 20. For example, the selector 46 selects each signal output from the inverter 47 and the inverter 50 when a low level RD signal is input to the SEL terminal.

  Next, the arrangement of programs in the flash memory 30 will be described with reference to FIG. Here, since the address in the flash memory 30 is 20 bits, the address of the flash memory 30 is 0x00000 to 0xFFFFF. Here, the address that the CPU 20 accesses immediately after startup is address 0x00000. The boot program located at 0x01000 or 0x02000 is a copy of the boot program located at 0x00000. It is assumed that the duplicate boot program is written in advance before being accessed by the CPU 20.

  Next, a timing chart of each signal will be described with reference to FIG. The CPU 20 performs read access to the boot address 0x00000 in order to read the boot program stored in the flash memory 30 immediately after startup. Specifically, the CPU 20 outputs a signal that sets ADDRESS = 0x00000, CS = Low, and RD = Low.

  In this figure, the conversion circuit 40 receives signals for ADDRESS = 0x00000 and CS = Low before receiving RD = Low. Prior to CK0, the conversion circuit 40 has not received the RD signal set to the Low signal. Therefore, the selector 45 outputs the input ADRESS signal and CS signal as they are. Therefore, the F_ADDRESS signal has the same value as the ADRESS signal, and the F_CS signal has the same value as the CS signal.

  Next, at the rising edge of CK0, the RD generator 43 detects RD = Low. Further, the RD generator 43 outputs a low level signal detected at CK0 at the rising edge of CK1. When the selector 45 receives RD = Low, the selector 45 outputs the signals output from the address generation unit 41, the CS generation unit 42, and the RD generation unit 43 to the flash memory 30. The address generation unit 41 outputs the ADDRESS signal to the selector 45 as it is. Further, the CS generation unit 42 also outputs the CS signal to the selector 45 as it is. Therefore, the F_ADDRESS signal and the F_CS signal are signals having the same values as those before RD = Low is input. The RD generator 43 outputs RD = Low detected at CK0 at the rising edge of CK1. For this reason, a low level signal is output as the F_RD signal at the rising edge of CK1.

  The flash memory 30 receives the F_RD signal set to the Low level, and outputs the boot program stored at the address set in the F_ADDRESS signal to the conversion circuit 40 as F_DATA. Therefore, the shift register 49 receives F_DATA = <X> at the rising edge of CK2. <X> indicates a boot program stored in 0x00000.

  Next, when SFT_CLK changes to High level at CK3, the shift register 49 outputs <X> from the DATA_a terminal at the rising edge of CK3.

  Next, the address generation unit 41 converts 0x00000 into 0x01000 and outputs it at CK4. The timing at which the address generation unit 41 converts the output address may be determined in advance. For example, when 0x00000 is output for a predetermined period, 0x01000 may be output next after the predetermined timing. The address generation unit 41 converts the output address at a predetermined timing.

  Further, the RD generation unit 43 outputs a signal set to the High level at CK4. The timing at which the RD generation unit 43 converts the output signal from the low level to the high level may be determined in advance, for example, to be the same timing as the timing at which the address generation unit 41 converts the output address. When the RD generation unit 43 converts the output signal from the low level to the high level, the flash memory 30 receives the high level signal as the F_RD signal. Therefore, the flash memory 30 stops outputting F_DATA = <X>, which is a boot program stored in 0x00000.

  Next, at CK5, the RD generator 43 outputs a signal set to the Low level. For example, the RD generation unit 43 may convert the output signal to the Low level again in the next clock cycle after converting the output signal to the High level, and may determine other timing as the conversion timing. As a result, the flash memory 30 receives the F_RD signal set to the Low level. Further, the flash memory 30 outputs the boot program stored in 0x01000 set in the F_ADDRESS signal to the conversion circuit 40 as F_DATA. Therefore, the shift register 49 receives F_DATA = <Y> at the timing of CK6. <Y> indicates a boot program stored in 0x01000.

  Next, when SFT_CLK changes to High level at CK7, the shift register 49 outputs <Y> from the DATA_a terminal and <X> from the DATA_b terminal at the rising edge of CK7.

  Next, the address generation unit 41 converts 0x01000 into 0x02000 and outputs it at CK8. The timing at which the address generation unit 41 converts the output address may be determined in advance.

  Further, the RD generation unit 43 outputs a signal set to the high level at CK8. When the RD generation unit 43 converts the output signal from the low level to the high level, the flash memory 30 receives the high level signal as the F_RD signal. Therefore, the flash memory 30 stops outputting F_DATA = <Y>, which is a boot program stored in 0x01000.

  Next, at CK9, the RD generator 43 outputs a signal set to the Low level. As a result, the flash memory 30 receives the F_RD signal set to the Low level. Further, the flash memory 30 outputs the boot program stored in 0x02000 set in the F_ADDRESS signal to the conversion circuit 40 as F_DATA. Therefore, the shift register 49 receives F_DATA = <Z> at the timing of CK10. <Z> indicates a boot program stored in 0x02000.

  Next, when SFT_CLK changes to high level at CK11, the shift register 49 outputs <Z> from the DATA_a terminal, <Y> from the DATA_b terminal, and <X> from the DATA_c terminal at the rising edge of CK11. Is output. The clock generation unit 44 may determine the timing for changing SFT_CLK in advance. For example, the clock generation unit 44 determines that SFT_CLK is set to a high level after F_RD is set to a low level and a boot program is set to F_DATA.

  When the XOR circuit 48 receives three signals output from the shift register 49 at CK11, the XOR circuit 48 performs an XOR operation. Further, the CPU 20 receives the signal output from the inverter 47 as DATA.

  Here, the DATA received by the CPU 20 will be described in detail. The boot program <X>, boot program <Y>, and boot program <Z> output from the flash memory 30 are the same program. However, assuming a data abnormality due to power interruption during rewriting of the boot program, only the program accessed at the time of power interruption becomes abnormal. That is, there is a possibility that only one of the addresses 0x00000, 0x01000, and 0x02000 has an incorrect value. In other words, out of the 3-bit data output from the DATA_a terminal, the DATA_b terminal, and the DATA_c terminal, only 1 bit may be an incorrect value.

  The XOR circuit 48 is used for ignoring erroneous bits and outputting a value that can be read normally as DATA.

  For example, if 1 bit is originally converted to 0 by mistake, the input 3 bits in the XOR circuit 48 are (1, 1, 0), and the result of the operation in the XOR circuit 48 is 0. Also, assuming that 0 bit is accidentally converted to 0, the 3 input bits in the XOR circuit 48 are (0, 0, 1), and the result of the operation in the XOR circuit 48 is 1. The respective inversion values are output as DATA to the CPU 20 by the inverter 47. Therefore, as a result, the result of (1, 1, 0) is 1, and the result of (0, 0, 1) is 0. As a result, a correct value is output to the CPU 20.

  Thereafter, the CPU 20 sequentially outputs the address and reads the data in the flash memory 30, but converts the read from the CPU 20 once into the read of three times as in the above description, and continues reading the program.

  As described above, the following effects can be obtained by using the computer apparatus according to the second embodiment of the present invention.

  When the boot program is rewritten in a general circuit configuration, there is a risk that the boot program may not start normally due to a power failure. Therefore, the boot program could not be updated. On the other hand, by utilizing the present invention, the CPU 20 can read a plurality of boot programs stored in the flash memory 30. Therefore, even when an error occurs in a part of boot programs, the boot program can be normally read out by using another boot program. Therefore, the boot program can be upgraded.

  Furthermore, generally, the data retention time of the nonvolatile memory is defined by the time from data writing. Since the boot program can be erased and rewritten in the present invention, the data retention time of the nonvolatile memory can be extended.

  In the above-described embodiments, the present invention has been described as a hardware configuration, but the present invention is not limited to this. The present invention can also realize processing executed in the conversion circuit by causing a CPU (Central Processing Unit) to execute a computer program.

  In the above example, the program can be stored and supplied to a computer using various types of non-transitory computer readable media. Non-transitory computer readable media include various types of tangible storage media. Examples of non-transitory computer-readable media include magnetic recording media (for example, flexible disks, magnetic tapes, hard disk drives), magneto-optical recording media (for example, magneto-optical disks), CD-ROMs (Read Only Memory), CD-Rs, CD-R / W, semiconductor memory (for example, mask ROM, PROM (Programmable ROM), EPROM (Erasable PROM), flash ROM, RAM (Random Access Memory)) are included. The program may also be supplied to the computer by various types of transitory computer readable media. Examples of transitory computer readable media include electrical signals, optical signals, and electromagnetic waves. The temporary computer-readable medium can supply the program to the computer via a wired communication path such as an electric wire and an optical fiber, or a wireless communication path.

  Note that the present invention is not limited to the above-described embodiment, and can be changed as appropriate without departing from the spirit of the present invention. For example, the conversion circuit 40 may be built in a memory controller in a SoC (System ON Chip) in advance.

DESCRIPTION OF SYMBOLS 10 Computer apparatus 11 Control part 12 Address conversion part 13 Memory 14 Program reading part 20 CPU
30 Flash Memory 40 Conversion Circuit 41 Address Generation Unit 42 CS Generation Unit 43 RD Generation Unit 44 Clock Generation Unit 45 Selector 46 Selector 47 Inverter 48 XOR Circuit 49 Shift Register 50 Inverter 51 XOR Circuit 52 Shift Register

Claims (8)

A control unit for outputting a first boot program address signal;
Memory for storing boot programs at multiple addresses;
The first boot program address signal is converted into a second boot program address signal that is an address of a memory in which the boot program is stored, and the second boot program address signal is output to the memory. An address translation unit;
A program reading unit that detects an error in the plurality of boot programs read from the memory and outputs the boot program in which the error is corrected to the control unit, and
The program reading unit
Each of the boot programs read out from the memory at different timings is set as an output terminal, and each of the boot programs set as output terminals is output to the XOR circuit at the same timing, and has a shift register. Computer device. The address conversion unit
The computer apparatus according to claim 1, wherein the second boot program address signal is sequentially converted to an address storing the boot program at a predetermined timing. The program reading unit
The computer apparatus according to claim 1, wherein an error of a plurality of the boot programs is corrected using an XOR circuit. Further comprising, a computer device of claim 1 clock generator for generating a clock indicating the timing to be set to the output terminal of each of the plurality of the boot program in the shift register. The first boot program address signal output from the control unit is converted into a second boot program address signal indicating an address in a memory storing a plurality of boot programs and indicating a location where the boot program is stored. An address conversion unit for outputting the second boot program address signal to the memory;
A program reading unit that detects an error in the plurality of boot programs read from the memory and outputs the boot program in which the error is corrected to the control unit, and
The program reading unit
Each of the boot programs read out from the memory at different timings is set as an output terminal, and each of the boot programs set as output terminals is output to the XOR circuit at the same timing, and has a shift register. Address translation device. The address conversion unit
6. The address conversion device according to claim 5 , wherein the second boot program address signal is sequentially converted into an address storing the boot program at a predetermined timing. The program reading unit
The address translation device according to claim 5 or 6 , wherein an error of a plurality of the boot programs is corrected using an XOR circuit. The first boot program address signal output from the control unit is converted into a second boot program address signal indicating an address in a memory storing a plurality of boot programs and indicating a location where the boot program is stored. ,
Outputting the second boot program address signal to the memory;
Each of the boot programs read from the memory at different timings is set to the output terminal of the shift register ,
Output each boot program set to the output terminal to the XOR circuit at the same timing,
Detecting a plurality of boot program errors using the XOR circuit;
A program that causes a computer to output the boot program in which an error is corrected to the control unit.

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