JP5006121B2 - Logic verification device and logic verification method - Google Patents

Description

  The present invention relates to a logic verification device, and more particularly to a logic verification device for a semiconductor integrated circuit.

  In recent years, with the miniaturization of processes and the reduction in voltage, there is an increasing possibility that data held in a memory, such as transistor variations, power supply noise, wiring crosstalk, and neutron beams, may be garbled.

  Therefore, in the field where high reliability is required, it is necessary to suppress the occurrence of errors and at the same time detect the generated data and perform control so that the system does not malfunction.

  Among microprocessors, those employed in products that require particularly high reliability add data parity to various data signals in the processor to protect data. When an error such as a parity error occurs, it is required to perform a special operation such as notifying the outside of the processor without overlooking the error and checking the entire system. Furthermore, in order to verify the operation when an error occurs during logic simulation, it is necessary to actually put incorrect data on the signal.

  As a related technique, JP-A-2001-134629 (Patent Document 1) discloses a simulation method and a simulation apparatus. This known technique has a valid memory address (lower) and an invalid memory address (upper) among the addresses for accessing the memory model. An error generation address is added to an invalid memory address, and an error control module existing in the memory module generates a desired error in Read / Write data of the memory based on the contents. In this known technique, an invalid address bit is created by limiting the memory module area that is actually read and written, and the invalid address bit is used for error control. By performing such processing, a desired error can be generated for an arbitrary address or data when accessing the memory by the LSI model. Then, operation verification such as detection of an error occurrence can be performed.

JP 2001-134629 A

  In the known technique described above, the error occurrence is controlled using the invalid portion of the address of the memory module. Therefore, in the memory where there is no invalid address, the occurrence of the error cannot be controlled in the first place. In the known technique, an invalid address bit is created by limiting the memory module area that is actually read and written, and the invalid address bit is used for error control.

  In the following, means for solving the problem will be described using the numbers used in [Best Mode for Carrying Out the Invention] in parentheses. These numbers are added to clarify the correspondence between the description of [Claims] and [Best Mode for Carrying Out the Invention]. However, these numbers should not be used to interpret the technical scope of the invention described in [Claims].

  The logic verification apparatus of the present invention is provided in the CPU (10), an error control memory (21) connected to the CPU (10) and holding error occurrence conditions for logic verification, and the CPU (10). During the logic verification, an error occurrence control circuit (122) for outputting an error occurrence signal based on the error occurrence condition and the bus access state of the CPU (10) and an error occurrence are provided in the CPU (10). And an error generation circuit (123) for generating a bus error according to the content of the signal.

  As described above, the error control memory storing the error generation conditions for logic verification is provided outside the CPU, and the error generation control circuit and the error generation circuit are provided in the function model for hardware macro (memory) logic simulation inside the CPU. By providing these in one logic simulation environment, it is possible to control the occurrence of errors on the program during the simulation execution using the address from the CPU core to the function model for hard macro (memory) logic simulation.

  An error can be generated no matter where the memory model is accessed.

A first embodiment of the present invention will be described below with reference to the accompanying drawings.
FIG. 1 shows a logic simulation environment to which the present invention is applied. This logic simulation environment shows the system configuration of the logic verification apparatus according to the present invention.
The logic simulation environment (logic verification device) 1 includes a CPU 10 and an external memory 20. The CPU 10 and the external memory 20 are connected by a memory R / W bus 30. Note that R / W indicates Read / Write.

  The logic simulation environment 1 checks whether the CPU 10 conforms to the specification by executing a verification program created by the verifier. In other words, logical verification is performed to confirm whether it functions correctly. If the operation is as expected, it is determined to be OK.

  The CPU 10 is a semiconductor integrated circuit to be subjected to logic verification, and reads an instruction code or data in the external memory 20 by performing Read / Write access to the external memory 20 via the memory R / W bus 30. , Execute instructions, write results, etc.

  The CPU 10 includes a CPU core 11 and a function model 12 for hard macro (memory) logic simulation.

  The CPU core 11 manages the internal logic of the CPU, which is a part to be subjected to logic verification. When data with an error is received, the CPU core 11 detects and processes an error such as a parity error based on the specification. Here, a parity error will be described as an example, but it is not actually limited to a parity error.

  The hard macro (memory) logic simulation function model 12 is a simulation model equivalent to the operation of a hard macro (memory) existing in an actual device.

  The external memory 20 has an error control memory area 21 and an instruction / data memory area 22. The error control memory area 21 and the instruction / data memory area 22 may be physically independent memories.

  The error control memory area 21 is a readable / writable area by Read / Write access from the CPU 11. Thereby, the occurrence of an error can be controlled.

  The instruction / data memory area 22 stores a verification program for logic verification and expected value data.

In FIG. 1, a test pattern file 40 is shown as a verification program.
The test pattern file 40 is obtained by converting a verification test program created based on the instruction set of the CPU 10 with an assembler or the like. The data is stored in the instruction / data memory area 22 as a memory image. When there are a plurality of hard macro (memory) logic simulation function models 12, by setting the address of the error control memory area 21 for each hard macro (memory) logic simulation function model, an error Generation can be controlled.

  Although only one hard macro (memory) is shown in FIG. 1, there are a plurality of memories depending on the internal configuration of the CPU 10. The function model 12 for hard macro (memory) logic simulation exists for each hard macro (memory) having different functions. FIG. 2 shows a case where there are a plurality of hard macro (memory) logic simulation function models 12 (12-i, i = 1 to n: n is arbitrary).

  The function model 12 for hard macro (memory) logic simulation includes a memory body 121, an error generation control circuit 122, and an error generation circuit 123. The error generation control circuit 122 and the error generation circuit 123 can be installed at any location on the CPU internal bus connected to the memory main body 121.

  The memory main body 121 is a hard macro (memory) inside the functional model 12 for hard macro (memory) logic simulation.

  The error generation control circuit 122 probes the data in the error control memory area 21 during the logic simulation. When the condition generated from the value of the error control memory area 21 matches the condition of the bus access from the CPU core 11, an error occurrence signal is output to the error generation circuit 123.

  The error generation circuit 123 receives the error generation signal from the error generation control circuit 122, generates a bus error according to the content, and returns data with an error to the CPU core 11. Alternatively, data with an error is stored in the memory main body 121.

Next, the overall operation of the present invention will be described with reference to FIG.
(1) Step S101
As shown in FIG. 4, the test program written by the verifier is converted into a test pattern file 40 by an assembler or the like, and stored in the instruction / data memory area 22 as a memory image.
(2) Step S102
When the reset is released, the CPU 10 reads an instruction from the external memory 20 and performs processing according to the instruction.
(3) Step S103
Depending on the test program, the error control memory area 21 may be described to read / write. Depending on the contents written in the error control memory area 21, the error generation control circuit 122 may cause an error in the write data and read data of the hard macro (memory) logic simulation function model 12. When an error occurs, the CPU core 11 performs exception processing based on the specification at the time of error detection, and then performs normal processing again.
(4) Step S104
When a series of operations described in the test pattern file 40 is performed, the process ends normally.
(5) Step S105
If the operation is against the specifications, it will end abnormally.

A logic simulation flow will be described with reference to FIG. Although a parity error is described here as an example, the present invention is not limited to a parity error in practice.
(A) When no parity error occurs When the reset is released after the simulation is started, the CPU 10 continues to process the instructions written in the test program. During this time, Read / Write to the external memory 20 and Read / Write to the function model 12 for hard macro (memory) logic simulation are performed. If a specification violation occurs during processing execution, the simulation ends abnormally. If a series of operations are performed without causing a specification violation, the simulation ends normally.
(B) When a parity error occurs After the simulation is started, a parity error occurrence condition is set by writing to the error control memory area 21. Parity error detection is performed based on the set conditions. If no parity error is detected, the simulation ends abnormally. If a parity error is detected, exception processing based on the specification at the time of parity error detection is performed. If a specification violation occurs even during exception processing, the simulation ends abnormally.

  Next, the details of the error control memory area 21 will be described with reference to FIG.

  FIG. 6 shows an example in which a condition is set for a hard macro (memory) N that, when Read access to address 0x2 occurs, if the read data is 0xffff_ff00, the 0th bit of the data is inverted and an error occurs. is there.

  In the example shown in FIG. 6, the CPU 10 divides the error control memory area 21 into the number (N) of hard macros (memory) and sets areas for hard macros (memory) 1 to N. Further, one hard macro (memory) N area (base address 0x0100) holds the contents of access address (offset 0x0), access data (offset 0x8), access type (offset 0x10), and error contents (offset 0x18). To do. During the logic simulation, reading / writing can be performed by a Load (read) / Store (store) instruction from the CPU core.

  Next, the details of the error generation control circuit 122 and the error generation circuit 123 will be described with reference to FIG.

  FIG. 7 shows an example of notifying the error generation circuit of an error occurrence signal for inverting the 0th bit of data when the read of the address 0x2 is performed and the read data is 0xffff_ff00 when the setting of FIG. 6 is performed. It is.

  As shown in FIG. 7, the error occurrence control circuit 122 includes a memory probe unit 1221 and an error occurrence condition check unit 1222.

  The memory probe unit 1221 probes the value of the error control memory area 21 during the logic simulation. The error generation control circuit 122 monitors the information in the external memory 20, the access address, access type, and access data (write data) from the CPU core 11 every cycle in synchronization with the rising edge of the clock in the memory probe unit 1221. Yes.

  The error occurrence condition check unit 1222 checks the data read by the memory probe unit 1221 and the access address, access type, write data, and read data output by the CPU core 11, and determines whether or not the condition is met. The determination may be performed by a program or the like.

  For example, Verilog HDL (hardware description language) can be implemented using PLI or the like, or an assign statement specifying a hierarchy.

For the sake of explanation, an image of description in Verilog HDL is shown below. However, actually, it is not limited to this example.
<Description example>
assign. TargetAddr = board. ExtMem. PErrAdr;
assign. TargetType = board. ExtMem. PErrTyp;
assign. TargetData = board. ExtMem. PErrDat;
always @ (possed clk) begin
Match = (TargetAddr == MemAddr)
& (TargetType == MemType)
& (TargetData == MemData);
end

  Here, “assign” indicates continuous assignment. For example, it corresponds to wiring connection of an electric circuit. “TargetAddr” indicates an access address as a condition. “TargetType” indicates an access type as a condition. “TargetData” indicates access data as a condition. “Board” indicates a semiconductor integrated circuit serving as a base. Here, a logic simulation environment (logic verification device) 1 is shown. “ExtMem” indicates the external memory 20. Here, an error control memory area 21 is particularly shown. That is, “board.ExtMem.PErrAdr” indicates an access address that is a value of the error control memory area 21. Similarly, “board.ExtMem.PErrTyp” indicates an access type that is a value of the error control memory area 21. “Board.ExtMem.PErrDat” indicates access data that is a value of the error control memory area 21. “Always @ (event formula)” is a block that is executed whenever an event in the event formula occurs. “Position clk” designates a case where the clock signal changes from 0 to 1. That is, it is synchronized with the rising edge of the clock signal. “Begin... End” is a general block range. “MemAddr” indicates an access address from the CPU core 11. “MemType” indicates an access type from the CPU core 11. “MemData” indicates access data from the CPU core 11. “Match = (TargetAddr == MemAddr) & (TargetType == MemType) & (TargetData == MemData);” indicates whether or not the condition is met. Here, if the access address, access type, and access data all match, it is determined that the condition is met. However, in practice, it may be determined that the condition is matched if any of the access address, the access type, and the access data matches.

  The error occurrence condition check unit 1222 outputs an error occurrence signal to the error generation circuit 123 if the condition is met.

  The error generation circuit 123 performs data inversion processing according to the content of the error generation signal.

  Next, referring to FIG. 8, during the logic simulation, the CPU 10 accesses the hard macro (memory) N area from the access address (0x2), access data (0xffff_ff00), access type (0x1), and error content (0x1). ) Will be described. That is, when the read data from address 0x2 is 0xffff_ff00, the 0th bit of the data is inverted.

(1) Step S201
The memory probe unit 1221 in the error occurrence control circuit 122 probes the value of the hard macro (memory) area.
(2) Step S202
The error occurrence condition check unit 1222 in the error occurrence control circuit 122 compares the actual access of the access address, access type, write data, and read data from the memory body 121 with the value of the memory probe unit 1221. If the condition is met, an error occurrence signal is output. Here, a signal for inverting the 0th bit of the read data is generated.
(3) Step S203
The error generation circuit 123 receives the error generation signal from the error generation control circuit 122, inverts the 0th bit of the read data, and passes the data with an error to the CPU core 11 as the read data.
(4) Step S204
The CPU core 11 receives data with an error and performs an operation defined in the specification.

  As described above, in the present invention, the error control memory area is provided outside the CPU, and the error generation control circuit and the error generation circuit are provided in the function model for hard macro (memory) logic simulation. By providing these in one logic simulation environment, the occurrence of a parity error can be controlled on the program during the simulation execution using the address from the CPU core to the function model for hard macro (memory) logic simulation. In the known technology, the occurrence of errors can be controlled only in a limited area of the memory model, but the present invention can solve this problem.

  According to the present invention, a logic simulation can be performed in consideration of the occurrence timing of a parity error. In addition, an error can be generated regardless of where the memory model is accessed. It is also possible to operate by replacing the parity with ECC. In addition, since the occurrence of a parity error can be controlled for each memory, it is possible to verify cases that cannot occur normally, such as simultaneous errors in a plurality of memories. Furthermore, it is possible to facilitate the analysis in the case where an analysis of a defective product that seems to be caused by a parity error in a real machine is performed by simulation.

The second embodiment of the present invention will be described below.
In the publicly-known technology described in the background art, since an error is controlled by a trigger (trigger) as an access, it is considered that a case (example) in which an error occurs at random timing cannot be handled.

  The basic configuration of the logic simulation environment (logic verification device) in this embodiment is the same as that in the first embodiment. This embodiment is characterized by Read (read) / Write (write) processing.

First, the Read process will be described.
In this embodiment, even when there is no read request, if the read type is set to “read” in the error control memory area 21 and the error occurrence condition check unit 1222 matches the random error occurrence condition, the error occurrence circuit An error is generated in the read data bus between the CPU 123 and the CPU core 11. This is performed to check an operation in which the CPU core 11 does not erroneously detect an error with respect to data output from the memory (for example, data at the previous read time).

Next, a write (write) process will be described.
In this embodiment, even when there is no write request, if “write” is set in the access type of the error control memory area 21 and the error occurrence condition check unit 1222 matches the random error occurrence condition, the error occurrence circuit An error is generated in the write data from 123 to the memory main body 121, and the data with the error is actually written in the memory main body.

  For example, assuming that the memory body is a cache memory of 4 sets (way), 4 sets of read data are output to the same read address. The CPU core 11 selects one set of necessary data from the read four sets of data and uses it.

  By randomly writing data with an error in the memory main body, the CPU core 11 checks the operation that the error is not erroneously detected even if an error has occurred in the data of a set that is not originally necessary.

  It is possible to omit the procedure of generating a write access from the CPU core 11, writing with an error, and then reading the set data that is not necessary at the time of reading again.

  The details of the error control memory area 21 in this embodiment will be described with reference to FIG.

  In this embodiment, the hard macro (memory) N is changed so that errors occur randomly. FIG. 9 shows that when the generation time interval is in the range of 0x00000100 to 0x0000ff00, the retention period is in the range of 0x00000001 to 0x000000ff, and the generation address is in the range of 0x00 to 0xff, the 0th bit of the data is inverted in the Read data and Write data, and an error occurs. This is an example in which a condition to do is set.

  In the example shown in FIG. 9, one hard macro (memory) N area (base address 0x0100) has a generated address (offset 0x0), generated time interval data (offset 0x8), access type (offset 0x10), and error contents. The content of (offset 0x18) is held. Comparing FIG. 6 and FIG. 9, “generation address” and “generation time interval data” are held instead of “access address” and “access data”. That is, “occurrence address” is held as “access address”, and “occurrence time interval data” is held as “access data”. The upper 32 bits of the “occurrence time interval data” are set as “holding period”, and the lower 32 bits of the “occurrence time interval data” are set as “occurrence time interval”.

  Next, the details of the error generation control circuit 122 and the error generation circuit 123 in this embodiment will be described with reference to FIG.

  FIG. 10 is basically the same as FIG. 7, but in this embodiment, the access address, access type, and access data (write data) from the CPU core 11 are not monitored during random setting.

The operation at the time of random setting will be described with reference to FIG.
The error generation condition check unit 1222 and the error generation circuit 123 in the error generation control circuit 122 perform the following operations and generate random errors.

(1) Step S301
The error generation circuit 123 generates a random number within the range indicated by the generation time interval. This is the number of clocks (A) until an error occurs.
(2) Step S302
The error generation circuit 123 generates a random number within the range indicated by the holding period. This is the number of clocks (B) in which the occurrence of errors continues.
(3) Step S303
The error generation circuit 123 generates a random number within the range indicated by the generation address. This is the address (C) where the error occurs.
(4) Step S304
The error occurrence condition check unit 1222 subtracts 1 from the number of clocks (A) for each clock.
(5) Step S305
The error generation circuit 123 generates an error when the clock number (A) becomes zero.
(6) Step S306
When the number of clocks (A) reaches 0, the error occurrence condition check unit 1222 subtracts 1 from the number of clocks (B) for each clock.
(7) Step S307
The error occurrence condition check unit 1222 checks the access type.
(8) Step S308
If the access type is “Read”, the error generation circuit 123 sets the read data path from the error generation circuit 123 to the CPU core 11 regardless of whether the read access occurs until the clock number (B) becomes zero. Generate an error according to the error content.
(9) Step S309
If the access type is Write, the error generating circuit 123 generates an error corresponding to the error content for the address (C) and writes it in the memory body.

  The above operation is repeated.

  In this embodiment, the timing of an error that occurs based on random settings is separated from the timing of memory access from the CPU core 11. That is, it is not a trigger.

The third embodiment of the present invention will be described below.
In this embodiment, an error is generated on an internal common bus that connects a CPU, memory, and I / O (Input / Output).

With reference to FIG. 12, the configuration of the CPU in this embodiment will be described.
In this embodiment, the CPU 10 includes a CPU core 11, a function model 12 for hard macro (memory) logic simulation, an I / O 13, a memory I / F (interface) 14, and an internal common bus 15.

  There may be a plurality of CPU cores 11 (11-j, j = 1 to m: m is arbitrary). That is, the CPU 10 includes at least one CPU core 11. In FIG. 12, a CPU core 11-1 and a CPU core 11-2 are shown as an example. The function model 12 for hard macro (memory) logic simulation includes a memory body 121, an error generation control circuit 122, and an error generation circuit 123. The I / O 13 is various input / output ports. The memory I / F 14 is an interface for connecting to the external memory 20. The internal common bus 15 is an internal bus for mutually connecting the CPU core 11, the function model 12 for hard macro (memory) logic simulation, the I / O 13, and the memory I / F 14.

  The CPU 10 and the external memory 20 are connected by a memory R / W bus 30. The external memory 20 has an error control memory area 21 and an instruction / data memory area 22. The error control memory area 21 provides data to the error generation control circuit 122.

  With this configuration, data read out from the hard macro (memory) logic simulation function model 12 onto the internal common bus 15 or the hard macro (memory) logic simulation function via the internal common bus 15. An error can be generated in the data written to the model 12.

Finally, features of the present invention will be described.
In the present invention, based on the data in the error control memory area outside the CPU, the error generation control circuit controls the error generation circuit to generate a parity error. Further, the error generation control circuit and the error generation circuit control errors for all addresses of the function model for hard macro (memory) logic simulation that is not logically synthesized. Therefore, a circuit for extending the bit width of a special address is not required for the CPU core. Further, the error generation method can be freely changed by changing the error generation control circuit and the error generation circuit. It is possible even after the processor has taped out.

  As described above, the present invention realizes the occurrence of an error during simulation without increasing the resources in the processor, and facilitates operation verification. Alternatively, it helps to reproduce the situation on the simulation when an error occurs during actual machine evaluation.

  The present invention can be applied to the logic verification field of microprocessors that require high reliability.

FIG. 1 is a configuration diagram of a logic simulation environment (logic verification apparatus) that is an object of the present invention. FIG. 2 is a diagram illustrating an example where a plurality of memories exist in the CPU. FIG. 3 is a flowchart showing the operation in the present invention. FIG. 4 is a diagram illustrating an example of a test program. FIG. 5 is a diagram for explaining the flow of logic simulation. FIG. 6 is a diagram for explaining the error control memory area in the first embodiment. FIG. 7 is a diagram for explaining the error generation control circuit and the error generation circuit in the first embodiment. FIG. 8 is a flowchart showing the operation when various data are written from the CPU to the hard macro (memory) area during the logic simulation. FIG. 9 is a diagram for explaining an error control memory area in the second embodiment. FIG. 10 is a diagram for explaining the error generation control circuit and the error generation circuit in the second embodiment. FIG. 11 is a flowchart showing an operation at the time of random setting. FIG. 12 is a diagram for explaining the CPU in the third embodiment.

Explanation of symbols

1 ... Logic simulation environment (logic verification device)
10 ... CPU
11 ... CPU core 12 ... Functional model for hard macro (memory) logic simulation 121 ... Memory body (hard macro (memory))
DESCRIPTION OF SYMBOLS 122 ... Error generation control circuit 1221 ... Memory probe part 1222 ... Error generation condition check part 123 ... Error generation circuit 20 ... External memory 21 ... Error control memory area 22 ... Instruction / data memory area

Claims (4)

  CPU,
  An error control memory connected to the CPU and holding information on an access address, access data, an access type, an occurrence time interval, a retention period, and an occurrence address as the error occurrence condition for logic verification;
Comprising
  The CPU
  CPU core,
  An internal memory connected to the CPU core via a bus;
  An error generation control circuit that outputs an error generation signal based on the error generation condition and the state of the bus access of the CPU during the logic verification;
  An error generation circuit for generating a bus error according to the content of the error generation signal;
Comprising
  The error generation control circuit includes:
  A memory probe for probing the value of the error control memory during logic verification; and
  When the data probed by the memory probe unit and the data output from the CPU core to the internal memory are compared, and the access condition from the CPU core to the internal memory matches the error occurrence condition In addition, an error occurrence condition check unit that outputs the error occurrence signal to the error generation circuit;
Comprising
  The error occurrence condition check unit sets a first clock number until an error occurs based on a random number within the range indicated by the occurrence time interval, and the error occurrence continues based on the random number within the range indicated by the holding period. A second clock number is set, an address as an error generation target is set based on a random number within the range indicated by the generated address, and the first clock number is subtracted by 1 for each clock, and the first clock number is When it reaches 0, subtract the second clock number by 1 for each clock, check the access type,
  The error generation circuit generates an error when the first clock number becomes zero, and if the access type is Read, the error generation circuit transfers from the error generation circuit to the CPU core until the second clock number becomes zero. An error corresponding to the error content is generated in the read data path, and if the access type is Write, an error corresponding to the error content is generated for the address and written to the internal memory.
  Logic verification device. The logic verification device according to claim 1 ,
When the internal memory is plural,
The error control memory holds the error occurrence condition for each of the plurality of internal memories,
The error generation control circuit and the error generation circuit are provided for each of the plurality of internal memories. The logic verification device according to claim 1 or 2 ,
The error control memory holds a random error occurrence condition for generating a random bus error,
The error generation circuit generates a bus error using a random timing and address based on the random error generation condition. The logic verification device according to any one of claims 1 to 3 ,
The error generation circuit performs data inversion processing according to the content of the error generation signal, and passes data with an error to the CPU core .

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