KR101917165B1 - Semiconductor memory apparatus - Google Patents

Abstract

The semiconductor memory device includes a pin reduction signal generating unit, first and second cyclic redundancy checking units, and first and second output units. The pin reduction signal generator receives the pin reduction mode entry signal and the test mode signal and generates a pin reduction signal. The first cyclic redundancy checker performs a cyclic redundancy check on a plurality of first data to generate first cyclic redundancy check data. The second cyclic redundancy checker performs a cyclic redundancy check on a plurality of second data to generate second cyclic redundancy check data. The first output unit outputs the first cyclic redundancy check data to the first error detection code output pin regardless of the state of the pin reduction signal. The second output unit is disabled when the pin reduction signal is inactive and outputs the second cyclic redundancy check data to the second error detection code output pin when the pin reduction signal is active.

Description

[0001] SEMICONDUCTOR MEMORY APPARATUS [0002]

The present invention relates to a semiconductor memory device, and more particularly, to a test circuit of a semiconductor memory device.

A packaged semiconductor memory device has a plurality of output pins for transferring a large amount of data.

1 is a diagram showing an output pin arrangement of a graphics DRAM among general semiconductor memory devices.

The semiconductor memory device shown in Fig. 1 has a total of 40 output pins. At this time, the output pin has a plurality of data input / output pins DQ <0: 7>, DQ <8:15>, DQ <16:23>, DQ <24:31>, data bus inversion information output And the error detection code output pins EDC <0>, EDC <1>, EDC <2>, EDC <2>, and DBC < &Lt; 3 &gt;).

The data input / output pins DQ <0: 7>, DQ <8:15>, DQ <16:23>, and DQ <24:31> serve to input or output data stored in the semiconductor memory device .

The data bus inversion information output pins DBI <0>, DBI <1>, DBI <2> and DBI <3> serve to output data bus inversion information. The data bus inversion information is a signal that is activated when the number of bits whose logical value is changed from the previous data bit is half or more. This data bus inversion signal has a problem that is caused by an increase in the number of logical values of the current data bit compared to the previous data bits in the entire data bits during data transmission, i.e., simultaneous switching noise or internal symbol interference inter symbol interference).

The error detection code output pins EDC <0>, EDC <1>, EDC <2> and EDC <3> serve to output an error detection code. The error detection code is a signal generated in order to ensure the reliability of data transfer. Recently, the semiconductor memory device has recently performed a cyclic redundancy check (Cyclic Redundancy Check) on the stored data, Output to the code. In one embodiment, the stored data and the data bus inversion signal for the data may be received to perform the cyclic redundancy check. When the inspection is completed, the error detection code output from the outside can be discriminated and it can be determined whether or not there is an error in the data output result.

At this time, data bus inversion information and error detection code for the data allocated to DQ <0: 7> are output as DBI <0> and EDC <0>, respectively, and data for data allocated to DQ < The bus reversal information and the error detection code are output as DBI <1> and EDC <1>, respectively, and the data bus inversion information and error detection code for data allocated to DQ <16:23> are DBI < <2>, and data bus inversion information and error detection code for data allocated to DQ <24:31> are output as DBI <3> and EDC <3>, respectively.

1 uses data input / output pins DQ <0: 7>, DQ <8:15>, DQ <16:23>, and DQ <24:31> X32 mode, but it is also possible to input and output data by using half of the data input / output pins as in the x16 mode. In FIG. 1, four sets of input / output pins are shown. In the x16 mode, data can be input / output through the left data input / output pins (DQ <0: 7>, DQ <16:23>). That is, when the write operation is performed in the x16 mode, data can be written to all the memory cells through half of the data input / output pins (DQ <0: 7> and DQ <16:23>), , The data of all the memory cells can be read out via the half data input / output pins (DQ <0: 7>, DQ <16:23>). At this time, only DBI <0> and DBI <2> are activated in the data bus inversion information output pin, and only EDC <0> and EDC <2> are activated in the error detection code output pin.

This pin reduction mode is useful in test mode. When the package test is performed, the number of semiconductor memory devices connected to the test board is limited. When the pin reduction mode is executed, more semiconductor memory devices can be tested simultaneously.

However, if the test is performed in the pin reduction mode, it is possible to perform test on many semiconductor memory devices at the same time, but the operation of reading and outputting data not allocated to the connected I / O pins must be performed, have. That is, if you run the test in x16 mode, you can connect twice as many semiconductor memory devices to the test board as in x32 mode, but it takes twice the test time.

The present invention provides a scheme for efficiently testing a semiconductor memory device.

A semiconductor memory device according to an embodiment of the present invention includes a plurality of data input / output pins and a plurality of error detection code output pins. In the pin reduction mode, only a part of the plurality of data input / And outputting an error detection code assigned to the plurality of error detection code output pins using only a part of the plurality of error detection code output pins, wherein when the test is performed in the pin reduction mode, And outputting the error detection code assigned to each of the plurality of test patterns.

A semiconductor memory device according to an embodiment of the present invention includes a pin reduction signal generator for receiving a pin reduction mode input signal and a test mode signal and generating a pin reduction signal; A first cyclic redundancy check unit for performing a cyclic redundancy check on a plurality of first data to generate first cyclic redundancy check data; A second cyclic redundancy check unit for performing a cyclic redundancy check on a plurality of second data to generate second cyclic redundancy check data;

A first output unit for outputting the first cyclic redundancy check data to a first error detection code output pin regardless of a state of the pin reduction signal; And a second output unit for outputting the second cyclic redundancy check data to the second error detection code output pin if the pin reduction signal is in an inactive state and the pin reduction signal is in an active state.

A semiconductor memory device according to an embodiment of the present invention receives a pin reduction mode input signal and a test mode signal to generate a pin reduction signal and generates first and second strobe signals based on the state of the pin reduction signal, A signal generator for generating a second serialization signal and first and second output enable signals; A first cyclic redundancy check unit for performing a cyclic redundancy check on a plurality of first data to generate a plurality of first cyclic redundancy check data; A second cyclic redundancy check unit for performing a cyclic redundancy check on a plurality of second data to generate a plurality of second cyclic redundancy check data; A transfer unit for transferring the first and second cyclic redundancy check data in response to the first and second strobe signals; Serializing the plurality of first cyclic redundancy check data in response to the first serialization signal and outputting the first cyclic redundancy check data serialized in response to the first output enable signal to a first error detection code output pin A first output unit for outputting a first output signal; And serializing the plurality of second cyclic redundancy check data in response to the second serialization signal and outputting the second cyclic redundancy check data serialized in response to the second output enable signal to a second error detection code output pin And a second output unit for outputting the output signal.

According to the present technique, it is possible to perform a quick and efficient test on a plurality of semiconductor memory devices.

BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a diagram showing an output pin arrangement of a general semiconductor memory device,
2 is a block diagram of a test circuit of a semiconductor memory device according to an embodiment of the present invention;
FIG. 3 is a block diagram showing a concrete embodiment of the transmission unit of FIG. 2. FIG.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2 is a block diagram of a test circuit 20 of a semiconductor memory device according to an embodiment of the present invention.

The test circuit 20 shown in FIG. 2 may be inserted into the semiconductor memory device 100 shown in FIG. The test circuit 20 outputs an error detection code as test data through an error detection code output pin (EDC <0>, EDC <1>). FIG. 2 illustrates a test data output path for a plurality of first data (DATA_u <0:63>) allocated to DQ <0: 7> and a plurality of And the test data output path for the second data (DATA_d <0:63>) is shown as an example.

The test circuit 20 of the semiconductor memory device shown in FIG. 2 includes a test data output section 20A and a signal generation section 20B.

The signal generation unit 20B includes a pin reduction signal generation unit 21.

The pin reduction signal generation unit 21 receives the pin reduction mode entry signal RDC_in and the test mode signal TM and generates a pin reduction signal RDC. The pin deactivating mode entering signal RDC_in is a signal activated when the semiconductor memory device is intended to execute the pin deactivating mode. The test mode signal TM is a signal activated when the semiconductor memory device is to be tested.

The pin reduction signal generation unit 21 activates the pin reduction signal RDC when only the pin reduction mode entry signal RDC_in is activated, that is, when the entire semiconductor memory device operates normally in the pin reduction mode. As will be described in detail below, the pin reduction signal RDC includes first and second error detection codes EDC_u and EDC_d to the first and second error detection code output pins EDC <0> and EDC <1> It is a signal that determines whether pin reduction operation is performed for output. That is, when the pin reduction signal RDC is activated, only the first error detection code output pin EDC <0> among the first and second error detection code output pins EDC <0> and EDC <1> The first error detection code EDC_u is output. Of course, only the second error detection code output pin EDC <1> may be operated according to the setting.

On the other hand, when both the pin-down mode entering signal RDC_in and the test mode signal TM are activated, that is, when the entire semiconductor memory device performs the test operation in the pin-down mode And deactivates the pin reduction signal RDC. When the pin reduction signal RDC is inactivated, the first and second error detection code output pins EDC <0> and EDC <1> respectively output the first and second error detection codes EDC_u and EDC_d .

Specifically, the pin reduction signal generating unit 21 may be implemented with a first inverter IV1 and a first AND gate AD1 as shown in FIG. The first inverter IV1 inverts the test mode signal TM and outputs the inverted test mode signal TM. The first AND gate AD1 receives the output signal of the first inverter IV1 and the pin reduction mode entry signal RDC_in and outputs a pin reduction signal RDC. Accordingly, when the pin-reduction mode entering signal RDC_in is activated while the test mode signal TM is inactive, the pin-reducing signal RDC is activated. On the other hand, even if the PIN reduction mode entry signal RDC_in is activated, the PIN reduction signal RDC is inactivated when the test mode signal TM is activated.

That is, according to the embodiment of the present invention, when the test is performed in the pin reduction mode, all the data can not be output simultaneously to the data output pin because of the pin reduction mode. Instead, all the error detection code output pins (EDC <0> (EDC_u, EDC_d) containing the error information of the entire data output in the EDC <1> as the test data, it is possible to judge whether there is an error in the data output from the outside.

The signal generator 20B may further include a strobe signal generator 24, a serialization signal generator 25 and an output enable signal generator 26. [

The strobe signal generator 24 receives the first and second strobe control signals stb_ctrl <0: 1> and generates the first and second strobe signals strobe <0: 1> based on the state of the pin reduction signal RDC. 0: 1 &gt;). The first and second strobe control signals stb_ctrl &lt; 0: 1 &gt; each include a cyclic redundancy check result for a plurality of first data DATA_u &lt; 0:63 &gt; >) It is the signal which is activated when it wants to output the result of the cyclic redundancy check.

If the first and second strobe control signals stb_ctrl <0: 1> are activated when the pin reduction signal RDC is inactive, the strobe signal generator 24 generates the first and second strobe signals strobe <0: 1>). On the other hand, when the pin reduction signal RDC is activated, the first strobe signal strobe < 0 > is activated even if the first and second strobe control signals stb_ctrl < 0: 1 & 2 Strobe signal (strobe <1>) is deactivated.

Specifically, the strobe signal generator 24 stops the output of the second strobe signal strobe <1> from the second strobe control signal stb_crtl <1> in response to the pin reduction signal RDC. (Not shown).

The strobe signal generator 24 may generate the first and second strobe signals stro <0: 1> and generate an activated serialization control signal after a predetermined time.

The serialization signal generator 25 receives the serialization control signal pin and generates the first and second serialization signals pin_u and pin_d based on the state of the pin reduction signal RDC. The first and second serialization signals pin_u and pin_d are used to generate a cyclic redundancy check result for the plurality of first data DATA_u <0:63> transmitted in parallel and a plurality of second data DATA_d <0: Lt; 63 >).

The serialization signal generator 25 activates both the first and second serialization signals pin_u and pin_d when the serialization control signal pin is activated when the pin reduction signal RDC is inactivated. On the other hand, when the pin reduction signal RDC is activated, the first serialization signal pin_u is activated and the second serialization signal pin_d is inactivated even if the serialization control signal pin is activated.

Specifically, the serialization signal generator 25 generates a pass gate (not shown) for interrupting the output of the second serialization signal pin_d from the serialization control signal pin in response to the pin reduction signal RDC .

That is, after the cyclic redundancy check result is generated for the first and second data, the serialization signal generator 25 determines whether the results are serialized according to the state of the pin reduction signal RDC .

The output enable signal generator 26 receives the output enable control signal outen and outputs the first and second output enable signals outen_u and outen_d based on the state of the pin reduction signal RDC . The output enable control signal outen is a signal that is activated when the test data is to be output to the outside. The first and second output enable signals outen_u and outen_d are respectively applied to the cyclic redundancy check result and the second data DATA_d <0:63> for the serialized first data (DATA_u <0:63>) Is a signal for determining whether to output the cyclic redundancy check result to the first and second error detection code output pins EDC <0> and EDC <1>.

The output enable signal generator 26 generates the first and second output enable signals outen_u and outen_d when the output enable control signal outen is activated when the pin reduction signal RDC is inactivated, Respectively. On the other hand, when the pin reduction signal RDC is activated, the first output enable signal outen_u is activated and the second output enable signal outen_d is activated even if the output enable control signal outen is activated Deactivated.

Specifically, the output enable signal generator 26 generates a signal for blocking the output of the second output enable signal outen_d from the output enable control signal outen in response to the pin reduction signal RDC. Gate (not shown).

The test data output section 20A includes first and second cyclic redundancy check sections 22 and 23, a transfer section 27 and first and second output sections 28 and 29. [

The first cyclic redundancy check unit 22 performs a cyclic redundancy check on a plurality of first data DATA_u <0:63> to generate a plurality of first cyclic redundancy check data (CRC_u <0: 7>) . At this time, the first cyclic redundancy checking unit 22 receives the data bus inversion information (DBI_u <0: 7>) for the plurality of first data together with the first data (DATA_u <0:63> The cyclic redundancy check can be performed.

The second cyclic redundancy check unit 23 performs a cyclic redundancy check on a plurality of second data (DATA_d <0: 63>) to generate a plurality of first cyclic redundancy check data (CRC_d <0: 7>) . At this time, the second cyclic redundancy checking unit 23 receives the data bus inversion information (DBI_d <0: 7>) for the plurality of second data together with the plurality of second data (DATA_d <0:63> The cyclic redundancy check can be performed.

The first and second cyclic redundancy checking units 22 and 23 may be implemented with a general CRC circuit.

The transfer unit 27 transfers the first and second cyclic redundancy check data CRC_u <0: 7>, CRC_d <0: 7> in response to the first and second strobe signals strobe <0: 1> &Gt;). The transfer unit 27 transfers the first cyclic redundancy check data CRC_u <0: 7> to the first output unit 28 when the first strobe signal strobe <0> is activated. And transmits the second cyclic redundancy check data CRC_d <0: 7> to the second output unit 29 when the second strobe signal strobe <1> is activated.

Fig. 4 is a block diagram showing a concrete embodiment of the transfer unit 27. Fig.

The transfer unit 27 receives one bit from the first and second cyclic redundancy check data (CRC_u <0: 7>, CRC_d <0: 7>) of a plurality of bits and outputs the first and second strobe signals and first to eighth selection transfer units 27_1 to 27_8 for determining whether to transmit the corresponding bit according to strobe <0: 1>. The number of the selective transfer units can be adjusted according to the number of bits of the first and second cyclic redundancy check data (CRC_u <0: 7>, CRC_d <0: 7>).

The operation of the first selection transfer unit 27_1 will be described below as an example. When the normal operation is performed in the pin reduction mode, the first strobe signal (strobe <0>) is activated but the second strobe signal (strobe <1>) is deactivated and applied. Therefore, the first selection transfer unit 27_1 delivers CRC_u <0> to CRC_du <0>, but blocks transmission of CRC_d <0>.

On the other hand, when the test operation is performed in the pin reduction mode, both the first and second strobe signals strobe <0: 1> are activated and applied. Therefore, the first selection transfer unit 27_1 transfers CRC_u <0> to CRC_du <0>, and transmits CRC_d <0> to CRC_dd <0>.

Specifically, the first selection transfer unit 27_1 includes a pass gate (not shown) for determining whether or not to block transfer of CRC_u <0> in response to the first strobe signal (strobe <0>), (not shown) for determining whether or not the transmission of CRC_d <0> is blocked in response to the strobe <1>.

The second to eighth selective transfer units 27_2 to 27_8 are configured and operated as described above to generate the first and second cyclic redundancy check data CRC_u <0: 7>, CRC_d <0: 7> To the first output unit 28 and the second output unit 29, respectively.

The first output unit 28 outputs the first cyclic redundancy check data CRC_du <0: 7> to the first error detection code output pin EDC <0> with the first error detection code EDC_u Lt; / RTI &gt;

Specifically, the first output unit 28 serializes the first cyclic redundancy check data (CRC_du <0: 7>) transmitted when the first serialization signal pin_u is activated, and the first output enable When the signal outen_u is activated, the serialized first cyclic redundancy check data is output to the first error detection code output pin EDC <0> by the first error detection code EDC_u. The first output unit 28 includes a pipe latch (not shown) for serializing the transferred first cyclic redundancy check data (CRC_du <0: 7>) in response to the first serialization signal pin_u, And an output driver (not shown) for outputting the first error detection code EDC_u in response to the first output enable signal outen_u.

The second output unit 29 outputs the second cyclic redundancy check data CRC_dd <0: 7> to the second error detection code EDC_u and the second error detection code output pin EDC <1> Lt; / RTI &gt;

Specifically, the second output unit 29 serializes the second cyclic redundancy check data (CRC_dd <0: 7>) transmitted when the second serialization signal pin_d is activated, and the second output enable When the signal outen_d is activated, the serialized second cyclic redundancy check data is output to the second error detection code output pin EDC <1> by the second error detection code EDC_d. The second output unit 29 includes a pipe latch (not shown) for serializing the transferred second cyclic redundancy check data (CRC_dd <0: 7>) in response to the second serialization signal pin_d, And an output driver (not shown) for outputting a second error detection code EDC_d in response to the second output enable signal outen_d.

That is, when the test is performed in the pin reduction mode, the first and second output units 28 and 29 are respectively supplied with the first and second error detection code output pins EDC <0> and EDC <1> 1 and the second error detection codes EDC_u and EDC_d as test data.

The semiconductor memory device according to the embodiment of the present invention outputs data by using only a part of the output pins when the semiconductor memory device operates normally in the pin reduction mode but when the test operation is performed in the pin reduction mode, And outputting the corresponding error detection code as the test data, it is possible to determine whether or not the entire data output result is erroneous at the same time.

It will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the present invention as defined by the following claims and their equivalents. Only. The scope of the present invention is defined by the appended claims rather than the detailed description and all changes or modifications derived from the meaning and scope of the claims and their equivalents are to be construed as being included within the scope of the present invention do.

100: semiconductor memory device 20: test circuit
20A: Test data output section 20B:
21: pin reduction signal generating unit 22: first cyclic redundancy check unit
23: second cyclic redundancy checking unit 24: strobe signal generating unit
25: serialization signal generator 26: output enable signal generator
27: transfer part 28: first output part
29: second output section

Claims (22)

A plurality of data input / output pins and a plurality of error detection code output pins, wherein in a pin reduction mode, only a part of the plurality of data input / output pins is used to output data assigned thereto, and only a part of the plurality of error detection code output pins And outputting an error detection code assigned to the semiconductor memory device,
And a test circuit for outputting the error detection code assigned to each of the plurality of error detection code output pins through the plurality of error detection code output pins as a whole when the test is performed in the pin reduction mode. ◈ Claim 2 is abandoned due to payment of registration fee. The method according to claim 1,
Wherein each of the error detection codes is generated by performing a cyclic redundancy check on the allocated data. A pin reduction signal generation unit for receiving a pin reduction mode entry signal and a test mode signal to generate a pin reduction signal;
A first cyclic redundancy check unit for performing a cyclic redundancy check on a plurality of first data to generate first cyclic redundancy check data;
A second cyclic redundancy check unit for performing a cyclic redundancy check on a plurality of second data to generate second cyclic redundancy check data;
A first output unit for outputting the first cyclic redundancy check data to a first error detection code output pin regardless of a state of the pin reduction signal; And
And a second output unit for outputting the second cyclic redundancy check data to the second error detection code output pin if the pin reduction signal is in an inactive state and disabled if the pin reduction signal is in an inactive state. ◈ Claim 4 is abandoned due to the registration fee. The method of claim 3,
Wherein the pin reduction signal generating unit comprises:
Activates the pin reduction signal when only the pin reduction mode entering signal is activated,
And deactivates the pin reduction signal when both the pin reduction mode entry signal and the test mode signal are activated. ◈ Claim 5 is abandoned due to the registration fee. The method of claim 3,
Wherein the first cyclic redundancy check unit comprises:
And performs data cyclic redundancy checking by receiving data bus inversion information for the plurality of first data together with the plurality of first data. ◈ Claim 6 is abandoned due to the registration fee. The method of claim 3,
Wherein the second cyclic redundancy check unit comprises:
And data bus inversion information for the plurality of second data together with the plurality of second data to perform the cyclic redundancy check. ◈ Claim 7 is abandoned due to registration fee. The method of claim 3,
And an output enable signal generating section for receiving the output enable control signal and the pin reduction signal to generate a first output enable signal and a second output enable signal. ◈ Claim 8 is abandoned due to the registration fee. 8. The method of claim 7,
Wherein the output enable signal generator comprises:
When the pin enable signal is inactivated when the output enable control signal is activated, activating both the first and second output enable signals,
And activates the first output enable signal and deactivates the second output enable signal if the pin reduction signal is active when the output enable control signal is activated. ◈ Claim 9 is abandoned upon payment of registration fee. 9. The method of claim 8,
Wherein the first output unit comprises:
And outputs the first cyclic redundancy check data to the first error detection code output pin with a first error detection code when the first output enable signal is activated. ◈ Claim 10 is abandoned due to the registration fee. 9. The method of claim 8,
Wherein the second output unit comprises:
And outputs the second cyclic redundancy check data to the second error detection code output pin with a second error detection code when the second output enable signal is activated. Receiving a pin reduction mode entry signal and a test mode signal to generate a pin reduction signal and outputting the first and second strobe signals, the first and second serialization signals, and the first and second outputs A signal generator for generating an enable signal;
A first cyclic redundancy check unit for performing a cyclic redundancy check on a plurality of first data to generate a plurality of first cyclic redundancy check data;
A second cyclic redundancy check unit for performing a cyclic redundancy check on a plurality of second data to generate a plurality of second cyclic redundancy check data;
A transfer unit for transferring the first and second cyclic redundancy check data in response to the first and second strobe signals;
Serializing the plurality of first cyclic redundancy check data in response to the first serialization signal and outputting the first cyclic redundancy check data serialized in response to the first output enable signal to a first error detection code output pin A first output unit for outputting a first output signal; And
Serializing the plurality of second cyclic redundancy check data in response to the second serialization signal and outputting the second cyclic redundancy check data serialized in response to the second output enable signal to a second error detection code output pin And a second output section for outputting the second output signal. ◈ Claim 12 is abandoned due to registration fee. 12. The method of claim 11,
Wherein the signal generator comprises:
A pin reduction signal generation unit receiving the pin reduction mode entry signal and the test mode signal and generating the pin reduction signal;
A strobe signal generator for receiving the first and second strobe control signals and generating the first and second strobe signals based on the state of the pin reduction signal;
A serialization signal generator for receiving the serialization control signal and generating the first and second serialization signals based on the state of the pin reduction signal;
And an output enable signal generator for receiving the output enable control signal and generating the first and second output enable signals based on the state of the pin reduction signal. ◈ Claim 13 is abandoned due to registration fee. 13. The method of claim 12,
Wherein the pin reduction signal generating unit comprises:
Activates the pin reduction signal when only the pin reduction mode entering signal is activated,
And deactivates the pin reduction signal when both the pin reduction mode entry signal and the test mode signal are activated. ◈ Claim 14 is abandoned due to registration fee. 13. The method of claim 12,
Wherein the first and second strobe control signals are activated when the first and second cyclic redundancy check data are to be output, respectively,
Wherein the strobe signal generator comprises:
Wherein when the first and second strobe control signals are activated, both the first and second strobe signals are activated when the pin reduction signal is inactivated,
And activates the first strobe signal and deactivates the second strobe signal even if the first and second strobe control signals are activated when the pin reduction signal is activated. ◈ Claim 15 is abandoned due to registration fee. 15. The method of claim 14,
Wherein the strobe signal generator comprises:
And generates the first and second strobe signals and generates the serialization control signal activated after a predetermined time. ◈ Claim 16 is abandoned due to registration fee. 13. The method of claim 12,
Wherein the serialization signal generator comprises:
And activating the first and second serialization signals when the serialization control signal is activated when the pin reduction signal is inactivated,
And activates the first serialization signal and deactivates the second serialization signal even if the serialization control signal is activated when the pin reduction signal is activated. ◈ Claim 17 is abandoned due to registration fee. 13. The method of claim 12,
Wherein the output enable signal generator comprises:
When the pin enable signal is inactivated, activating both the first and second output enable signals when the output enable control signal is activated,
And activates the first output enable signal and deactivates the second output enable signal even if the output enable control signal is activated when the pin reduction signal is activated. ◈ Claim 18 is abandoned due to registration fee. 12. The method of claim 11,
Wherein the first cyclic redundancy check unit comprises:
And performs data cyclic redundancy checking by receiving data bus inversion information for the plurality of first data together with the plurality of first data. ◈ Claim 19 is abandoned due to registration fee. 12. The method of claim 11,
Wherein the second cyclic redundancy check unit comprises:
And data bus inversion information for the plurality of second data together with the plurality of second data to perform the cyclic redundancy check. ◈ Claim 20 is abandoned due to registration fee. 12. The method of claim 11,
[0030]
A plurality of selection units for transferring the first cyclic redundancy check data to the first output unit when the first strobe signal is activated and transferring the second cyclic redundancy check data to the second output unit when the second strobe signal is activated, And a transfer portion. ◈ Claim 21 is abandoned due to registration fee. 12. The method of claim 11,
Wherein the first output unit comprises:
Serializing the plurality of first cyclic redundancy check data transmitted from the transfer unit when the first serialization signal is activated and outputting the first cyclic redundancy check data serialized when the first output enable signal is activated, And outputting the detection code to the first error detection code output pin. ◈ Claim 22 is abandoned due to registration fee. 12. The method of claim 11,
Wherein the second output unit comprises:
Serializing the second cyclic redundancy check data transmitted from the transfer unit when the second serialization signal is activated and outputting the second cyclic redundancy check data serialized when the second output enable signal is activated to a second error And outputting the detection code to the second error detection code output pin.

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