JP2010211654A - Data transfer method and device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To read one group of data from a buffer device to a transfer destination processing unit before the whole writing from a transfer origin processing unit to the buffer device is completed for one group of data. <P>SOLUTION: When writing one group of data comprising a plurality of components transferred from the transfer origin processing unit 10 in the buffer device 20 in a write order the same as or different from the arrangement order of the one group of data in the arrangement order, reading the one group of data from the buffer device 20 in the read order the same as or different from the arrangement order and transferring them to the transfer destination processing unit 30, the number f of cycles is obtained corresponding to the maximum value within differences for which the read order is subtracted from the write order in the respective arrangement orders of the one group of data, and the read of the one group of data from the buffer device is started after the lapse of the number f of cycles from the write start of the one group of data to the buffer device 20. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a data transfer method and apparatus for transferring a group of data (one transaction) composed of a plurality of components from a transfer source processing unit to a transfer destination processing unit.

  In parallel processing using a pipeline structure, regarding the transfer of transactions between processing units, the interval of each processing unit and the order of writing / reading are designed and analyzed in advance to synthesize a fixed processing circuit, or double buffer And a multi-buffer method (for example, see Non-Patent Documents 1 and 2).

  When transferring a group of data (1 transaction), for example, 8 data in 8 cycles, normally, as shown in FIG. 8, when a write start command is generated, the transfer source processing unit 10 Write data Wi is written in the buffer device 20 in the order of, for example, W 1 → W 5 → W 2 → W 6 → W 3 → W 7 → W 4 → W 8. The subscript i indicates the order of data arrangement. In the buffer device 20, the data is stored in the address i in the order i of the data arrangement. That is, the write data Wi is stored at the i-th address of the buffer device 20. Here, at the time of design, when the order of data writing is not fixed as described above (1 → 5 → 2 → 6 → 3 → 7 → 4 → 8), the start of reading is the data writing. Must be done after all is done (after 8 cycles).

  Then, after the read start command is generated, the read data Ri is read by the transfer destination processing unit 30 in the order of, for example, R1, R2, R3, R4, R5, R6, R7, R8 (Ri = Wi). is there). Also, during this reading, if the reading order is not fixed as described above (1 → 2 → 3 → 4 → 5 → 6 → 7 → 8), in order to prevent overwriting of unread data. However, the next write cannot be started.

  If it is necessary to start the next writing during reading, another set of buffer devices is prepared and the control is switched alternately. This is a double buffer.

  However, in the method of synthesizing a fixed processing circuit by performing design analysis in advance, redesign is required every time the order of writing and reading of processing units changes. In order to avoid this, when a method using a double buffer or a multi-buffer is employed, there are problems such as an increase in the amount of memory used as a buffer and an increase in latency of the entire process.

  An object of the present invention is to enable reading from a buffer device to a transfer destination processing unit before all writing from the transfer source processing unit to the buffer device is completed for a group of data composed of a plurality of components. It is an object of the present invention to provide a data transfer method and apparatus capable of reducing the overall processing latency without increasing the processing speed.

  In order to achieve the above object, according to a first aspect of the present invention, a group of data consisting of a plurality of components transferred from a transfer source processing unit is written in the same or different writing order as the arrangement order of the group of data. In the data transfer method of writing to the buffer device according to the arrangement order, reading the group of data from the buffer device in the same or different reading order as the arrangement order, and transferring the data to the transfer destination processing unit. The number of cycles f is obtained according to the maximum value of the difference obtained by subtracting the reading order from the writing order in each data arrangement order, and the number of cycles from the start of writing the group of data to the buffer device. After the elapse of f, reading of the group of data from the buffer device is started.

The invention according to claim 2 is the data transfer method according to claim 1, wherein the number of cycles f is:
f = 1 + max (Tw (i) −Tr (i))
Here, i = 1, 2,..., N (n is the number of components of a group of data)
Tw (i) is the order of writing the components in the i-th order
Tr (i) is obtained in the reading order of the components in the i-th arrangement order.

  According to a third aspect of the present invention, in the data transfer method according to the first or second aspect, when a predetermined condition is satisfied in a cycle next to the start of the reading, a reading abnormality is displayed. To do.

According to a fourth aspect of the present invention, in the data transfer method according to the third aspect, the predetermined condition for displaying the read abnormality is:
(F−g) ≧ n
Where n is the number of components of a group of data
f = 1 + max (Tw (i) −Tr (i))
g = 1 + min (Tw (i) -Tr (i))
i = 1, 2,..., n
Tw (i) is the writing order of the components in the i-th order
Tr (i) is characterized in that it is the reading order of the components in the i-th arrangement order.

  According to a fifth aspect of the present invention, a group of data transferred from a transfer source processing unit is transferred to a buffer device in the same or different writing order as the order of arrangement of the group of data in the order of arrangement. In the data transfer device that reads the group of data from the buffer device in a reading order that is the same as or different from the arrangement order and transfers the data to the transfer destination processing unit, the writing order of the group of data is stored. A writing order storage device; and a reading order storage device for storing the reading order of the group of data, the writing order of the writing order storage device in each arrangement order from the writing order of the reading order storage device The number of cycles f is obtained according to the maximum value of the difference obtained by subtracting the reading order, and the group of data to the buffer device is obtained. From the write start, after the lapse of the cycle number f, starts reading of the first group of data from said buffer unit, and wherein the.

The invention according to claim 6 is the data transfer apparatus according to claim 5, wherein the cycle number f is:
f = 1 + max (Tw (i) −Tr (i))
Here, i = 1, 2,..., N (n is the number of components of a group of data)
Tw (i) is the writing order of the components in the i-th order of the writing order storage device. Tr (i) is obtained by the reading order of the components in the i-th order of the reading order storage device. And

  The invention according to claim 7 is the data transfer device according to claim 5 or 6, wherein a read error is displayed when a predetermined condition is satisfied in a cycle next to the start of the read. .

The invention according to claim 8 is the data transfer device according to claim 7, wherein the predetermined condition for displaying the read abnormality is:
(F−g) ≧ n
Where n is the number of components of the data in one group f = 1 + max (Tw (i) −Tr (i))
g = 1 + min (Tw (i) -Tr (i))
i = 1, 2,..., n
Tw (i) is the writing order of the i-th order component of the writing order storage device Tr (i) is the reading order of the i-th order component of the reading order storage device It is characterized by.

  According to the present invention, even when a processing unit whose processing characteristics vary due to the characteristics of the processing unit, changes in load, etc. is connected to construct a synchronous processing system, a group of data consisting of a plurality of components With respect to, before all writing from the transfer source processing unit to the buffer device is completed, reading from the buffer device to the transfer destination processing unit becomes possible. That is, even when a change occurs in the order of writing or reading by the processing unit during the execution of the operation, the reading start of the transfer destination processing unit can be autonomously adjusted. When the adjustment cannot be completed, the occurrence of abnormality can be displayed. Therefore, in a design method in which a system is constructed by transaction connection of functional parts, it is possible to suppress performance loss in transfer and resource consumption such as parts and power. As a result, the amount of memory in the buffer device can be reduced without employing a double buffer, and the processing on the transfer destination processing unit side can be started without waiting for the buffer device to complete writing. Can be reduced.

It is explanatory drawing of the data transfer apparatus of one Example of this invention. It is explanatory drawing of the writing to a writing order storage apparatus. It is explanatory drawing of the writing to a writing order storage apparatus and a reading order storage apparatus. It is explanatory drawing of a type | formula. It is explanatory drawing of the writing / reading of the data transfer apparatus of a present Example. It is a flowchart of operation | movement of the data transfer apparatus of a present Example. It is a flowchart of operation | movement of the data transfer apparatus of a present Example. It is explanatory drawing of the conventional data transfer apparatus.

  FIG. 1 shows a schematic configuration of a data transfer apparatus according to one embodiment of the present invention. 10 is a transfer source processing unit for transferring processed data, 20 is a buffer device, 30 is a transfer destination processing unit for receiving and processing data, 41 is a writing order storage device comprising buffers, and 42 is a similar reading order. A storage device 50 is an arithmetic unit.

  The transfer source processing unit 10 executes writing to the buffer device 20 when outputting the processing result during the processing. At this time, the data D (i) of the value Vs written to the buffer device 20 by the writing order Sws is given by the transfer source processing unit 10. i indicates the data arrangement order (address i of the buffer device 20), and i = 1, 3,..., 8 in this embodiment. The transfer source processing unit 10 transitions the value of the write order Sws as necessary. This transfer can be arbitrarily determined by the transfer source processing unit 10. For example, even if the writing order is first 1 → 5 → 2 → 6 → 3 → 7 → 4 → 8, it may be the same in the next cycle, or a part of the order may be changed. The data arrangement order i and the writing order Sws may be the same or different. When the writing order Sws is 1 → 2 → 3 → 4 → 5 → 6 → 7 → 8, it is the same as the data arrangement order i.

  The transfer destination processing unit 30 reads out the buffer device 20 when referring to the processing result during the processing. At this time, data D (i) appears as a value Vd by reading. In reading, the transfer destination processing unit 30 shifts the reading order Swd as necessary. This transition can be arbitrarily determined by the transfer destination processing unit 30 according to the processing contents of the transfer destination processing unit 30. Further, Syncd described later is used as a signal for starting the transition of the reading order Swd.

  The writing order storage device 41 changes the value Ixs in the order of 1 → 2 → 3 → 4 → 5 → 6 → 7 → 8 in the machine cycle, and starts again from 1 in the next machine cycle and repeats this. . Then, the value Ixs at that time is written in the place of the write order Sws given by the transfer source processing unit 10. FIG. 2 shows the contents Tw (i) of the arbitration first buffer device 41 when the writing order Sws changes as 1 → 5 → 2 → 6 → 3 → 7 → 4 → 8. For example, data with the fifth arrangement order i indicates that the writing order is second. Thus, the order of writing the data D (i) to be written at the address i of the buffer device 20 is stored in Tw (i) of the writing order storage device 41.

  The reading order storage device 42 changes the value Ixd in the order of 1 → 2 → 3 → 4 → 5 → 6 → 7 → 8 following the machine cycle, and starts again from 1 in the next machine cycle and repeats this. When Syd to be described later is 1, the value Ixd at that time is written in the position of the reading order Swd given by the transfer destination processing unit 30. In FIG. 3, the reading order storage after the writing order Sws is changed from 1 → 5 → 2 → 6 → 3 → 7 → 4 → 8 and the contents Tw (i) of the writing order storage device 41 is created. The contents Tr (i) of the device 42 are shown. The content Tr (i) of the reading order storage device 42 indicates that, for example, the data having the fifth arrangement order i has the fifth writing order. As described above, the order of reading the data D (i) read from the address i of the buffer device 20 is stored in Tr (i) of the reading order storage device 42.

  In the arithmetic unit 50, from the contents Tw (i) of the writing order storage device 41 and the contents Tr (i) of the reading order storage device 42, f and g are expressed by the equations (1) and (2) shown in FIG. A calculation unit 51 for calculating values and registers 52 to 27 for storing variables DET, Lf, Postd, Syd, Syd1, Syncd and the like created based on these f and g are provided.

  The value of Postd in the register 54 is decreased by 1 for each reading from the initial value n = 8 (write cycle to D (i)). Repeat this step. However, when Postd = 8, if Syd = 0 and Syd1 = 1, the value of Postd is increased by “(f−Lf) −1” after the next reading. When f = Lf, the value decreases by one. Thereafter, it is decremented by 1 for each reading.

  The Lf value of the register 53 is updated with the value of f after the next reading when Postd = 8, Syd = 0, and Syd1 = 1. In other cases, the previous value is held (see equation (3) in FIG. 4).

  The initial value of the Syd value in the register 55 is 1, and every time Postd = 1, the value shifts alternately between 1 and 0 (see equation (4) in FIG. 4).

  The value of Synd1 in the register 56 is updated with the value of Synd after the next reading (see equation (5) in FIG. 4).

  The value of Syncd in the register 57 is 1 only when Postd = 1 (see equation (6) in FIG. 4).

  The value of DET in the register 52 is Syd = 0, Syd1 = 1, and Postd = 8, and when (f−g) <8, it becomes 0 (= normal display) after the next reading. When Syd = 0, Syd1 = 1, and Postd = 8 and (f−g) ≧ 8, 1 (= abnormal display) is set after the next reading. Otherwise, the value is the previous value (see equation (7) in FIG. 4).

  As described above, when Syncd = 1, when the transfer destination processing unit 30 starts reading in the next cycle, as shown in FIG. 5, the reading is started from the next cycle in which the writing of the write data W6 is completed. Reading of the data R1 is started. When reading is started with Syncd = 1, Postd = 8, Syd = 0, and Syd1 = 1.

  As an example according to the above, a time chart of the data transfer apparatus of the present embodiment is shown in FIG. Here, the writing order Sws of the group of data by the transfer source processing unit 10 is 1 → 5 → 2 → 6 → 3 → 7 → 4 → 8, and the reading order of the group of data by the transfer destination processing unit 30 is as follows. The case where Swd is 1 → 2 → 3 → 4 → 5 → 6 → 7 → 8 will be described. The values of Vs and Vd are 1 digit in the first cycle (8 cycles), 2 in the second cycle, 2 in the second cycle, 3 in the second digit, etc. A numerical value indicating the number of cycles is added to the second digit. If Vd appears in the order of 1 → 2 → 3 → 4 → 5 → 6 → 7 → 8, 11 → 12 → 13 → 14 → 15 → 16 → 17 → 18, etc., a group of data is transferred correctly. It shows that it was broken.

At time t = 8 after the first eight cycles are completed, the content Tw (i) of the writing order storage device 41 and the content Tr (i) of the reading order storage device 42 are as shown in FIG. . For this reason, from the equation (1)
f = 1 + max (Tw (i) −Tr (i))
= 1 + (7-4)
= 4
It becomes. Lf = 0.

  Therefore, after this, the value of Postd is adjusted (8 → 11 → 10 → 9 →... → 2 → 1). As a result, by following Syncd = 1 generated at time t = 19, reading of the group of data succeeds after the next time t = 20, and the group of data written by the transfer source processing unit 10 (above As described above, the transfer destination processing unit 30 can take out the first digit of the value of Vs so that it can be easily understood without losing the arrangement. FIG. 5 shows this simply. Read data R1 is read out in the fourth cycle from writing of the write data W1.

  Further, the writing order Sws is changed from time t = 40 (3 → 1 → 2 → 4 → 6 → 5 → 8 → 7). For this reason, the reading order of the group of data to be read is temporarily lost. However, after time t = 51, the group of data Vd is read again in the normal reading order (1 → 2 → 3 → 4 → 5 → 6 → 7 → 8).

  By the way, depending on the order Sws for writing a group of data by the transfer source processing unit 10 and the order Swd for reading a group of data by the transfer destination processing unit 30, there is a case where the loss during reading and writing cannot be avoided by the adjustment of Postd. In order to detect this, DET is calculated using the values of f and g.

  That is, in the next cycle after Syncd = 1, when Postd = 8, Syd = 0, and Syd1 = 1, “f−g” is calculated by the equation (7), and the value is 8 or more. Calculate whether or not. When the result is DET = 1, even if the transfer destination processing unit 30 starts reading from the next cycle according to Syncd = 1, the reading order of the group of data written by the transfer source processing unit 10 is lost. It is. In this way, by referring to the value of DET, it is possible to detect a missing combination (order) of a group of data.

  FIG. 7 shows a condition of an operation example in which the writing order Sws of a group of data by the transfer source processing unit 10 is changed and the combination (order) of reading is made incorrect, and whether normal or abnormal is detected by the DET value. A chart is shown. From time t = 1 to 31, the same operation as shown in the time chart of FIG. 6 is performed.

  From time t = 32, the write order Sws of the group of data by the transfer source processing unit 10 is changed to 3 → 7 → 4 → 2 → 6 → 8 → 5 → 1. As a result, at time t = 34, the value read is Vd = 47 instead of the expected value Vd = 37, and thereafter, the group of data read is different from the expected order of writing. End up. This results in a change in g and f between time t = 35 and time t = 40.

  At time t = 44, Postd is adjusted to reflect f = 8 and Lf = 4 (8 → 11 → 10 →... → 2 → 1), but Syncd = 1 at time t = 55. By just doing so, the read group of data does not recover the mismatch with the expected order. At this time, due to f and g at time t = 44, DET = 1 at time t = 45, indicating that an expected order mismatch has occurred.

  Further, at time t = 56, the write order Sws of the group of data by the transfer source processing unit 10 is changed again to 3 → 1 → 4 → 2 → 6 → 5 → 6 → 7. As a result, after time t = 67, the group of data written from the transfer source processing unit 10 is recovered so that it can be read correctly by the transfer destination processing unit 30 in the expected order.

  Prior to time t = 67, Postd adjustment (8 → 2 → 1) is performed at f = 3 and Lf = 8 at time t = 64, but at the same time, DET at time t = 65 by f and g. Return to = 0. In this way, if the value of DET is evaluated by Syncd = 0 generated at time t = 65 and DET = 0, it can be detected from this reading that a group of data can be transmitted in the correct order.

10: transfer source processing unit 20: buffer device 30: transfer destination processing unit 41: writing order storage device, 42: reading order storage device 50: arithmetic device, 51: arithmetic circuit, 52-27: register

Jonathan Barrett, Programming High-Performance Applications on Cell BE Processor, Part 6: Smart Buffer Management with DMA Transfer, [Search February 4, 2009], Internet <URL: https://www.ibm. com / developerworks / jp / linux / library / pa-linuxps3-6 / ＞ Satojo et al., “PDS Optimization Cycle: Cell BE Program Optimization Strategy Proposal”, “Cell Speed Challenge 2008 Free Task Division” June 2008, [Search February 4, 2009], Internet <http: //www.hpcc.jp/sacsis/2008/cell/outputs/doc/jiyu_2.pdf>

Claims (8)

Write a group of data consisting of a plurality of components transferred from the transfer source processing unit to the buffer device in the order of writing in the same or different writing order as the order of arrangement of the group of data. In a data transfer method of reading a group of data in the same or different reading order as the arrangement order and transferring the data to a transfer destination processing unit,
The number of cycles f is determined according to the maximum value of the difference obtained by subtracting the read order from the write order in each arrangement order of the group of data,
Starting the reading of the group of data from the buffer device after elapse of the number of cycles f from the start of writing of the group of data to the buffer device;
A data transfer method characterized by the above. The data transfer method according to claim 1,
The cycle number f is:
f = 1 + max (Tw (i) −Tr (i))
Here, i = 1, 2,..., N (n is the number of components of a group of data)
Tw (i) is the order of writing the components in the i-th order
Tr (i) is obtained by the reading order of the constituent elements in the i-th arrangement order. The data transfer method according to claim 1 or 2,
A data transfer method characterized by displaying an abnormality in reading when a predetermined condition is satisfied in the next cycle after the start of reading. The data transfer method according to claim 3,
The predetermined condition for displaying the reading abnormality is:
(F−g) ≧ n
Where n is the number of components of a group of data
f = 1 + max (Tw (i) −Tr (i))
g = 1 + min (Tw (i) -Tr (i))
i = 1, 2,..., n
Tw (i) is the writing order of the components in the i-th order
Tr (i) is a data transfer method characterized in that it is a reading order of components in the i-th arrangement order. Write a group of data consisting of a plurality of components transferred from the transfer source processing unit to the buffer device in the order of writing in the same or different writing order as the order of arrangement of the group of data. In a data transfer apparatus that reads a group of data in the same or different reading order as the arrangement order and transfers the data to a transfer destination processing unit.
A writing order storage device for storing the writing order of the group of data; and a reading order storage device for storing the reading order of the group of data;
Obtaining the number of cycles f according to the maximum value of the difference obtained by subtracting the reading order of the reading order storage device from the writing order of the writing order storage device in each arrangement order;
Starting the reading of the group of data from the buffer device after elapse of the number of cycles f from the start of writing of the group of data to the buffer device;
A data transfer device. The data transfer device according to claim 5, wherein
The cycle number f is:
f = 1 + max (Tw (i) −Tr (i))
Here, i = 1, 2,..., N (n is the number of components of a group of data)
Tw (i) is the writing order of the components in the i-th order of the writing order storage device. Tr (i) is obtained by the reading order of the components in the i-th order of the reading order storage device. A data transfer device. In the data transfer device according to claim 5 or 6,
A data transfer apparatus that displays a read error when a predetermined condition is satisfied in a cycle next to the start of the read. The data transfer device according to claim 7, wherein
The predetermined condition for displaying the reading abnormality is:
(F−g) ≧ n
Where n is the number of components of the data in one group f = 1 + max (Tw (i) −Tr (i))
g = 1 + min (Tw (i) -Tr (i))
i = 1, 2,..., n
Tw (i) is the writing order of the i-th order component of the writing order storage device Tr (i) is the reading order of the i-th order component of the reading order storage device A data transfer device.

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