TW201725515A - Data transmission system and method for operating a data transmission system - Google Patents

Abstract

A method for operating a data transmission system includes a parallel serial master controller receiving a read signal, a write signal, a slave select signal, a plurality of data control signals and a plurality of address signals in parallel, transmitting the read signal, the write signal, the slave select signal and the plurality of data control signals serially through a data control output terminal, and transmitting the plurality of address signals serially through an address output terminal. The parallel serial slave controller receives the read signal, the write signal, the slave select signal and the plurality of data control signals serially through a data control input terminal, and receiving the plurality of address signals serially through an address input terminal. The parallel serial slave controller outputs the read signal, the write signal, the slave select signal, the plurality of data control signals, and the plurality of address signals in parallel.

Description

Data transmission system and method for operating data transmission system

The present invention relates to a data transmission system, and more particularly to a data transmission system capable of reducing transmission lines.

FIG. 1 is a schematic diagram showing the connection between the host terminal H1 and the slave terminal S1 of the prior art. In the first figure, the host terminal H1 and the slave terminal S1 are respectively disposed on different circuit boards, so that they are connected to each other through the backplane B1, that is, the signal required between the host terminal H1 and the backplane B1. The line includes M address signal lines LA ₀ to LA _M-1 , N data signal lines LD ₀ to LD _N-1 and P control signal lines LC ₀ to LC _P-1 , M, N and P are greater than 1 Positive integer. The signal line corresponding to the backplane B1 and the slave terminal S1 also needs to be corresponding to the M address lines LA' ₀ to LA' _M-1 and the N data signal lines LD' ₀ to LD' _N-1 and P The strip controls the signal line LC' ₀ to LC' _P-1 . The address signal lines LA ₀ to LA _M-1 and LA' ₀ to LA' _M-1 can transmit the internal address of the host terminal H1 to read or write to the slave terminal S1, and the data signal lines LD ₀ to LD _{N -1} and LD' ₀ to LD' _N-1 can transfer the data written by the host H1 to the slave S1 or the data read by the host H1 from the slave S1. In addition, since there may be more than one slave connected to the host H1, the host H1 also informs the slave S1 whether it is hosted through the control signal lines LC ₀ to LC _P-1 and LC' ₀ to LC' _P-1 . End H1 selection, and what should be done.

The backplane B1 is configured to couple the address signal lines LA ₀ to LA _M-1 and LA' ₀ to LA' _M-1 , the data signal lines LD ₀ to LD _{N-1 ,} and LD ' ₀ to LD ' _{N- 1} , and control the signal line LC ₀ to LC _P-1 and LC' ₀ to the end of LC' _P-1 , so when the values of N, M and P are large, the space required for the backplane B1 will also follow The increase and the winding on the backing plate B1 will be more complicated. Moreover, if the host terminal H1 needs to be connected to a plurality of slave terminals, the wiring on the backplane B1 is multiplied along with the number of slave terminals, which makes the design of the backplane B1 difficult, and also increases the wire required for the connection.

An embodiment of the present invention provides a data transmission system including a parallel sequence host controller and a parallel sequence slave controller. The parallel sequence host controller includes a plurality of data input and output terminals, a plurality of address input terminals, a slave select input terminal, a read signal input terminal, a write signal input terminal, a clock output terminal, an address output terminal, and a data control output. Terminal, clock input and data control input. The plurality of data input and output terminals can receive the plurality of first data control signals in parallel, and output the plurality of second data control signals in parallel. A plurality of address inputs can receive a plurality of address signals in parallel. The slave select input can receive the slave select signal, the read signal input can receive the read signal, and the write signal input can receive the write signal. The clock output terminal can output a first clock signal, and the address output terminal can sequentially output a plurality of address signals. The data control output can sequentially output the read signal, the write signal, the slave selection signal and the plurality of first data control signals. The clock input can receive the second clock signal. The data control input can sequentially receive a plurality of second data control signals. The parallel sequence slave controller includes a plurality of data input and output terminals, a plurality of address output terminals, a slave select output terminal, a read signal output terminal, a write signal output terminal, a clock input terminal, an address input terminal, and a data control input. End, clock output and data control output. The plurality of data input and output terminals can output a plurality of first data control signals in parallel, and receive a plurality of second data control signals in parallel. A plurality of address outputs can output a plurality of address signals in parallel. The slave select output can output a slave select signal, the read signal output can output a read signal, and the write signal output can output a write signal. The clock input can receive the first clock signal. The address input can receive a plurality of address signals in sequence. The data control input terminal can sequentially receive the read signal, the write signal, the slave selection signal and the plurality of first data control signals. The clock output can output a second clock signal. The data control output can serially output a plurality of second data control signals.

Another embodiment of the present invention provides a method of operating a data transfer system. The data transmission system comprises a parallel sequence host controller and a parallel sequence slave controller. The method for operating the data transmission system comprises the parallel sequence host controller receiving the read signal, the write signal, the slave selection signal, and the plurality of first data control signals in parallel. And a plurality of address signals, the parallel sequence host controller sequentially outputs the read signal, the write signal, the slave selection signal, and the plurality of first data control signals via the first data control output of the parallel sequence host controller, and the parallel sequence The host controller sequentially outputs a plurality of address signals via the address output end of the parallel sequence host controller, and the parallel sequence host controller sequentially outputs the read signal, the write signal, the slave selection signal, and the plurality of first data controls. When the signal and the plurality of address signals are received, the parallel sequence host controller outputs the first clock signal, and the parallel sequence slave controller sequentially receives the read signal, the write signal, and the slave selection via the data control input terminal of the parallel sequence slave controller. Signal and a plurality of first data control signals, parallel sequences from The controller receives the first clock signal, and the parallel sequence slave controller sequentially receives the plurality of address signals via the address input terminals of the parallel sequence slave controller, and the parallel sequence slave controller outputs the read signals and the write signals in parallel. Subordinate selection signal, multiple first data control signals and multiple address signals.

FIG. 2 is a schematic diagram showing the operation of the data transmission system 100 according to an embodiment of the present invention. In FIG. 2, data transmission and control signals can be transmitted between the host terminal H1 and the slave terminal S1 through the data transmission system 100. The data transmission system 100 includes a parallel sequence master controller 110 and a parallel sequence slave controller 120. Although in FIG. 2, the parallel sequence host controller 110 and the host terminal H1 are separately disposed, in some embodiments of the present invention, the parallel sequence host controller 110 may also be disposed in the host terminal H1, and/or The parallel sequence slave controller 120 can be disposed in the slave terminal S1.

The parallel sequence host controller 110 includes a plurality of data input and output terminals HDIO ₀ to HDIO _N-1 , a plurality of address input terminals HAI ₀ to HAI _M-1 , a slave select input terminal HCSI, a read signal input terminal HRDI, and a write Signal input terminal HWRI, clock output terminal HCLKO, address output terminal HAO, data control output terminal HDCO, clock input terminal HCLKI and data control input terminal HDCI.

The data input/output terminals HDIO ₀ to HDIO _N-1 can receive or output the data control signals in a parallel manner, and the address inputs HAI ₀ to HAI _M-1 can receive the addresses transmitted from the host terminal H1 in parallel. data. The slave select input HCSI can receive the slave select signal CS, the read signal input HRDI can be used to receive the read signal RD, and the write signal input terminal HWRI can receive the write signal WR. The slave terminal S1 can recognize whether the host terminal H1 is to operate on the slave terminal S1 according to the state of the slave select signal CS, and can identify the operation to be performed by the host terminal H1 according to the read signal RD and the write signal WR.

For example, when the host terminal H1 wants to operate the slave terminal S1, the host terminal H1 can maintain the slave select signal CS transmitted to the slave terminal S1 at the logic 1 potential, and if the host terminal H1 wants to the non-slave terminal S1. When the other slaves operate, the host terminal H1 can maintain the slave select signal CS transmitted to the slave terminal S1 at a logic 0 potential, so the slave terminal S1 can determine whether it needs to be based on the host side according to the logic potential of the slave select signal CS. H1's instructions to perform the corresponding operations. In addition, when the host terminal H1 wants to perform a write operation on the slave terminal S1, the host terminal H1 can maintain the write signal WR transmitted to the slave terminal S1 at a logic 1 potential, and maintain the read signal RD at a logic 0. When the host terminal H1 wants to perform a read operation on the slave terminal S1, the host terminal H1 can maintain the write signal WR transmitted to the slave terminal S1 at a logic 0 potential, and maintain the read signal RD at logic. 0 potential. Of course, in other embodiments of the present invention, the logic potentials of the slave select signal CS, the write signal WR, and the read signal RD may also have other correspondences with the operational state represented by the system according to the needs of the system.

In the embodiment of FIG. 2, the write signal WR is logic 1, indicating that the host terminal H1 is to perform a write operation on the slave terminal S1. The host controller 110 may be parallel to the end of the sequence HDIO ₀ HDIO to receive the first control data signal coming from the host terminal H1 is parallel to the _N-1 D1 ₀ through _N-1 Dl data input and output via the address input via HAI ₀ The HAI _M-1 receives the address signals A ₀ to A _M-1 transmitted from the host terminal H1 in parallel, where N and M are positive integers. At this time, the address signals A ₀ to A _{M-1 are} the addresses of the register of the slave terminal H1 to be written by the host terminal H1, and the first data control signals D1 ₀ to D1 _N-1 are corresponding to the writes. The data of the register of the address signals A ₀ to A _M-1 . j

In some embodiments of the present invention, the parallel sequence host controller 110 may latch the address signals A ₀ to A _M-1 and the first data control signals D1 ₀ to D1 _N-1 and store them in a parallel sequence. The register of the host controller 110 ensures that the received data is properly saved. After the parallel sequence host controller 110 stores the address signals A ₀ to A _M-1 and the first data control signals D1 ₀ to D1 _{N-1 in the} register, the parallel sequence host controller 110 can also transmit through the transmission line L. When the signal RDY is completed to the host terminal H1, when the host terminal H1 senses the potential change of the completion signal RDY on the transmission line L, it can be determined that the parallel sequence host controller 110 has actually received the address signals A ₀ to A _{M- 1} and the first data control signal D1 ₀ to D1 _N-1 , at this time, the host terminal H1 can also change the potential of the completion signal RDY through the transmission line L again, so that the parallel sequence host controller 110 knows that the write operation has been completed. In this way, the host terminal H1 can stop outputting the address signals A ₀ to A _M-1 and the first data control signals D1 ₀ to D1 _N-1 , and can stop controlling the slave select signals CS, read signals RD and write. Enter the signal WR potential to reduce the burden on the host H1.

After receiving the slave select signal CS, the write signal WR, the read signal RD, the first data control signals D1 ₀ to D1 _N-1, and the address signals A ₀ to A _M-1 , the parallel sequence host controller 110 may The received data is transmitted in a serial manner to reduce the number of wires required to transfer the data. In FIG. 2, the parallel sequence host controller 110 sequentially outputs the address signals A ₀ to A _M-1 through the address output terminal HAO, and sequentially outputs the first data control signal D1 ₀ through the data control output terminal HDCO to D1 _N-1 , write signal WR, read signal RD and slave select signal CS. In addition, in order for the slave terminal S1 to clearly determine the data of each bit, the parallel sequence host controller 110 also outputs the first clock signal CLK1 through the clock output terminal HCLKO, so the parallel sequence slave controller 120 can be in the first When the positive or negative edge of the clock signal CLK1 is detected, the data of each bit is judged.

In the embodiment of FIG. 2, the data control output terminal HDCO sequentially outputs the first data control signals D1 ₀ to D1 _N-1 , the write signal WR, the read signal RD, and the slave selection signal CS, but in the present invention In other embodiments, the data control output HDCO can also output the first data control signals D1 ₀ to D1 _N-1 , the write signal WR, the read signal RD, and the slave select signal CS in different orders. In addition, in the embodiment of FIG. 2, M is greater than (N+3), so the first data control signals D1 ₀ to D1 _N-1 , the write signal WR, the read signal RD, and the HDCO are outputted at the data control output terminal HDCO. After the slave select signal CS, the address output terminal HAO will continuously output the address signal, and the parallel sequence host controller 110 can control the output through the data before the output address signal A _{M-1 is} completed through the address output terminal HAO. The terminal HDCO outputs a potential of logic 0 to be synchronized with the output of the address output HAO. However, in other embodiments of the present invention, M may also be smaller than (N+3). After the address output terminal HAO completes the output address signal A _M-1 , the parallel sequence host controller 110 may also pass the address. The signal A _M-1 outputs a potential of logic 0, so that the data control output terminal HDCO outputs the first data control signals D1 ₀ to D1 _N-1 , the write signal WR, the read signal RD and the slave selection signal CS.

The parallel sequence slave controller 120 may include N data input and output terminals SDIO ₀ to SDIO _N-1 , M address output terminals SAO ₀ to SAO _M-1 , slave select output terminal SCSO, read signal output terminal SRDO, write Incoming signal output terminal SWRO, clock input terminal SCLKI, address input terminal SAI, data control input terminal SDCI, clock output terminal SCLKO and data control output terminal SDCO.

In FIG. 2, the clock input terminal SCLKI, the address input terminal SAI, the data control input terminal SDCI, the clock output terminal SCLKO, and the data control output terminal SDCO of the parallel sequence slave controller 120 are respectively coupled to the parallel sequence host. The clock output terminal HCLKO of the controller 110, the address output terminal HAO, the data control output terminal HDCO, the clock input terminal HCLKI, and the data control input terminal HDCI. Therefore, in the embodiment of FIG. 2, the parallel sequence slave controller 120 can receive the first clock signal CLK1 through the clock input terminal SCLKI, and can receive the address signals A ₀ to A _M- through the address input terminal SAI. ₁ and receiving the first data control signals D1 ₀ to D1 _N-1 , the write signal WR, the read signal RD and the slave selection signal CS through the data control input terminal SDCI.

In some embodiments of the present invention, the parallel sequence slave controller 120 may include a buffer register for storing the received data signal and the address signal, and after the data signal and the address signal are collected, parallel The method outputs the received data signal to the slave S1. For example, in the process of the parallel sequence slave controller 120 receiving the first data control signals D1 ₀ to D1 _N-1 , the write signal WR, the read signal RD, and the slave selection signal CS through the data control input terminal SDCI. The parallel sequence slave controller 120 can temporarily store the received signals to the buffer register, and sort and classify according to the received signals, and then, after receiving all the signals, pass through the data input/output terminal SDIO ₀ to The SDIO _N-1 outputs the first data control signals D1 ₀ to D1 _N-1 in parallel, and outputs the slave select signal CS through the slave select output terminal SCSO, and outputs the read signal RD through the read signal output terminal SRDO, and transmits the read signal through the write signal. The output terminal SWRO outputs a write signal WR. Similarly, in the process that the parallel sequence slave controller 120 receives the address signals A ₀ to A _M-1 serially through the address input terminal SAI, the parallel sequence slave controller 120 can temporarily store the received address data. After the buffer register is received, the address signals A ₀ to A _M-1 are output in parallel through the address output terminals SAO ₀ to SAO _M-1 after receiving all the address data.

In addition, the parallel sequence slave controller 120 can also receive the read signal RD, the write signal WR, the slave select signal CS, the first data control signals D1 ₀ to D1 _N-1, and the address signals A ₀ to A _M in sequence. _{After -1} , the slave control acknowledgement signal ACK is output through the data control output SDCO to inform the parallel sequence host controller 110 and/or the host terminal H1 that the data has been received.

In FIG. 2, the data input/output terminals SDIO ₀ to SDIO _{N-1 of the} parallel sequence slave controller 120, the address output terminals SAO ₀ to SAO _M-1 , the slave select output terminal SCSO, the read signal output terminal SRDO and The write signal output terminal SWRO is coupled to the slave terminal S1. Therefore, the slave terminal S1 can receive through the data input and output terminals SDIO ₀ to SDIO _N-1 , the address output terminals SAO ₀ to SAO _M-1 , the slave select output terminal SCSO, the read signal output terminal SRDO and the write signal output terminal SWRO. The first data control signals D1 ₀ to D1 _N-1 , the address signals A ₀ to A _M-1 , the slave selection signals CS, the read signals RD, and the write signals WR. The slave S1 processes and applies the received first data control signals D1 ₀ to D1 _N-1 and the address signals A ₀ to A _M-1 according to the slave selection signal CS, the read signal RD and the write signal WR. In this embodiment, the slave S1 writes the first data control signals D1 ₀ to D1 _N-1 into the storage device corresponding to the address signals A ₀ to A _M-1 to complete the host H1 pair. Write operation of slave S1.

In this way, the host end H1 and the slave end S1 can perform a write operation in a sequence manner through the data transmission system 100 without changing the hardware design, thereby achieving the effect of saving external wiring.

Moreover, in the embodiment of FIG. 2, the parallel sequence host controller 110 further includes a first exclusive OR gate (XOR gate) and a second exclusive OR gate 114. The first mutex or gate 112 has a first end, a second end, and an output end. The first end of the first mutex or gate 112 is coupled to the data control output HDCO of the parallel sequence host controller 110, and the first mutual The output of the repeller or gate 112 is coupled to the second end of the first mutex or gate 112. The second mutex or gate 114 has a first end, a second end, and an output end, and the first end of the second mutex or gate 114 is coupled to the address output terminal HAO of the parallel sequence host controller 110, and the second mutual The output of the repeller or gate 114 is coupled to the second end of the second mutex or gate 114.

In addition, the parallel sequence slave controller 120 can also include a third mutex or gate 122 and a fourth mutex or gate 124. The third mutex or gate 122 has a first end, a second end, and an output end, and the first end of the third mutex or gate 122 is coupled to the data control input terminal SDCI of the parallel sequence slave controller 120, and the third mutual The output of the repeller or gate 122 is coupled to the second terminal of the third mutex or gate 122. The fourth mutex or gate 124 has a first end, a second end, and an output end, and the first end of the fourth mutex or gate 124 is coupled to the address input terminal SAI of the parallel sequence slave controller 120, and the fourth mutual The output of the repeller or gate 124 is coupled to the second terminal of the fourth mutex or gate 124.

The parallel sequence host controller 110 can separately output the bit data of each output through the first mutex or gate 112 and the second mutex or gate 114 when sequentially outputting the data control signal and the address signal. Or logical processing is performed to output a first check signal P1 at an output of the first mutex or gate 112 and a second check signal P2 at an output of the second mutex or gate 114. For example, if the first data control signal D1 ₀ to D1 _N-1 is an octet data control signal 10110011, the write signal WR is 1, the read signal RD is 0, and the slave select signal CS is 1, parallel. The sequence host controller 110 sequentially outputs the first data control signals D1 ₀ to D1 _N-1 , the write signal WR, the read signal RD, and the slave selection signal CS through the data control output terminal HDCO. The first check signal P1 outputted by the output of the gate 112 is the first data control signal D1 ₀ to D1 _N-1 , the write signal WR, the read signal RD and the subordinate selection signal CS. The result of the exclusive OR logic operation, that is, 1 (according to the characteristics of the exclusive OR logic, even the parallel sequence host controller 110 outputs the first data control signals D1 ₀ to D1 _N-1 , the write signal WR, the read signal RD, and After the slave select signal CS, the potential of the logic 0 is continuously output, and the state of the first check signal P1 is still not changed. Similarly, if the address signals A ₀ to A _M-1 are 16-bit data 1111000011110000, the parallel sequence host controller 110 outputs the address signals A ₀ to A _M-1 through the address output terminal HAO. The second check signal P2 outputted by the output of a mutex or gate 112 is zero.

In the case where the data transmission is normal, the signal output by the parallel sequence host controller 110 and the signal received by the parallel sequence slave controller 120 should be the same, in which case the third of the parallel sequence slave controllers 120 is mutually exclusive or The third check signal P3 outputted from the output of the gate 122 should be the same as the first check signal P1 outputted by the first mutex of the parallel sequence host controller 110 or the output of the gate 112, and the row sequence slave controller 120 The fourth check signal P4 outputted by the output of the fourth mutex or gate 124 should also be the same as the second check signal P2 outputted by the second mutex of the parallel sequence host controller 110 or the output of the gate 114. If the first check signal P1 is different from the third check signal P3 and/or the second check signal P2 is different from the fourth check signal P4, it means that the data transmission by the data transmission system 100 is incorrect.

In the embodiment of FIG. 2, the parallel sequence host controller 110 can sequentially output the first data control signals D1 ₀ to D1 _N-1 , the write signal WR, the read signal RD, and the slaves through the data control output HDCO. After the signal CS is selected, the first inspection signal P1 is successively outputted, and the second inspection signal P2 is successively outputted after the address signal A ₀ to A _{M-1 is} output through the address output terminal HAO. The parallel sequence slave controller 120 can receive the first data control signals D1 ₀ to D1 _N-1 , the write signal WR, the read signal RD, and the slave select signal CS after serially receiving the data control input terminal SDCI. The third check signal P3 outputted by the mutex OR gate 122 is compared with the first check signal P1, and after receiving the address signals A ₀ to A _M-1 serially through the address input terminal SAI, the fourth mutually exclusive or The fourth inspection signal P4 output by the gate 124 is compared with the second inspection signal P2. In this way, the parallel sequence slave controller 120 or the slave terminal S1 can determine whether the data transmission is incorrect according to the first check signal P1, the second check signal P2, the third check signal P3, and the fourth check signal P4, and can notify Host H1 to retransmit the data.

In addition, in other embodiments of the present invention, the parallel sequence host controller 110 can also directly transmit the first check signal P1 and the second check signal P2 to the host end H1 through other transmission lines, and the parallel sequence slave controller 120 also The third check signal P3 and the fourth check signal P4 can be directly transmitted back to the host end H1 through other transmission lines. At this time, the host end H1 can be based on the first check signal P1, the second check signal P2, and the third check signal. P3 and the fourth check signal P4 determine whether it is necessary to retransmit the data. Of course, in the case where the data transmission environment is relatively stable, the data transmission system 100 can also eliminate the process of comparing the check signals, and even omit the first mutual exclusion or gate 112, the second mutual exclusion or gate 114, and the third mutual exclusion or Gate 122 and fourth mutex or gate 124 are used to reduce the space and components required by data transmission system 100.

FIG. 3 is a schematic diagram showing the operation of the data transmission system 100 according to another embodiment of the present invention. In the embodiment of FIG. 3, the write signal WR is at a potential of logic 0, and the read signal RD is at a potential of logic 1, indicating that the host terminal H1 is to perform a read operation on the slave terminal S1. Thus parallel host controller 110 via the serial address input terminal HAI ₀ to HAI _M-1 parallel to the receiving host terminal H1 transmitted address signal A ₀ through A _M-1, at this time the address signals A ₀ to A _{M -1 is} the address of the scratchpad of the slave terminal S1 to be read by the host terminal H1.

After receiving the slave select signal CS, the write signal WR, the read signal RD, and the address signals A ₀ to A _M-1 , the parallel sequence host controller 110 can transmit the received data to the parallel sequence in a sequence. Slave controller 120.

In FIG. 3, the parallel sequence slave controller 120 receives the first clock signal CLK1 through the clock input terminal SCLKI, and sequentially receives the address signals A ₀ to A _M-1 through the address input terminal SAI. The data control input terminal SDCI sequentially receives the write signal WR, the read signal RD and the slave select signal CS. In this embodiment, the host terminal H1 performs a read operation on the slave terminal S1, so the host terminal H1 does not need to transmit a data control signal, or transmits a data control signal in which each bit is a logic 0.

The parallel sequence slave controller 120 can pass the address output terminals SAO ₀ to SAO _M- after receiving the address signals A ₀ to A _M-1 , the write signal WR , the read signal RD and the slave select signal CS . ₁ outputting the address signals A ₀ to A _M-1 in parallel, outputting the slave selection signal CS through the slave select output terminal SCSO, outputting the read signal RD through the read signal output terminal SRDO, and outputting the write signal through the write signal output terminal SWRO The signal is WR.

When the slave S1 receives the slave select signal CS, the read signal RD and the write signal WR, the slave S1 can determine the operation to be performed by the host H1, so the slave S1 will correspondingly correspond to the address. The data stored in the storage devices of the signals A ₀ to A _M-1 are transmitted to the host terminal H1 through the data transmission system 100, that is, the slave terminal S1 can transmit the corresponding second data control signals D2 ₀ to D2 _N-1 through the parallel sequence. The data input/output terminals SDIO ₀ to SDIO _{N-1 of the} slave controller 120 are transferred to the parallel sequence slave controller 120.

When the parallel sequence slave controller 120 receives the second data control signals D2 ₀ to D2 _N-1 , the parallel sequence slave controller 120 may latch the second data control signals D2 ₀ to D2 _N-1. The parallel sequence slave controller 120 is buffered to ensure that the received data is properly saved.

The parallel sequence slave controller 120 sequentially outputs the second data control signals D2 ₀ to D2 _N-1 to the parallel sequence host controller 110 through the data control output SDCO, and in order to enable the parallel sequence host controller 110 to correctly interpret the The second data control signal D2 ₀ to D2 _N-1 each bit signal, the parallel sequence slave controller 120 also outputs the second clock signal CLK2 through the clock output terminal SCLKO, so the parallel sequence host controller 110 can be The positive/negative edge of the second clock signal CLK2 determines the data of each bit.

The parallel sequence host controller 110 receives the second clock signal CLK2 through the clock input terminal HCLKI, and receives the second data control signals D2 ₀ to D2 _N-1 through the data control input terminal HDCI. In some embodiments of the present invention, the parallel sequence host controller 110 may also include a buffer register, and the parallel sequence host controller 110 receives the second data control signals D2 ₀ to D2 _N-1 through the data control input terminal HDCI. During the process, the parallel sequence host controller 110 can temporarily store the received signals to the buffer register, sort and classify according to the received signals, and then input the data after receiving all the signals. The output terminals HDIO ₀ to HDIO _N-1 output the second data control signals D2 ₀ to D2 _{N-1 in} parallel.

In some embodiments of the present invention, the parallel sequence host controller 110 outputs the second data control signals D2 ₀ to D2 _N-1 in parallel through the data input/output terminals HDIO ₀ to HDIO _N-1. The completion signal RDY can also be transmitted through the transmission line to the host terminal H1. When the host terminal H1 senses the potential change of the completion signal RDY on the transmission line (for example, the potential of the logic 0 becomes the logic 1 potential), the slave can be determined. The terminal S1 has completed the read operation, and the second data control signals D2 ₀ to D2 _N-1 can be read from the parallel sequence host controller 110. At this time, the host terminal H1 can access the second data control signals D2 ₀ to D2 _N-1 and change the potential of the read signal RD from the potential of the logic 1 to the potential of the logic 0. When the parallel sequence host controller 110 senses that the potential of the read signal RD has become a logic 0 potential, it indicates that the host end H1 has completed accessing the second data control signals D2 ₀ to D2 _N-1 , and the parallel sequence The host controller 110 can stop outputting the second data control signals D2 ₀ to D2 _N-1 , and then the host terminal H1 can change the potential of the slave selection signal CS from the potential of the logic 1 to the potential of the logic 0, and the parallel sequence host control The device 110 can correspondingly change the potential of the completion signal RDY (for example, the potential of the logic 1 to the logic 0), so that the reading operation of the slave terminal S1 by the host terminal H1 is completed.

In this way, in the embodiment of FIG. 3, the host end H1 and the slave end S1 can be read in a serial manner through the data transmission system 100 without changing the hardware design, thereby saving external wiring. efficacy.

In addition, in the embodiments of FIG. 2 and FIG. 3, the parallel sequence host controller 110 and the parallel sequence slave controller 120 may be directly coupled to each other. However, in some embodiments of the present invention, the host terminal H1 is And the parallel sequence host controller 110 may be different from the slave S1 and the parallel sequence slave controller 120. In order to increase the flexibility of use, the user can conveniently insert and remove the slave S1, the parallel sequence host. The controller 110 and the parallel sequence slave controllers 120 can also be connected through a wired backplane.

FIG. 4 is a schematic diagram of a data transmission system 200 according to an embodiment of the present invention. The data transmission system 200 operates in the same principle as the data transmission system 100. The difference is that the data transmission system 200 further includes a connection backplane 230, and the parallel sequence host controller 110 and the parallel sequence slave controller 120 are connected through the connection backplane. 230 to connect.

The connection backplane 230 can include a first clock input terminal BCLKI1, an address input terminal BAI, a first data control input terminal BDCI1, a second clock output terminal BCLKO2, a second data control output terminal BDCO2, and a first clock output. The terminal BCLKO1, the address output terminal BAO, the first data control output terminal BDCO1, the second clock input terminal BCLKI2, and the second data control input terminal BDCI2.

The first clock input terminal BCLKI1 is coupled to the clock output terminal HCLKO of the parallel sequence host controller 110 and can receive the first clock signal CLK1. The address input terminal BAI is coupled to the address output terminal HAO of the parallel sequence host controller 110, and can sequentially receive the address signals A ₀ to A _M-1 . The first data control input terminal BDCI1 is coupled to the data control output terminal HDCO of the parallel sequence host controller 110, and can sequentially receive the read signal RD, the write signal WR, the slave select signal CS, and the first data control signal D1 ₀ To D1 _N-1 . The second clock output terminal BCLKO2 is coupled to the clock input terminal HCLKI of the parallel sequence host controller 110, and can output the second clock signal CLK2. The second data control output BDCO2 is coupled to the data control input terminal HDCI of the parallel sequence host controller 110, and can sequentially output the second data control signals D2 ₀ to D2 _N-1 . The first clock output terminal BCLKO1 is coupled to the clock input terminal SCLKI of the parallel sequence slave controller 120, and can output the first clock signal CLK1. The address output terminal BAO is coupled to the address input terminal SAI of the parallel sequence slave controller 120, and can sequentially output the address signals A ₀ to A _M-1 . The first data control output terminal BDCO1 is coupled to the data control input terminal SDCI of the parallel sequence slave controller 120, and can sequentially output the read signal RD, the write signal WR, the slave select signal CS, and the first data control signal D1 ₀ To D1 _N-1 . The second clock input terminal BCKLI2 is coupled to the clock output terminal SCLKO of the parallel sequence slave controller 120 and can receive the second clock signal CLK2. The second data control input terminal BDCI2 is coupled to the data control output terminal SDCO of the parallel sequence slave controller 120, and can sequentially receive the second data control signals D2 ₀ to D2 _N-1 .

In this way, the data transmission system 200 can reduce the wire required for transmitting signals through the parallel sequence host controller 110 and the parallel sequence slave controller 120 without changing the hardware settings of the host terminal H1 and the slave terminal S1. The parallel sequence host controller 110 and the parallel sequence slave controllers 120 can also be connected through the connection backplane 230 to facilitate the user to plug and unplug the slave S1 to the connection backplane 230. In addition, in some embodiments of the present invention, when the host end H1 wants to control a plurality of slave terminals, the connection backplane 230 can also be expanded according to the number of parallel sequence host controllers and parallel sequence slave controllers to be connected. The number of each of the above signal output inputs increases the flexibility of the data transmission system 200 in use.

FIG. 5 is a diagram of a method 300 of operating a data transmission system 100 or 200 according to an embodiment of the present invention. The method 300 includes steps S310 to S380.

S310: The parallel sequence host controller 110 receives the read signal RD, the write signal WR, the slave select signal CS, the first data control signals D1 ₀ to D1 _N-1, and the address signals A ₀ to A _{M-1 in} parallel;

S320: The parallel sequence host controller 110 sequentially outputs the read signal RD, the write signal WR, the slave select signal CS, and the first data control signals D1 ₀ to D1 via the first data control output HDCO of the parallel sequence host controller 110. _N-1 ;

S330: The parallel sequence host controller 110 sequentially outputs the address signals A ₀ to A _M-1 via the address output terminal HAO of the parallel sequence host controller 110;

S340: When the parallel sequence host controller 110 sequentially outputs the read signal RD, the write signal WR, the slave select signal CS, the first data control signals D1 ₀ to D1 _N-1, and the address signals A ₀ to A _M-1 The parallel sequence host controller 110 outputs the first clock signal CLK1;

S350: The parallel sequence slave controller 120 sequentially receives the read signal RD, the write signal WR, the slave select signal CS, and the first data control signals D1 ₀ to D1 _N- via the data control input terminal SDCI of the parallel sequence slave controller 120. ₁ ;

S360: The parallel sequence slave controller 120 receives the first clock signal CLK1;

S370: The parallel sequence slave controller 120 sequentially receives the address signals A ₀ to A _M-1 via the address input SAI of the parallel sequence slave controller 120; and

S380: The parallel sequence slave controller 120 outputs the read signal RD, the write signal WR, the slave select signal CS, the first data control signals D1 ₀ to D1 _N-1, and the address signals A ₀ to A _{M-1 in} parallel.

In some embodiments of the present invention, the parallel sequence slave controller 120 sequentially receives the read signal RD, the write signal WR, the slave select signal CS, the first data control signal D1 ₀ to D1 _N-1, and the address signal. After A ₀ to A _M-1 , the parallel sequence slave controller 120 may also output a slave acknowledge signal ACK to inform the parallel sequence host controller 110 and/or the host terminal H1 that the receipt of the data has been completed.

According to the method 300, the data transmission system 100 or 200 can write the data required to be written by the host terminal H1 to the slave terminal S1 and the address to be written, that is, the first data control signals D1 ₀ to D1. _N-1 and the address signals A ₀ to A _{M-1 are} transmitted between the host terminal H1 and the slave terminal S1 through the parallel sequence master controller 110 and the parallel sequence slave controller 120 to reduce the wiring required for data transmission. .

When the host terminal H1 is to perform a read operation on the slave terminal S1, the address signals A ₀ to A _M-1 described in the method 300 may be the address of the slave terminal S1 to be read by the host terminal H1. The first data control signals D1 ₀ to D1 _N-1 in the method 300 can be replaced by arbitrary data signals, for example, N logic 0 signals. The parallel sequence slave controller 120 outputs the read signal RD, the write signal WR, the slave select signal CS, the first data control signals D1 ₀ to D1 _N-1, and the address signals A ₀ to A _M-1 in parallel. The slave S1 outputs the second data control signals D2 ₀ to D2 _N-1 corresponding to the address signals A ₀ to A _M-1 according to the received signals, and the parallel sequence slave controllers 120 receive the second in parallel. after D2 ₀ through D2 _N-1, to the control output terminal sequence SDCO output signal via a second data of the second data control information to the control signal D2 ₀ D2 _N-1 to the host controller 110 sequences in parallel. When the parallel sequence slave controller 120 sequentially outputs the second data control signals D2 ₀ to D2 _N-1 , the parallel sequence slave controller 120 also synchronously outputs the second clock signal CLK2 to the parallel sequence host controller 110, so that The parallel sequence host controller 110 can correctly interpret the received second data control signals D2 ₀ to D2 _N-1 . In this way, the data transmission system 100 or 200 can also complete the reading operation of the slave terminal S1 by the host terminal H1 through the method 300 and the above steps.

In addition, FIG. 6 is a flowchart S410 to S450 of operating the data transmission system 100 or 200 according to another embodiment of the present invention. When it is determined whether the data transmission of the data transmission system 100 or 200 is incorrect, the method 300 may further include Steps S410 to S450.

S410: After the parallel sequence host controller 110 sequentially outputs the read signal RD, the write signal WR, the slave select signal CS, and the first data control signals D1 ₀ to D1 _N-1 , the parallel sequence host controller 110 reads according to The signal RD, the write signal WR, the slave select signal CS, and the first data control signals D1 ₀ to D1 _N-1 output the first check signal P1;

S420: After the parallel sequence host controller 110 sequentially outputs the address signals A ₀ to A _M-1 , the parallel sequence host controller 110 outputs the second check signal P2 according to the address signals A ₀ to A _M-1 ;

S430: After the parallel sequence slave controller 120 sequentially receives the read signal RD, the write signal WR, the slave select signal CS, and the first data control signals D1 ₀ to D1 _N-1 , the parallel sequence slave controller 120 reads according to The signal RD, the write signal WR, the slave select signal CS, and the first data control signals D1 ₀ to D1 _N-1 output a third check signal P3;

S440: After the parallel sequence slave controller 120 sequentially receives the address signals A ₀ to A _M-1 , the parallel sequence slave controller 120 outputs the fourth check signal P4 according to the address signals A ₀ to A _M-1 ;

S450: When the first inspection signal P1 is different from the third inspection signal P3 and/or the second inspection signal P2 is different from the fourth inspection signal P4, it is determined that the transmission data of the data transmission system 100 (or 200) is incorrect.

In summary, the data transmission system and the method for operating the data transmission system according to the embodiments of the present invention can pass the parallel sequence host controller and the parallel sequence slave controller, so that the original host end and the slave end are output in parallel. The signal is output in a sequential manner, thereby reducing the number of wires required to transmit signals and reducing the complexity of wiring or routing. In addition, the data transmission system and the operation data transmission system proposed by the embodiments of the present invention can also determine whether the transmitted data is incorrect by transmitting a check signal, thereby increasing the transmission between the host and the slave. Trustworthiness. The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should be within the scope of the present invention.

H1‧‧‧Host side
S1‧‧‧ slave
B1‧‧‧ Backboard
LA ₀ to LA _M-1 , LA' ₀ to LA' _M-1 ‧‧‧ address line
LD ₀ to LD _N-1 , LD' ₀ to LD' _N-1 ‧‧‧ data signal line
LC ₀ to LC _P-1 , LC' ₀ to LC' _P-1 ‧‧‧Control signal line
100, 200‧‧‧ data transmission system
110‧‧‧Parallel sequence host controller
120‧‧‧Parallel Sequence Slave Controller
112‧‧‧First mutual exclusion or gate
114‧‧‧Second exclusive or gate
122‧‧‧ third mutual exclusion or gate
124‧‧‧ fourth mutual exclusion or gate
HDIO ₀ , HDIO _N-1 , SDIO ₀ , SDIO _N-1 ‧‧‧ Data input and output
HAI ₀ , HAI _M-1 , SAI, BAI‧‧‧ address inputs
HCSI‧‧‧ slave selection input
HRDI‧‧‧ read signal input
HWRI‧‧‧Write signal input
HCLKI, SCLKI‧‧‧ clock input
HDCI, SDCI‧‧‧ data control input
HCLKO, SCLKO‧‧‧ clock output
HAO, SAO ₀ , SAO _M-1 , BAO‧‧‧ address output
HDCO‧‧‧first data control output
SDCO‧‧‧Second data control output
SCSO‧‧‧Subordinate selection output
SRDO‧‧‧ read signal output
SWRO‧‧‧ write signal output
L‧‧‧ transmission line
RDY‧‧‧Complete signal
ACK‧‧‧ confirmation signal
D1 ₀ , D1 _N-1 ‧‧‧First data control signal
D20, D2 _N-1 ‧‧‧Second data control signal
A ₀ , A _M-1 ‧‧‧ address signal
CS‧‧‧Subordinate selection signal
RD‧‧‧ read signal
WR‧‧‧ write signal
CLK1‧‧‧ first clock signal
CLK2‧‧‧ second clock signal
P1‧‧‧ first inspection signal
P2‧‧‧Second inspection signal
P3‧‧‧ third inspection signal
P4‧‧‧ Fourth inspection signal
230‧‧‧Connected backplane
BCLKO2‧‧‧second clock output
BCLKI1‧‧‧ first clock input
BDCI1‧‧‧First data control input
BCLKI2‧‧‧second clock input
BDCI2‧‧‧Second data control input
BCLKO1‧‧‧ first clock output
BDCO1‧‧‧First data control output
BDCO2‧‧‧Second data control output
300‧‧‧ method
S310 to S380, S410 to S450‧‧‧ steps

Figure 1 is a schematic diagram of the connection between the host side and the slave side of the prior art. FIG. 2 is a schematic diagram showing the operation of a data transmission system according to an embodiment of the present invention. Figure 3 is a schematic diagram of another operation of the data transmission system of Figure 2. Figure 4 is a schematic diagram showing the operation of a data transmission system according to another embodiment of the present invention. FIG. 5 is a flow chart showing a method of operating the data transmission system of FIG. 2 according to an embodiment of the present invention. Figure 6 is a diagram showing the steps of operating the data transmission system of Figure 2 in accordance with an embodiment of the present invention.

H1‧‧‧Host side

S1‧‧‧ slave

100‧‧‧ data transmission system

110‧‧‧Parallel sequence host controller

120‧‧‧Parallel Sequence Slave Controller

112‧‧‧First mutual exclusion or gate

114‧‧‧Second exclusive or gate

122‧‧‧ third mutual exclusion or gate

124‧‧‧ fourth mutual exclusion or gate

HDIO ₀ , HDIO _N-1 , SDIO ₀ , SDIO _N-1 ‧‧‧ Data input and output

HAI ₀ , HAI _M-1 , SAI‧‧‧ address inputs

HCSI‧‧‧ slave selection input

HRDI‧‧‧ read signal input

HWRI‧‧‧Write signal input

HCLKI, SCLKI‧‧‧ clock input

HDCI, SDCI‧‧‧ data control input

HCLKO, SCLKO‧‧‧ clock output

HAO, SAO ₀ , SAO _M-1 ‧‧‧ address output

HDCO‧‧‧first data control output

SDCO‧‧‧Second data control output

SCSO‧‧‧Subordinate selection output

SRDO‧‧‧ read signal output

SWRO‧‧‧ write signal output

L‧‧‧ transmission line

RDY‧‧‧Complete signal

ACK‧‧‧ confirmation signal

D1 ₀ , D1 _N-1 ‧‧‧First data control signal

A ₀ , A _M-1 ‧‧‧ address signal

CS‧‧‧Subordinate selection signal

RD‧‧‧ read signal

WR‧‧‧ write signal

CLK1‧‧‧ first clock signal

P1‧‧‧ first inspection signal

P2‧‧‧Second inspection signal

P3‧‧‧ third inspection signal

P4‧‧‧ Fourth inspection signal

Claims (10)

A data transmission system comprising: a parallel sequence host controller, comprising: a plurality of data input and output ends for receiving a plurality of first data control signals in parallel, and outputting a plurality of second data control signals in parallel; a address input end for receiving a plurality of address data in parallel; a slave select input terminal for receiving a slave select signal; a read signal input terminal for receiving a read signal; and a write signal input The terminal is configured to receive a write signal; a clock output terminal for outputting a first clock signal; a bit address output terminal for sequentially outputting the address signals; and a data control output terminal for Serially outputting the read signal, the write signal, the slave select signal, and the first data control signals; a clock input terminal for receiving a second clock signal; and a data control input terminal for Serially receiving a plurality of second data control signals; and a parallel sequence slave controller, comprising: a plurality of data input and output ends for outputting the first ones in parallel Data control signals, and receiving the second data control signals in parallel; a plurality of address output terminals for outputting the address data in parallel; a slave select output terminal for outputting the slave select signal; a signal output terminal for outputting the read signal; a write signal output terminal for outputting the write signal; a clock input terminal for receiving the first clock signal; and an address input terminal for Receiving the address signals in sequence; a data control input terminal for sequentially receiving the read signal, the write signal, the slave select signal, and the first data control signals; And outputting the second clock signal; and a data control output for sequentially outputting the second data control signals. The data transmission system of claim 1, further comprising: a connection backplane, comprising: a first clock input end coupled to the parallel sequence host controller for receiving the first clock signal; An address input end coupled to the parallel sequence host controller for receiving the address signals in sequence; a first data control input coupled to the parallel sequence host controller for serially receiving The read signal, the write signal, the slave select signal, and the first data control signals; a second clock output coupled to the parallel sequence host controller for outputting the second clock signal a second data control output coupled to the parallel sequence host controller for sequentially outputting the second data control signals; a first clock output coupled to the parallel sequence slave controller For outputting the first clock signal; a bit address output end coupled to the parallel sequence slave controller for sequentially outputting the address signals; a first data control output coupled to the parallel Sequence slave control The controller is configured to sequentially output the read signal, the write signal, the slave select signal, and the first data control signals; a second clock input end coupled to the parallel sequence slave controller Receiving the second clock signal; and a second data control input coupled to the parallel sequence slave controller for sequentially receiving the second data control signals. The data transmission system of claim 1 or 2, wherein: the parallel sequence host controller further comprises: a first exclusive OR gate (XOR gate) having a first end coupled to the parallel The data control output of the serial host controller, a second end, and an output end coupled to the second end of the first mutex or gate; and a second exclusive OR gate (XOR) a gate having a first end coupled to the address output of the parallel sequence host controller, a second end, and an output coupled to the second end of the second mutex or gate; The parallel sequence slave controller further includes: a third exclusive OR gate (XOR gate) having a first end coupled to the data control input of the parallel sequence slave controller, and a second end And an output end coupled to the second end of the third mutex or gate; and a fourth exclusive OR gate (XOR gate) having a first end coupled to the parallel sequence slave The address input end of the controller, a second end, and an output end coupled to the fourth mutually exclusive or Of the second end. The data transmission system of claim 3, wherein: the parallel sequence host controller is further configured to sequentially output the read signal, the write signal, the slave select signal, and the first data control signals. Outputting a first check signal of the output of the output of the first mutex or gate, and outputting the address signals of the second mutex or gate after the serial output of the address signals, and outputting a second check of the output of the output of the second mutex or gate And the parallel sequence slave controller is further configured to output the third mutex or gate after receiving the read signal, the write signal, the slave select signal, and the first data control signals in sequence The output end outputs a third check signal, and after receiving the address signals in sequence, outputting a fourth check signal outputted by the output of the fourth mutex or gate. The data transmission system of claim 1 or 2, wherein: the parallel sequence slave controller is further configured to serially receive the read signal, the write signal, the slave select signal, and the first data control signals. And after the address signals, a subordinate confirmation signal is output. A method of operating a data transmission system, the data transmission system comprising a parallel sequence host controller and a parallel sequence slave controller, the method comprising: the parallel sequence host controller receiving a read signal, a write signal, a slave select signal, a plurality of first data control signals and a plurality of address signals; the parallel sequence host controller serially outputs the read signal and the write via one of the parallel data sequence controller first data control outputs The input signal, the slave selection signal, and the first data control signals; the parallel sequence host controller sequentially outputs the address signals via one of the parallel sequence host controller address outputs; when the parallel sequence host controls When the read signal, the write signal, the slave select signal, the first data control signal, and the address signals are sequentially output, the parallel sequence host controller outputs a first clock signal; the parallel The sequence slave controller serially receives the read signal via one of the parallel sequence slave controller data control inputs The write signal, the slave select signal, and the first data control signals; the parallel sequence slave controller receives the first clock signal; the parallel sequence slave controller transmits an address of the slave controller via the parallel sequence The input terminal serially receives the address signals; and the parallel sequence slave controller outputs the read signal, the write signal, the slave select signal, the first data control signals, and the address signals in parallel. The method of claim 6, further comprising: after the parallel sequence host controller sequentially outputs the read signal, the write signal, the slave select signal, and the first data control signals, the parallel sequence host The controller outputs a first check signal according to the read signal, the write signal, the slave select signal, and the first data control signals; after the parallel sequence host controller sequentially outputs the address signals, The parallel sequence host controller outputs a second check signal according to the address signals; receiving, in the parallel sequence slave controller, the read signal, the write signal, the slave select signal, and the first data control signals. The parallel sequence slave controller outputs a third check signal according to the read signal, the write signal, the slave select signal, and the first data control signals; and sequentially receiving the slave sequence controller in the parallel sequence After the address signals, the parallel sequence slave controller outputs a fourth check signal according to the address signals. The method of claim 7, further comprising: determining that the data transmission system is different when the first inspection signal is different from the third inspection signal and/or the second inspection signal is different from the fourth inspection signal The transmission data is incorrect. The method of claim 6, further comprising: sequentially receiving, at the parallel sequence slave controller, the read signal, the write signal, the slave select signal, the first data control signals, and the address signals Thereafter, the parallel sequence slave controller outputs a slave acknowledge signal. The method of claim 6, further comprising: after the parallel sequence slave controller outputs the read signal, the write signal, the slave select signal, and the address signals in parallel, the parallel sequence slave controller Receiving a plurality of second data control signals in parallel; after the parallel sequence slave controllers receive the second data control signals in parallel, the parallel sequence slave controller sequentially outputs the plurality of the second data control outputs Two data control signals to the parallel sequence host controller; and when the parallel sequence slave controller sequentially outputs a plurality of second data control signals, the parallel sequence slave controller outputs a second clock signal to the parallel sequence host Controller.