CN104752423B - 一种半导体器件及其制造方法和电子装置 - Google Patents

一种半导体器件及其制造方法和电子装置 Download PDF

Info

Publication number
CN104752423B
CN104752423B CN201310754079.2A CN201310754079A CN104752423B CN 104752423 B CN104752423 B CN 104752423B CN 201310754079 A CN201310754079 A CN 201310754079A CN 104752423 B CN104752423 B CN 104752423B
Authority
CN
China
Prior art keywords
doping type
type
well region
doping
semiconductor devices
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201310754079.2A
Other languages
English (en)
Other versions
CN104752423A (zh
Inventor
汪铭
马千成
程勇
滕丽华
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Semiconductor Manufacturing International Shanghai Corp
Original Assignee
Semiconductor Manufacturing International Shanghai Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Semiconductor Manufacturing International Shanghai Corp filed Critical Semiconductor Manufacturing International Shanghai Corp
Priority to CN201310754079.2A priority Critical patent/CN104752423B/zh
Priority to US14/532,624 priority patent/US9824928B2/en
Publication of CN104752423A publication Critical patent/CN104752423A/zh
Priority to US15/806,191 priority patent/US10211106B2/en
Application granted granted Critical
Publication of CN104752423B publication Critical patent/CN104752423B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823418—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/07—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common
    • H01L27/0705—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common comprising components of the field effect type
    • H01L27/0727—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common comprising components of the field effect type in combination with diodes, or capacitors or resistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0638—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for preventing surface leakage due to surface inversion layer, e.g. with channel stopper
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66659—Lateral single gate silicon transistors with asymmetry in the channel direction, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
    • H01L29/7835—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
    • H01L29/0653—Dielectric regions, e.g. SiO2 regions, air gaps adjoining the input or output region of a field-effect device, e.g. the source or drain region
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/47—Schottky barrier electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
    • H01L29/6609—Diodes
    • H01L29/66143—Schottky diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • H01L29/872—Schottky diodes

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)

Abstract

本发明提供一种半导体器件及其制造方法和电子装置，涉及半导体技术领域。本发明的半导体器件，包括第一掺杂类型的半导体衬底以及位于所述半导体衬底内的LDMOS晶体管和二极管，其中所述半导体衬底与位于其内的第二掺杂类型的阱区形成PN结，所述二极管与所述PN结反向串联。本发明的半导体器件，通过在LDMOS晶体管的漏极一侧形成与半导体衬底和位于其内的第二掺杂类型的阱区构成的PN结反向串联的二极管，可以避免当LDMOS晶体管应用于电感负载模式时产生流向半导体衬底的大电流，提高了半导体器件的性能。本发明的半导体器件的制造方法，用于制造上述半导体器件，制得的器件同样具有上述优点。本发明的电子装置，包括上述半导体器件，同样具有上述优点。

Description

一种半导体器件及其制造方法和电子装置
技术领域
本发明涉及半导体技术领域，具体而言涉及一种半导体器件及其制造方法和电子装置。
背景技术
在半导体技术领域中，LDMOS(Laterally Diffused Metal OxideSemiconductor；横向扩散金属氧化物半导体)晶体管由于在热稳定性、频率稳定性、耐久性等方面的优异性能而在CDMA、WCDMA、数字地面电视等领域得到了广泛的应用。
现有技术中的一种横向扩散金属氧化物半导体晶体管（即LDMOS晶体管）的结构如图1所示。该LDMOS晶体管包括P型衬底100以及形成于P型衬底100内的P阱1001和N阱1002，P阱1001内包括N型源极101，N阱1002内包括N型漏极102。此外，该LDMOS晶体管还包括位于P型衬底上的栅极103以及位于P阱1001内的P型体电极104，如图1所示。并且，该LDMOS晶体管还可以包括位于P型衬底内的浅沟槽隔离（STI）1003。上述LDMOS晶体管结构中源极101、栅极103以及体电极104等各组成部分在实际结构中均为围绕漏极102的环状结构，即，各组成部分在平面结构中均为环状结构。
在现有技术中，LDMOS晶体管的漏极102经常作为N阱1002的拾取区（pickup）通过欧姆接触连接至电感负载，使得LDMOS晶体管应用于电感负载模式（inductive loadmode）。当电感负载引起的负脉冲（negative pulse）被施加在漏极102处时，P型衬底100与N阱1002构成的PN结将正向导通，因而会导致产生流向P型衬底100的大电流。
因此，为了解决上述问题，有必要提出一种新的半导体器件结构及其制造方法。
发明内容
针对现有技术的不足，本发明提供一种半导体器件及其制造方法和电子装置，以避免当LDMOS晶体管应用于电感负载模式时产生流向P型衬底的大电流。
本发明实施例一提供一种半导体器件，包括第一掺杂类型的半导体衬底以及位于所述半导体衬底内的LDMOS晶体管和二极管，其中，所述半导体衬底与位于其内的第二掺杂类型的阱区形成PN结，所述二极管与所述PN结反向串联；其中，所述第一掺杂类型与所述第二掺杂类型分别为P型掺杂和N型掺杂，或者，所述第一掺杂类型与所述第二掺杂类型分别为N型掺杂和P型掺杂。
可选地，所述二极管包括位于所述第二掺杂类型的阱区上方的金属硅化物与所述第二掺杂类型的阱区。
可选地，所述二极管还包括位于所述第二掺杂类型的阱区内且位于其上部的第一掺杂类型的离子注入区。进一步地，所述第一掺杂类型的离子注入区为P+离子注入区。
可选地，所述二极管为肖特基二极管。
可选地，所述LDMOS晶体管包括位于所述半导体衬底内的第一掺杂类型的阱区和所述第二掺杂类型的阱区，还包括位于所述第一掺杂类型的阱区内的源极以及位于所述半导体衬底上的栅极，其中，所述第二掺杂类型的阱区作为所述LDMOS晶体管的漂移区。
可选地，所述源极为第二掺杂类型的源极。进一步地，所述源极为N型源极。
可选地，所述LDMOS晶体管还包括位于所述第一掺杂类型的阱区内的体电极。
可选地，所述体电极为第一掺杂类型的体电极。进一步的，所述体电极为P型体电极。
可选地，所述LDMOS晶体管还包括位于所述第一掺杂类型的阱区和/或所述第二掺杂类型的阱区内的浅沟槽隔离。
本发明实施例二提供一种半导体器件的制造方法，所述方法包括：
步骤S101：提供半导体衬底，在所述半导体衬底内形成第一掺杂类型的阱区和第二掺杂类型的阱区，并在所述半导体衬底上形成LDMOS晶体管的栅极，其中所述第二掺杂类型的阱区作为所述LDMOS晶体管的漂移区；
步骤S102：进行第二掺杂类型的离子注入以在所述第一掺杂类型的阱区内形成所述LDMOS晶体管的源极，进行第一掺杂类型的离子注入以在所述第二掺杂类型的阱区内形成第一掺杂类型的离子注入区；
步骤S103：在所述第二掺杂类型的阱区的上方形成金属硅化物，其中所述金属硅化物与所述第二掺杂类型的阱区构成二极管；
其中，所述第一掺杂类型与所述第二掺杂类型分别为P型掺杂和N型掺杂，或者，所述第一掺杂类型与所述第二掺杂类型分别为N型掺杂和P型掺杂。
可选地，所述半导体衬底为第一掺杂类型的衬底，所述半导体衬底与所述第二掺杂类型的阱区形成的PN结与所述二极管为反向串联。
可选地，在所述步骤S102中，在所述进行第一掺杂类型的离子注入以在所述第二掺杂类型的阱区内形成第一掺杂类型的离子注入区的过程中，在所述第一掺杂类型的阱区内形成所述LDMOS晶体管的体电极。
可选地，在所述步骤S101中，还包括在所述半导体衬底内形成浅沟槽隔离的步骤。
可选地，在所述步骤S103之后还包括形成层间介电层和接触孔的步骤。
本发明实施例三提供一种电子装置，其特征在于，包括如上所述的半导体器件。
本发明的半导体器件，通过在LDMOS晶体管的漏极一侧形成与半导体衬底和位于其内的第二掺杂类型的阱区构成的PN结反向串联的二极管，可以避免当LDMOS晶体管应用于电感负载模式时产生流向半导体衬底的大电流，提高了半导体器件的性能。本发明的半导体器件的制造方法，用于制造上述半导体器件，制得的半导体器件同样具有上述优点。本发明的电子装置，包括上述半导体器件，同样具有上述优点。
附图说明
本发明的下列附图在此作为本发明的一部分用于理解本发明。附图中示出了本发明的实施例及其描述，用来解释本发明的原理。
附图中：
图1为现有技术中的一种LDMOS晶体管的结构的示意图；
图2为本发明实施例一的半导体器件的结构的示意性剖视图；
图3A至图3C为本发明实施例二的半导体器件的制造方法的关键步骤形成的图形示意性剖视图；
图4为本发明实施例二的半导体器件的制造方法的一种示意性流程图；
图5为本发明实施例三的电子装置的示意图。
具体实施方式
在下文的描述中，给出了大量具体的细节以便提供对本发明更为彻底的理解。然而，对于本领域技术人员而言显而易见的是，本发明可以无需一个或多个这些细节而得以实施。在其他的例子中，为了避免与本发明发生混淆，对于本领域公知的一些技术特征未进行描述。
应当理解的是，本发明能够以不同形式实施，而不应当解释为局限于这里提出的实施例。相反地，提供这些实施例将使公开彻底和完全，并且将本发明的范围完全地传递给本领域技术人员。在附图中，为了清楚，层和区的尺寸以及相对尺寸可能被夸大。自始至终相同附图标记表示相同的元件。
应当明白，当元件或层被称为“在...上”、“与...相邻”、“连接到”或“耦合到”其它元件或层时，其可以直接地在其它元件或层上、与之相邻、连接或耦合到其它元件或层，或者可以存在居间的元件或层。相反，当元件被称为“直接在...上”、“与...直接相邻”、“直接连接到”或“直接耦合到”其它元件或层时，则不存在居间的元件或层。应当明白，尽管可使用术语第一、第二、第三等描述各种元件、部件、区、层和/或部分，这些元件、部件、区、层和/或部分不应当被这些术语限制。这些术语仅仅用来区分一个元件、部件、区、层或部分与另一个元件、部件、区、层或部分。因此，在不脱离本发明教导之下，下面讨论的第一元件、部件、区、层或部分可表示为第二元件、部件、区、层或部分。
空间关系术语例如“在...下”、“在...下面”、“下面的”、“在...之下”、“在...之上”、“上面的”等，在这里可为了方便描述而被使用从而描述图中所示的一个元件或特征与其它元件或特征的关系。应当明白，除了图中所示的取向以外，空间关系术语意图还包括使用和操作中的器件的不同取向。例如，如果附图中的器件翻转，然后，描述为“在其它元件下面”或“在其之下”或“在其下”元件或特征将取向为在其它元件或特征“上”。因此，示例性术语“在...下面”和“在...下”可包括上和下两个取向。器件可以另外地取向(旋转90度或其它取向)并且在此使用的空间描述语相应地被解释。
在此使用的术语的目的仅在于描述具体实施例并且不作为本发明的限制。在此使用时，单数形式的“一”、“一个”和“所述/该”也意图包括复数形式，除非上下文清楚指出另外的方式。还应明白术语“组成”和/或“包括”，当在该说明书中使用时，确定所述特征、整数、步骤、操作、元件和/或部件的存在，但不排除一个或更多其它的特征、整数、步骤、操作、元件、部件和/或组的存在或添加。在此使用时，术语“和/或”包括相关所列项目的任何及所有组合。
这里参考作为本发明的理想实施例(和中间结构)的示意图的横截面图来描述发明的实施例。这样，可以预期由于例如制造技术和/或容差导致的从所示形状的变化。因此，本发明的实施例不应当局限于在此所示的区的特定形状，而是包括由于例如制造导致的形状偏差。例如，显示为矩形的注入区在其边缘通常具有圆的或弯曲特征和/或注入浓度梯度，而不是从注入区到非注入区的二元改变。同样，通过注入形成的埋藏区可导致该埋藏区和注入进行时所经过的表面之间的区中的一些注入。因此，图中显示的区实质上是示意性的，它们的形状并不意图显示器件的区的实际形状且并不意图限定本发明的范围。
为了彻底理解本发明，将在下列的描述中提出详细的步骤以及详细的结构，以便阐释本发明的技术方案。本发明的较佳实施例详细描述如下，然而除了这些详细描述外，本发明还可以具有其他实施方式。
实施例一
本发明实施例提供一种半导体器件，如图2所示，包括P型衬底100以及位于该P型衬底内的LDMOS晶体管结构，该LDMOS晶体管包括位于该P型衬底100内的P阱1001和N阱1002，其中，P阱1001内形成有N型源极101，N阱1002作为该器件的漂移区（drift area）。此外，该LDMOS晶体管还包括位于P型衬底上的栅极103以及位于P阱1001内的P型体电极104，如图2所示。
在本实施例中，该半导体器件还包括位于N阱1002上方的金属硅化物105，如图2所示。其中，该金属硅化物105与N阱1002（即，漂移区）构成肖特基二极管（Schottky diode）。形成该肖特基二极管的工艺，可以参考现有技术中的各种工艺，在此并不进行限定。显然，该肖特基二极管，与P型衬底100和N阱1002构成的PN结是反向串联的。也就是说，在本实施例的半导体器件中，在LDMOS晶体管的漏极102一侧集成有肖特基二极管，该肖特基二极管与P型衬底100和N阱1002构成的PN结形成反向串联的结构。
由于金属硅化物105与N阱1002构成肖特基二极管，在LDMOS晶体管的漏极102通过金属硅化物105被连接至电感负载的情况下，可以阻止大电流流向P型衬底100。具体地，当电感负载引起的负电压被施加在漏极102处时，金属硅化物105与N阱1002构成的肖特基二极管处于反向截止状态（reverse blocking mode），可以阻止产生的大电流流向P型衬底100。而当在漏极102施加正电压时，金属硅化物105与N阱1002构成的肖特基二极管处于正向导通状态（forward conduction mode），正电压将被传导到LDMOS晶体管的漂移区（driftarea）以保持LDMOS晶体管处于正常工作状态。
在本实施例中，还可以在N阱1002内形成位于其上部的P+离子注入区1021，如图2所示。其中，该P+离子注入区1021可以与金属硅化物105相接触，也可以不接触。由于P+离子注入区1021的存在，可以减小肖特基二极管处于反向截止状态时发生的泄漏，进一步阻止产生的大电流流向P型衬底100。
在本实施例中，如图2所示，金属硅化物105的顶端作为LDMOS晶体管的漏极（漏区）102，用于连接至电感或其他器件。与现有技术中漂移区采用拾取区（pickup）通过欧姆接触连接至负载的方式不同，本实施例的半导体器件由于在漏极一侧具有肖特基二极管，在LDMOS晶体管连接负载时，通过该肖特基二极管实现连接。
在本实施例中，LDMOS晶体管结构中源极101、栅极103以及体电极104等组成部分在实际结构中均为环状结构，具体可以参考现有技术中的LDMOS晶体管的结构，在此不再赘述。
在本实施例中，如图2所示，该LDMOS晶体管还包括位于所述P阱1001和/或所述N阱1002内的浅沟槽隔离（STI）1003，该浅沟槽隔离可以隔离P阱或N阱内的不同组件，提高LDMOS晶体管的性能。此外，本发明实施例的半导体器件，除LDMOS晶体管与肖特基二极管之外，还可以包括其他各种器件（例如普通MOS器件、CMOS器件、电感、电阻、电容等），在此并不进行限定。并且，本实施例的肖特基二极管也可以用普通二极管代替，而采用肖特基二极管则可以具有更好的性能。
需要解释的是，在本实施例中，P型衬底100可以为独立的衬底，也可为其他衬底（例如SOI衬底）的一部分。并且，本实施例的P型衬底100，也可以采用其他类型的衬底（例如N型衬底，此时各阱区以及其他组件也需要相应对掺杂类型进行调整），在此并不进行限定。此外，在本实施例中，N型源极101、N型漏极102中的“N型”是指掺杂有N型离子，P型体电极104中的“P型”是指掺杂有P型离子。本实施例的源极101、漏极102以及体电极104并不以此为限，还可以为其他各种合适的类型。
本发明实施例的半导体器件，通过在LDMOS晶体管的漏极一侧形成与P型衬底和N阱构成的PN结反向串联的二极管（优选为肖特基二极管），可以避免当LDMOS晶体管应用于电感负载模式时产生流向P型衬底的大电流，提高了半导体器件的性能。
本领域的技术人员可以理解，当P型衬底100变换为N型衬底、阱区（包括P阱1001和N阱1002）以及源极、体电极等的掺杂类型相应作调整的情况下，该半导体器件由于在LDMOS晶体管的漏极一侧形成与半导体衬底和位于其内的阱区构成的PN结反向串联的二极管，也可以避免当LDMOS晶体管应用于电感负载模式时产生流向半导体衬底的大电流，提高了半导体器件的性能。
实施例二
下面，参照图3A至图3C和图4来描述本发明实施例提出的半导体器件的制造方法。其中，图3A至图3C为本发明实施例二的半导体器件的制造方法的关键步骤形成的图形示意性剖视图；图4为本发明实施例二的半导体器件的制造方法的一种示意性流程图。
本发明实施例的半导体器件的制造方法，用于制造上述实施例一所述的半导体器件。如图4所示，本实施例的半导体器件的制造方法，包括如下步骤：
步骤A1：提供P型衬底100，在该P型衬底100内形成P阱1001和N阱1002，并在该P型衬底100上形成LDMOS晶体管的栅极103，如图3A所示。
其中，还可以形成位于P型衬底100内的浅沟槽隔离（STI）1003，如图3A所示。当然，在本步骤中，还可以形成其他组件，在此并不进行限定。
步骤A2：进行N+离子注入以在P阱1001内形成源极101，进行P+离子注入以在N阱1002内形成P+离子注入区1021，如图3B所示。
其中，“进行N+离子注入以在P阱1001内形成源极101”的步骤，与“进行P+离子注入以在N阱1002内形成P+离子注入区1021”的步骤的先后顺序可以互换。在进行P+离子注入以在N阱1002内形成P+离子注入区1021的步骤中，还可以同时在P阱1001形成LDMOS晶体管的P型体电极104，如图3B所示。
在本实施例中，N阱1002作为LDMOS晶体管的漂移区。
步骤A3：在N阱1002的上方形成金属硅化物105，所述金属硅化物105与所述N阱1002构成二极管，如图3C所示。
至此，完成了本发明实施例的半导体器件的制造方法的关键步骤的介绍。除了上述步骤之外，本发明的制造方法还可以包括其他步骤，例如，在步骤A3之后，还可以包括形成层间介电层（ILD）和接触孔（CT）的步骤。这些步骤均可以通过现有技术中的各种工艺来实现，此处不再赘述。
本发明实施例的半导体器件的制造方法，用于制造上述实施例一所述的半导体器件，该半导体器件在LDMOS晶体管的漏极一侧形成有与P型衬底和N阱构成的PN结反向串联的二极管，因而可以避免当LDMOS晶体管应用于电感负载模式时产生流向P型衬底的大电流，提高了半导体器件的性能。
需要解释的是，在本实施例中，P型衬底100可以为独立的衬底，也可为其他衬底（例如SOI衬底）的一部分。并且，本实施例的P型衬底100，也可以采用其他类型的衬底，在此并不进行限定。
图4示出了本发明实施例提出的半导体器件的制造方法的一种示意性流程图，用于简要示出上述方法的典型流程。具体包括：
步骤S101：提供半导体衬底，在所述半导体衬底内形成第一掺杂类型的阱区和第二掺杂类型的阱区，并在所述半导体衬底上形成LDMOS晶体管的栅极，其中所述第二掺杂类型的阱区作为所述LDMOS晶体管的漂移区；
步骤S102：进行第二掺杂类型的离子注入以在所述第一掺杂类型的阱区内形成所述LDMOS晶体管的源极，进行第一掺杂类型的离子注入以在所述第二掺杂类型的阱区内形成第一掺杂类型的离子注入区；
步骤S103：在所述第二掺杂类型的阱区的上方形成金属硅化物，其中所述金属硅化物与所述第二掺杂类型的阱区构成二极管。
实施例三
本发明实施例提供一种电子装置300，如图5所示，其包括半导体器件100。其中，半导体器件100为实施例一所述的半导体器件，或根据实施例二所述的半导体器件的制造方法制造的半导体器件。
本实施例的电子装置，可以是手机、平板电脑、笔记本电脑、上网本、游戏机、电视机、VCD、DVD、导航仪、照相机、摄像机、录音笔、MP3、MP4、PSP等任何电子产品或设备，也可为任何包括半导体器件100的中间产品。
本发明实施例的电子装置，由于使用了上述的半导体器件，因而具有更好的性能。
本发明已经通过上述实施例进行了说明，但应当理解的是，上述实施例只是用于举例和说明的目的，而非意在将本发明限制于所描述的实施例范围内。此外本领域技术人员可以理解的是，本发明并不局限于上述实施例，根据本发明的教导还可以做出更多种的变型和修改，这些变型和修改均落在本发明所要求保护的范围以内。本发明的保护范围由附属的权利要求书及其等效范围所界定。

Claims (15)

1.一种半导体器件，其特征在于，包括第一掺杂类型的半导体衬底以及位于所述半导体衬底内的LDMOS晶体管和二极管，其中，所述半导体衬底与位于其内的第二掺杂类型的阱区形成PN结，所述二极管与所述PN结反向串联，以避免当所述LDMOS晶体管应用于电感负载模式时产生流向所述半导体衬底的大电流；
其中，所述第一掺杂类型与所述第二掺杂类型分别为P型掺杂和N型掺杂，或者，所述第一掺杂类型与所述第二掺杂类型分别为N型掺杂和P型掺杂。
2.如权利要求1所述的半导体器件，其特征在于，所述二极管包括位于所述第二掺杂类型的阱区上方的金属硅化物与所述第二掺杂类型的阱区。
3.如权利要求2所述的半导体器件，其特征在于，所述二极管还包括位于所述第二掺杂类型的阱区内且位于其上部的第一掺杂类型的离子注入区。
4.如权利要求1所述的半导体器件，其特征在于，所述二极管为肖特基二极管。
5.如权利要求1所述的半导体器件，其特征在于，所述LDMOS晶体管包括位于所述半导体衬底内的第一掺杂类型的阱区和所述第二掺杂类型的阱区，还包括位于所述第一掺杂类型的阱区内的源极以及位于所述半导体衬底上的栅极，其中，所述第二掺杂类型的阱区作为所述LDMOS晶体管的漂移区。
6.如权利要求5所述的半导体器件，其特征在于，所述源极为第二掺杂类型的源极。
7.如权利要求4所述的半导体器件，其特征在于，所述LDMOS晶体管还包括位于所述第一掺杂类型的阱区内的体电极。
8.如权利要求7所述的半导体器件，其特征在于，所述体电极为第一掺杂类型的体电极。
9.如权利要求4所述的半导体器件，其特征在于，所述LDMOS晶体管还包括位于所述第一掺杂类型的阱区和/或所述第二掺杂类型的阱区内的浅沟槽隔离。
10.一种半导体器件的制造方法，其特征在于，所述方法包括：
步骤S101：提供半导体衬底，在所述半导体衬底内形成第一掺杂类型的阱区和第二掺杂类型的阱区，并在所述半导体衬底上形成LDMOS晶体管的栅极，其中所述第二掺杂类型的阱区作为所述LDMOS晶体管的漂移区；
步骤S102：进行第二掺杂类型的离子注入以在所述第一掺杂类型的阱区内形成所述LDMOS晶体管的源极，进行第一掺杂类型的离子注入以在所述第二掺杂类型的阱区内形成第一掺杂类型的离子注入区；
步骤S103：在所述第二掺杂类型的阱区的上方形成金属硅化物，其中所述金属硅化物与所述第二掺杂类型的阱区构成二极管；
其中，所述第一掺杂类型与所述第二掺杂类型分别为P型掺杂和N型掺杂，或者，所述第一掺杂类型与所述第二掺杂类型分别为N型掺杂和P型掺杂。
11.如权利要求10所述的半导体器件的制造方法，其特征在于，所述半导体衬底为第一掺杂类型的衬底，所述半导体衬底与所述第二掺杂类型的阱区形成的PN结与所述二极管为反向串联。
12.如权利要求10所述的半导体器件的制造方法，其特征在于，在所述步骤S102中，在所述进行第一掺杂类型的离子注入以在所述第二掺杂类型的阱区内形成第一掺杂类型的离子注入区的过程中，在所述第一掺杂类型的阱区内形成所述LDMOS晶体管的体电极。
13.如权利要求10所述的半导体器件的制造方法，其特征在于，在所述步骤S101中，还包括在所述半导体衬底内形成浅沟槽隔离的步骤。
14.如权利要求10所述的半导体器件的制造方法，其特征在于，在所述步骤S103之后还包括形成层间介电层和接触孔的步骤。
15.一种电子装置，其特征在于，包括如权利要求1所述的半导体器件。
CN201310754079.2A 2013-12-31 2013-12-31 一种半导体器件及其制造方法和电子装置 Active CN104752423B (zh)

Priority Applications (3)

Application Number Priority Date Filing Date Title
CN201310754079.2A CN104752423B (zh) 2013-12-31 2013-12-31 一种半导体器件及其制造方法和电子装置
US14/532,624 US9824928B2 (en) 2013-12-31 2014-11-04 Semiconductor device, related manufacturing method, and related electronic device
US15/806,191 US10211106B2 (en) 2013-12-31 2017-11-07 Semiconductor device, related manufacturing method, and related electronic device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201310754079.2A CN104752423B (zh) 2013-12-31 2013-12-31 一种半导体器件及其制造方法和电子装置

Publications (2)

Publication Number Publication Date
CN104752423A CN104752423A (zh) 2015-07-01
CN104752423B true CN104752423B (zh) 2018-08-21

Family

ID=53482809

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201310754079.2A Active CN104752423B (zh) 2013-12-31 2013-12-31 一种半导体器件及其制造方法和电子装置

Country Status (2)

Country Link
US (2) US9824928B2 (zh)
CN (1) CN104752423B (zh)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9196723B1 (en) * 2014-12-08 2015-11-24 United Microelectronics Corp. High voltage semiconductor devices with Schottky diodes
TWI645534B (zh) * 2015-03-06 2018-12-21 聯華電子股份有限公司 半導體靜電放電保護元件
US10510869B2 (en) 2016-05-06 2019-12-17 Silicet, LLC Devices and methods for a power transistor having a Schottky or Schottky-like contact
US9947787B2 (en) * 2016-05-06 2018-04-17 Silicet, LLC Devices and methods for a power transistor having a schottky or schottky-like contact
KR102424764B1 (ko) * 2018-02-02 2022-07-25 주식회사 디비하이텍 수평형 이중 확산 모스 트랜지스터
CN110024134B (zh) 2019-02-28 2020-06-26 长江存储科技有限责任公司 具有增大的击穿电压的高电压半导体器件及其制造方法
US11228174B1 (en) 2019-05-30 2022-01-18 Silicet, LLC Source and drain enabled conduction triggers and immunity tolerance for integrated circuits
US11417762B2 (en) * 2019-06-26 2022-08-16 Skyworks Solutions, Inc. Switch with integrated Schottky barrier contact
US10892362B1 (en) 2019-11-06 2021-01-12 Silicet, LLC Devices for LDMOS and other MOS transistors with hybrid contact
EP4200911A1 (en) 2020-12-04 2023-06-28 Amplexia, LLC Ldmos with self-aligned body and hybrid source

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101764131A (zh) * 2008-12-26 2010-06-30 世界先进积体电路股份有限公司 具有肖特基二极管的高压半导体元件

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6784489B1 (en) * 1997-03-28 2004-08-31 Stmicroelectronics, Inc. Method of operating a vertical DMOS transistor with schottky diode body structure
US7141860B2 (en) * 2004-06-23 2006-11-28 Freescale Semiconductor, Inc. LDMOS transistor
US7608907B2 (en) * 2005-01-06 2009-10-27 Micrel, Inc. LDMOS gate controlled schottky diode
US7064407B1 (en) * 2005-02-04 2006-06-20 Micrel, Inc. JFET controlled schottky barrier diode
KR100763848B1 (ko) * 2006-07-05 2007-10-05 삼성전자주식회사 쇼트키 다이오드 및 그 제조 방법
US20080246080A1 (en) * 2006-07-28 2008-10-09 Broadcom Corporation Shallow trench isolation (STI) based laterally diffused metal oxide semiconductor (LDMOS)
US20080293205A1 (en) * 2007-05-23 2008-11-27 Oh-Kyum Kwon Method of forming metal silicide layer, and method of manufacturing semiconductor device using the same
KR100932137B1 (ko) * 2007-06-08 2009-12-16 주식회사 동부하이텍 수평형 디모스 소자의 구조 및 그 제조방법
CN201075426Y (zh) 2007-06-21 2008-06-18 富士康(昆山)电脑接插件有限公司 电连接器
US8222698B2 (en) * 2009-06-29 2012-07-17 Analog Devices, Inc. Bond pad with integrated transient over-voltage protection
US8880014B2 (en) * 2010-06-07 2014-11-04 Skyworks Solutions, Inc. CMOS RF switch device and method for biasing the same
US8653535B2 (en) * 2010-09-06 2014-02-18 Panasonic Corporation Silicon carbide semiconductor device having a contact region that includes a first region and a second region, and process for production thereof
CN102610641B (zh) * 2011-01-20 2014-05-21 上海华虹宏力半导体制造有限公司 高压ldmos器件及其制造方法
US9059329B2 (en) * 2011-08-22 2015-06-16 Monolithic Power Systems, Inc. Power device with integrated Schottky diode and method for making the same
US9236472B2 (en) * 2012-04-17 2016-01-12 Freescale Semiconductor, Inc. Semiconductor device with integrated breakdown protection
US9231083B2 (en) * 2012-06-29 2016-01-05 Freescal Semiconductor Inc. High breakdown voltage LDMOS device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101764131A (zh) * 2008-12-26 2010-06-30 世界先进积体电路股份有限公司 具有肖特基二极管的高压半导体元件

Also Published As

Publication number Publication date
US20150187928A1 (en) 2015-07-02
US9824928B2 (en) 2017-11-21
US10211106B2 (en) 2019-02-19
US20180061713A1 (en) 2018-03-01
CN104752423A (zh) 2015-07-01

Similar Documents

Publication Publication Date Title
CN104752423B (zh) 一种半导体器件及其制造方法和电子装置
CN102446955B (zh) 高电压金属氧化半导体装置与制造该装置的方法
TWI617025B (zh) 於高電阻基板上形成的半導體器件及射頻模組
US8338854B2 (en) TVS with low capacitance and forward voltage drop with depleted SCR as steering diode
CN101350351B (zh) 半导体结构及其形成方法
CN104752511B (zh) 场效应半导体器件及其制造
CN102694011B (zh) 半导体器件
US20140167101A1 (en) Tvs with low capacitance & forward voltage drop with depleted scr as steering diode
US9159795B2 (en) High side DMOS and the method for forming thereof
CN105990331B (zh) 一种静电放电保护结构和电子装置
CN103681785A (zh) 半导体装置
CN101999163B (zh) 低漏电流和/或低导通电压的肖特基二极管
CN106257671B (zh) 在高阻衬底上形成的半导体器件和射频模块
Fujii et al. A 90nm bulk BiCDMOS platform technology with 15–80V LD-MOSFETs for automotive applications
CN105448994A (zh) 半导体装置及其制造方法
CN103035525A (zh) 高压隔离n型ldmos器件的制造方法
US9871031B2 (en) Semiconductor device and an electronic apparatus
TW201539745A (zh) 高壓半導體元件及其製造方法
CN111146270A (zh) 一种tvs器件及其制造方法
CN111223931A (zh) 沟槽mosfet及其制造方法
CN103456732B (zh) 具有增强击穿电压的肖特基二极管
TWI517414B (zh) 具有增強崩潰電壓之蕭基特二極體
CN105514091B (zh) 一种半导体器件及其制造方法和电子装置
CN106129119A (zh) 集成肖特基二极管的超结功率vdmos的版图结构及其制作方法
US20150041920A1 (en) Electrostatic discharge protection device and manufacturing method thereof

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant