CN104752229B - 半导体器件及其制造方法 - Google Patents
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Abstract
本发明提供了包括改善的外延形貌的finFET。一种半导体器件包括半导体衬底，该半导体衬底具有形成于其上表面上的多个半导体鳍。外延材料被形成在所述半导体衬底的上表面上以及所述半导体鳍的外表面上。所述外延材料包括epi上表面，所述epi上表面具有接触所述半导体鳍的下部区域和形成于所述下部区域上方的上部区域。所述上部区域与所述半导体鳍的上表面平行地延伸。
Description
技术领域
本发明涉及半导体器件，更具体地说，涉及包括平滑外延形貌的半导体器件。
背景技术
半导体制造工艺利用外延生长材料(即，epi)，例如，掺有磷的硅(Si:P)或硅锗(SiGe)，以使在半导体衬底上形成的半导体鳍(fin)的源极/漏极区合并(merge)。在常规外延生长工艺期间，epi在半导体鳍的侧壁上形成为小平面(facet)，并且可以根据生长方向以不同的且不均匀的速率继续生长。epi的不均匀生长速率导致粗糙(即，波纹形)外延形貌。然而，该粗糙的外延形貌可影响扩散接触(CA)岸面区(landing region)并可增大CA与多晶硅(PC)控制栅极之间的边缘电容。
发明内容
根据至少一个实施例，一种半导体器件包括半导体衬底，该半导体衬底具有形成于其上表面上的多个半导体鳍。外延材料被形成在所述半导体衬底的上表面上以及所述半导体鳍的外表面上。所述外延材料包括epi上表面，所述epi上表面具有接触所述半导体鳍的下部区域和形成于所述下部区域上方的上部区域。所述上部区域与所述半导体鳍的上表面平行地延伸。
一种制造半导体器件的方法包括在半导体衬底的上表面上形成多个半导体鳍。该方法还包括在所述半导体衬底的上表面上以及所述半导体鳍的外表面上生长外延材料。所述外延材料包括epi上表面，所述epi上表面具有接触所述半导体鳍的下部区域和形成于所述下部区域上方的上部区域。所述下部区域和所述上述区域在其间限定第一高度差。该方法还包括使所述上部区域凹陷以限定小于所述第一高度差的第二高度差，从而提高所述epi上表面的平滑度。
通过本发明的技术实现其他的特征。其他实施例在本文中被详细描述，并且被视为所要求保护的发明的一部分。为了更好地理解本发明的特征，参考说明书以及附图。
附图说明
在本说明书的结尾处的权利要求书中具体指出并确切地要求保护被视为本说明书的主题。从以下结合附图进行的详细描述，上述特征是明显的，在附图中：
图1示例出包括覆盖在形成于半导体衬底上的多个半导体鳍周围的栅极叠层的半导体器件的第一取向；
图2示例出在半导体鳍和半导体衬底的表面上生长外延材料以使鳍的源极/漏极区合并在一起之后的图1的半导体器件；
图3是示例出根据第二取向的图2的半导体器件的、沿着A-A’线截取的横截面图，示出了外延材料的有波纹的(corrugated)上表面；
图4示例出在沉积光学平面化层之后根据第一取向的图2-3的半导体器件，该光学平面化层覆盖外延材料的上表面；
图5示例出根据第二取向的图4的半导体器件；
图6示例出在使光学平面化层部分凹陷以暴露外延材料的上部区域之后根据第一取向的图4-5的半导体器件；
图7示例出根据第二取向的图6的半导体器件；
图8示例出在使外延材料的上部区域凹陷以与光学平面化层的剩余部分齐平的蚀刻工艺之后根据第一取向的图6-7的半导体器件；
图9示例出根据第二取向的图8的半导体器件；
图10示例出在从外延材料去除光学平面化层的剩余部分之后根据第一取向的图8-9的半导体器件；
图11示例出根据第二取向的图10的半导体器件，示出了具有减小的高度和提高的平坦度的外延材料的上部区域；
图12示例出在经历退火处理时根据第一取向的图10-11的半导体器件；
图13示例出在使得外延材料的上部区域的平滑度提高的退火处理之后根据第一取向的图12的半导体器件；
图14示例出根据第二取向的图13的半导体器件；以及
图15是示例出根据示例性实施例制造半导体器件的方法的流程图。
具体实施方式
现在参考图1，半导体器件100被总体示出。半导体器件100包括在半导体衬底104上形成的一个或多个半导体鳍102，如本领域普通技术人员所理解的。半导体鳍102和/或半导体衬底104可以由各种材料形成，这些材料包括例如硅(Si)。虽然示例出体(bulk)半导体衬底104，但应理解，半导体衬底104可以被形成为绝缘体上半导体(SOI)衬底，如本领域普通技术人员所理解的。
半导体器件100还包括形成在半导体鳍102上的栅极叠层106。半导体鳍102的源极/漏极区108因此被限定在半导体鳍102上且在栅极叠层106的相反两侧。栅极叠层106可以包括栅极元件110和在栅极元件110的外表面上形成的间隔物(spacer)112。栅极叠层106可以由例如多晶硅(PC)形成。间隔物112可以由包括但不限于氮化硅(SiN)的各种材料形成。
参考图2和图3，在半导体鳍102的外表面上以及衬底的位于半导体鳍102之间的区域上生长外延材料(epi)114。epi 114使半导体鳍102的源极/漏极区108合并在一起。可以使用生长epi 114的各种方法，如本领域普通技术人员所理解的。epi 114可以包括例如掺有磷的硅(Si:P)以及硅锗(SiGe)。
epi 114包括具有波纹(即，粗糙)形貌的上表面。该波纹形貌可以包括沿着半导体器件100的宽度(即，在与栅极叠层的长度垂直的方向上)延伸的一系列峰区116和谷区118。高度差(Δepi1)由一个或多个谷区118与一个或多个峰区116之间的距离限定，如图3所示例的。根据示例性实施例，Δepi1的范围可以为例如约15纳米(nm)到约20nm。
转向图4和5，光学平面化层(OPL)120被沉积在epi 114的上表面上并覆盖栅极叠层106。根据至少一个示例性实施例，OPL 120可以被用于使得能够实现与具有大数值孔径的透镜的浸渍光刻，同时使得反射率最小。OPL 120可以由有机电介质层(ODL)材料形成，所述ODL材料包括但不限于无定形碳、从Cheil Chemical Co.,Ltd.商业可得的CHM701B、从JSR Corporation商业可得的HM8006和HM8014、以及从ShinEtsu Chemical,Co.,Ltd.商业可得的ODL-102。
转向图6和7，使得OPL 120凹陷而暴露epi 114的上部区域，例如，峰区116。根据至少一个实施例，OPL 120被部分凹陷，以便OPL的残留量保持为形成在一个或多个谷区118中。可以使用本领域普通技术人员所理解的等离子体灰化蚀刻工艺来使得OPL 120凹陷。
现在参考图8和9，epi 114经历蚀刻处理，该蚀刻处理使得epi 114的上部区域(例如，峰区116)凹陷。在这方面，峰区116的平坦度提高，从而提高了epi 114的上表面的总平坦度。该蚀刻处理是对间隔物112(例如，SiN)和OPL 120的材料有选择性的。根据至少一个实施例，该蚀刻处理在OPL 120上停止，从而epi 114的凹陷的上部区域116’(例如，凹陷的峰区116’)与OPL 120的剩余部分齐平。在这方面，可以根据在epi 114上剩余的凹陷的OPL120的量来控制epi 114的由于该凹陷处理而调整的高度。相应地，一个或多个谷区118与一个或多个峰区116’之间的距离限定新的高度差(Δepi2)。在epi 114的凹陷的峰区116’与谷区118之间的Δepi2的范围可以为约3nm到约10nm。根据至少一个实施例，Δepi2可以为Δepi1的一半(即，Δepi1/2)。
参考图10和11，从epi 114剥离凹陷的OPL 120的剩余部分。可以使用例如诸如等离子体灰化蚀刻工艺或湿法HF蚀刻的各种蚀刻工艺来剥离OPL 120的剩余部分。等离子体灰化蚀刻工艺可以是对间隔物112和epi 114二者的材料都有选择性的。因此，epi 114被保留，并且包括凹陷的上部区域，即，凹陷的峰部116’，该凹陷的峰部116’包括与半导体鳍102的上表面平行地延伸的变平部。
参考图12，半导体器件100被示例为经历热退火处理。该退火处理可以包括在选定的时间段内将半导体器件100暴露于经加热的氢气(H2)。H2气的温度的范围可以为约750摄氏度(℃)到约800℃，并且该时间段的范围可以为约30秒到约60秒。
参考图13和14，示例出在该热退火处理之后的半导体器件100。响应于该退火处理，epi 114的凹陷的上部区域(即，峰区116’)的高度进一步减小，从而限定在谷区118与蚀刻后的峰区116’之间的第三高度差(Δepi3)。蚀刻后的峰区116’与谷区118之间的Δepi3的范围可以为约1nm到约5nm。在这方面，epi 114的上表面的平坦度被进一步提高，从而epi 114的上表面被平滑化。根据至少一个示例性实施例，该退火处理在epi 114的上表面上形成波形，该波形限定epi 114的平滑上表面。该波形上表面在半导体器件100的相反两端之间连续地延伸。由此，与由于epi 114的过大厚度(例如，约15nm或更大)而不能充分平滑epi 114的上表面的常规制造工艺不同，本教导的至少一个实施例提供了响应于向具有例如约10nm或更小的减小的Δepi的epi 114施加热退火处理而提高epi 114的上表面的平滑度的新的且预料不到的结果。
现在转向图15，流程图示例出根据示例性实施例制造半导体器件100的方法。该方法开始于操作1500，并且继续进行到形成半导体器件的操作1502。该半导体器件包括形成于半导体衬底的上表面上的多个半导体鳍。该半导体器件可以进一步包括覆盖在半导体鳍的一部分周围的栅极叠层以形成栅极沟道，该栅极沟道介于半导体鳍的相反源极/漏极区之间。在操作1504，在与源极/漏极区对应的半导体鳍的外表面上以及半导体衬底的上表面上生长外延材料。该外延材料包括epi上表面，该epi上表面包括与半导体鳍接触的下部区域和形成在该下部区域上方的上部区域。下部区域和上部区域在其间限定出第一高度差。在操作1506，外延材料的上部区域被凹陷以限定第二高度差，该第二高度差小于第一高度差。相应地，epi的上部区域的平坦度相对于先前未凹陷的上部区域提高。在操作1508，对epi上表面进行退火，使得上部区域的高度减小以限定第三高度差并提高epi上表面的平滑度，该第三高度差小于第二高度差，并且，该方法结束于操作1510。相应地，epi上表面的平滑度相对于先前未退火的epi上表面提高。
本文中所用的术语，仅仅是为了描述特定的实施例，而不意图限制本发明。本文中所用的单数形式的“一”和“该”，旨在也包括复数形式，除非上下文中明确地另行指出。还要知道，术语“包含”和/或“包含”在本说明书中使用时，说明存在所指出的特征、整体、步骤、操作、单元和/或组件，但是并不排除存在或增加一个或多个其它特征、整体、步骤、操作、单元组件，以及/或者它们的组合。
在下面的权利要求中的所有装置或步骤加功能要素的对应结构、材料、动作和等价物旨在包括用于与具体地要求保护的其他要求保护的要素组合地执行功能的任何结构、材料或动作。本发明的说明书是为了示例和说明的目的而给出的，而不旨在以所公开的形式穷举或限制本发明。只要不脱离本发明的范围和精神，多种修改和变化对于本领域的普通技术人员而言是显而易见的。为了最好地解释本发明的原理和实际应用，且为了使本领域的其他普通技术人员能够理解本发明的具有适于所预期的特定用途的各种修改的各种实施例，选择和描述了实施例。
本文中描绘的流程图仅仅是一个例子。在不脱离本发明的精神的情况下，可以存在对该流程图或其中描述的步骤的很多变型。例如，所述操作可以以不同的顺序进行或者可以添加、删除或修改操作。所有这些变型都被认为是所要求保护的方面的一部分。
尽管已经描述了各种实施例，但是应当理解，现在以及将来，本领域技术人员可以进行落入后附权利要求的范围内的各种修改。这些权利要求应当被认为保持对被首先描述的本发明的适当保护。
Claims (18)
1.一种制造半导体器件的方法，所述方法包括：
在半导体衬底的上表面上形成多个半导体鳍；
在所述半导体衬底的上表面上以及所述半导体鳍的外表面上生长外延材料，所述外延材料包括epi上表面，所述epi上表面具有接触所述半导体鳍的下部区域和形成于所述下部区域上方的上部区域，所述下部区域和所述上部区域在其间限定第一高度差；以及
使所述上部区域凹陷，以限定小于所述第一高度差的第二高度差且提高所述epi上表面的平坦度，其中凹陷的所述上部区域包括与所述半导体鳍的上表面平行地延伸的部分。
2.根据权利要求1所述的方法，其中，所述使所述上部区域凹陷形成多个凹陷的峰区，所述多个凹陷的峰区具有相对于在执行所述凹陷之前的所述上部区域提高的平坦度。
3.根据权利要求2所述的方法，其中，所述第二高度差的范围为3纳米到10纳米。
4.根据权利要求2所述的方法，还包括：在使所述上部区域凹陷之后对所述epi上表面进行退火，以使得所述上部区域的高度减小而限定小于所述第二高度差的第三高度差。
5.根据权利要求4所述的方法，其中，所述退火使得所述epi上表面平滑化而形成在所述半导体器件的相反端部之间连续地延伸的波形。
6.根据权利要求5所述的方法，其中，所述第三高度差的范围为1纳米到5纳米。
7.根据权利要求6所述的方法，还包括：在使所述上部区域凹陷之前在所述外延材料的所述epi上表面上沉积光学平面层以及使所述光学平面层凹陷而暴露所述上部区域。
8.根据权利要求7所述的方法，其中，所述凹陷包括使所述epi上表面凹陷以使凹陷的峰区与所述光学平面层齐平。
9.根据权利要求8所述的方法，其中，所述光学平面层的高度控制所述凹陷的峰区的高度。
10.根据权利要求9所述的方法，其中，所述退火包括在去除所述光学平面层之后将所述外延材料暴露于经加热的氢气(H2)。
11.根据权利要求10所述的方法，其中，所述半导体衬底由硅形成，并且所述外延材料由选自包括硅锗(SiGe)和掺有磷的硅(Si:P)的组的材料形成。
12.根据权利要求11所述的方法，还包括：在所述半导体器件上形成栅极叠层，所述栅极叠层被配置为覆盖在所述多个半导体鳍中的每个半导体鳍的一部分周围以限定介于相应半导体鳍的相反源极/漏极区之间的相应栅极沟道区。
13.根据权利要求12所述的方法，其中，所述生长所述外延材料包括在所述源极/漏极区上生长所述外延材料以使所述多个鳍合并在一起。
14.一种半导体器件，包括：
半导体衬底，其包括形成于其上表面上的多个半导体鳍；以及
外延材料，其被形成在所述半导体衬底的上表面上以及所述半导体鳍的外表面上，所述外延材料包括epi上表面，所述epi上表面具有接触所述半导体鳍的下部区域和形成于所述下部区域上方的上部区域，所述上部区域包括与所述半导体鳍的上表面平行地延伸的部分，
其中，所述epi上表面包括多个凹陷的峰区，并且所述下部区域包括至少一个介于凹陷的峰区的对之间的谷区，并且
其中，所述epi上表面具有在所述半导体器件的相反端部之间连续地延伸的波形以限定平滑表面。
15.根据权利要求14所述的半导体器件，其中，所述下部区域与所述上部区域之间的距离的范围为1纳米(nm)到3nm。
16.根据权利要求15所述的半导体器件，其中，所述半导体衬底由硅形成，并且所述外延材料由选自包括硅锗(SiGe)和掺有磷的硅(Si:P)的组的材料形成。
17.根据权利要求16所述的半导体器件，还包括栅极叠层，所述栅极叠层覆盖在所述多个半导体鳍中的每个半导体鳍的一部分周围，所述栅极叠层限定介于所述半导体鳍的相反源极/漏极区之间的栅极沟道区。
18.根据权利要求17所述的半导体器件，其中，所述外延材料被形成在所述源极/漏极区上。
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| US10497701B2 (en) * | 2015-12-16 | 2019-12-03 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device and manufacturing method thereof |
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