CN104752225A - Forming method of transistor - Google Patents
Forming method of transistor Download PDFInfo
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- CN104752225A CN104752225A CN201310754232.1A CN201310754232A CN104752225A CN 104752225 A CN104752225 A CN 104752225A CN 201310754232 A CN201310754232 A CN 201310754232A CN 104752225 A CN104752225 A CN 104752225A
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- 238000000034 method Methods 0.000 title claims abstract description 56
- 239000000758 substrate Substances 0.000 claims abstract description 99
- 238000001312 dry etching Methods 0.000 claims abstract description 71
- 238000012545 processing Methods 0.000 claims abstract description 50
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 36
- 229910052814 silicon oxide Inorganic materials 0.000 claims abstract description 24
- 230000008569 process Effects 0.000 claims abstract description 21
- 238000001039 wet etching Methods 0.000 claims abstract description 19
- 238000005530 etching Methods 0.000 claims description 80
- 230000004888 barrier function Effects 0.000 claims description 24
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical group [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 19
- 229910052710 silicon Inorganic materials 0.000 claims description 18
- 239000010703 silicon Substances 0.000 claims description 18
- 230000015572 biosynthetic process Effects 0.000 claims description 13
- 239000003795 chemical substances by application Substances 0.000 claims description 13
- WGTYBPLFGIVFAS-UHFFFAOYSA-M tetramethylammonium hydroxide Chemical compound [OH-].C[N+](C)(C)C WGTYBPLFGIVFAS-UHFFFAOYSA-M 0.000 claims description 12
- XPDWGBQVDMORPB-UHFFFAOYSA-N Fluoroform Chemical compound FC(F)F XPDWGBQVDMORPB-UHFFFAOYSA-N 0.000 claims description 10
- RWRIWBAIICGTTQ-UHFFFAOYSA-N difluoromethane Chemical compound FCF RWRIWBAIICGTTQ-UHFFFAOYSA-N 0.000 claims description 10
- 238000006243 chemical reaction Methods 0.000 claims description 9
- 239000007789 gas Substances 0.000 claims description 9
- CPELXLSAUQHCOX-UHFFFAOYSA-N Hydrogen bromide Chemical compound Br CPELXLSAUQHCOX-UHFFFAOYSA-N 0.000 claims description 8
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 claims description 6
- 239000001307 helium Substances 0.000 claims description 6
- 229910052734 helium Inorganic materials 0.000 claims description 6
- SWQJXJOGLNCZEY-UHFFFAOYSA-N helium atom Chemical compound [He] SWQJXJOGLNCZEY-UHFFFAOYSA-N 0.000 claims description 6
- 230000003647 oxidation Effects 0.000 claims description 6
- 238000007254 oxidation reaction Methods 0.000 claims description 6
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 5
- 239000001301 oxygen Substances 0.000 claims description 5
- 229910052760 oxygen Inorganic materials 0.000 claims description 5
- TXEYQDLBPFQVAA-UHFFFAOYSA-N tetrafluoromethane Chemical compound FC(F)(F)F TXEYQDLBPFQVAA-UHFFFAOYSA-N 0.000 claims description 5
- ZAMOUSCENKQFHK-UHFFFAOYSA-N Chlorine atom Chemical compound [Cl] ZAMOUSCENKQFHK-UHFFFAOYSA-N 0.000 claims description 4
- 239000000460 chlorine Substances 0.000 claims description 4
- 229910052801 chlorine Inorganic materials 0.000 claims description 4
- 229910000042 hydrogen bromide Inorganic materials 0.000 claims description 4
- KWYUFKZDYYNOTN-UHFFFAOYSA-M Potassium hydroxide Chemical compound [OH-].[K+] KWYUFKZDYYNOTN-UHFFFAOYSA-M 0.000 claims description 3
- 229910052786 argon Inorganic materials 0.000 claims description 3
- FAQYAMRNWDIXMY-UHFFFAOYSA-N trichloroborane Chemical compound ClB(Cl)Cl FAQYAMRNWDIXMY-UHFFFAOYSA-N 0.000 claims description 3
- 238000005516 engineering process Methods 0.000 abstract description 4
- 238000000926 separation method Methods 0.000 description 15
- 239000013078 crystal Substances 0.000 description 11
- 239000000463 material Substances 0.000 description 11
- 238000001020 plasma etching Methods 0.000 description 8
- 230000000694 effects Effects 0.000 description 7
- 239000000377 silicon dioxide Substances 0.000 description 6
- 230000008901 benefit Effects 0.000 description 5
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 4
- 229910052581 Si3N4 Inorganic materials 0.000 description 3
- 230000006835 compression Effects 0.000 description 3
- 238000007906 compression Methods 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 230000009467 reduction Effects 0.000 description 2
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 1
- 230000004087 circulation Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000000407 epitaxy Methods 0.000 description 1
- 229910000449 hafnium oxide Inorganic materials 0.000 description 1
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000013011 mating Effects 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 239000002210 silicon-based material Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/3065—Plasma etching; Reactive-ion etching
- H01L21/30655—Plasma etching; Reactive-ion etching comprising alternated and repeated etching and passivation steps, e.g. Bosch process
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
- H01L29/7848—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being located in the source/drain region, e.g. SiGe source and drain
Abstract
The invention provides a forming method of a transistor, wherein a source region and a drain region are formed by employing a stress technology, a groove is formed by dry etching a substrate, and a capitalized sigma-shaped groove is formed by wet etching the groove. When forming the groove by the dry etching, the process of forming the groove comprises multiple times of substrate processing. The substrate processing comprises the following steps performed sequentially: performing an isotropic first dry etching to the exposed substrate of a grid electrode structure, so as to form the groove; covering a silicon oxide layer on the surface of the groove; and performing an anisotropic second dry etching to the groove. Accordingly, the shape of the groove formed thereby is approximate to a jar having a flat bottom. The capitalized sigma-shaped groove formed by wet etching the groove in the shape of the jar is uniform in depth and short in both the vertical distance as well as the horizontal distance, thus the performance of the source region and the drain region of the stress layer formed inside the capitalized sigma-shaped groove can be increased.
Description
Technical field
The present invention relates to semiconductor applications, be specifically related to a kind of formation method of transistor.
Background technology
In existing semiconductor device, stress technique can promote the carrier mobility of channel region in semiconductor device, by providing tensile stress or compression stress to reach the effect improving cmos device carrier mobility to channel region, and then improve the performance of transistor.
Such as: in substrate corresponding to PMOS transistor source region and drain region, form Σ connected in star, epitaxial growth Ge silicon layer in described Σ connected in star again, carry out ion implantation to described germanium silicon layer and form source region and drain region, the raceway groove of described germanium silicon layer energy pair pmos transistor applies compression.
With reference to figure 1, Fig. 2, show the cutaway view that a kind of Transistor forming method of prior art forms Σ connected in star step, grid structure 03 is provided with on substrate 01 surface, grid structure comprises the side wall 05 of grid 04 and grid 04 sidewall, first dry etching is carried out to substrate 01 and form rectangular recess 06, then wet etching is carried out to described rectangular recess 06, form Σ connected in star, formed in Σ connected in star and fill stressor layers, to form source region or drain region 02.The shape in described source region or drain region 02 and the mating shapes of Σ connected in star, thus the cross section in described source region or drain region 02 is hexagon.When measuring source region or the distance between drain region 02 and grid 04 of this shape, usually judged by the distance between the described hexagonal tip (tip) of measurement and grid.This distance comprises vertical range (tip depth) S1 and lateral separation (proximity) S2.Wherein vertical range S1 is tip and the spacing of grid bottom surface along vertical substrates 01 direction, and lateral separation S2 is most advanced and sophisticated and the spacing of relative gate lateral wall along parallel substrate 01 direction.Described vertical range S1 and lateral separation S2 is less, and the source region in Σ type groove or drain region are also just the closer to grid 04, and the stress of generation is larger, and be more conducive to cmos device and improve carrier mobility, the performance of cmos device is also better.
Along with the development of technology, the requirement of vertical range S1 and lateral separation S2 in Σ connected in star is improved day by day.In addition, in prior art, dry etching is formed in the process of rectangular recess 06, the degree of depth difference of different size rectangular recess 06 is larger, rectangular recess 06 degree of depth being positioned at the same size of crystal circle center region and fringe region also has difference, thus also differs larger to the Σ connected in star degree of depth that different rectangular recess 06 wet etchings is formed.
Therefore, how better control dry etching thus the more consistent rectangular recess of Formation Depth, and reduce the vertical range of Σ connected in star and lateral separation becomes problem demanding prompt solution.
Summary of the invention
The problem that the present invention solves is to provide a kind of formation method of transistor, with the vertical range of the consistency and reduction groove that improve groove and lateral separation.
For solving the problem, the invention provides a kind of formation method of transistor, comprising:
Substrate is provided;
Form grid structure over the substrate;
Urniform groove is formed in the substrate that described grid structure exposes;
Wet etching is carried out to described urniform groove, to form Σ connected in star;
Stressor layers is formed, to form source region or drain region in described Σ connected in star;
Wherein, the process forming urniform groove comprises repeatedly substrate processing, and described substrate processing comprises carry out successively step by step following:
Isotropic first dry etching is carried out, to form groove to the substrate that described grid structure exposes;
Barrier bed is formed in described groove surfaces;
Anisotropic second dry etching is carried out to described groove, removes the barrier bed of bottom portion of groove.
Optionally, the step of described first dry etching comprises: in etching machine, carry out described first dry etching, and the source power of etching machine is greater than the bias power of etching machine.
Optionally, the step of described first dry etching comprises: in etching machine, carry out described first dry etching, and the source power of etching machine is in the scope of 1500 watts to 3500 watts, and the bias power of etching machine is in the scope of 0 to 500 watts.
Optionally, described substrate is silicon substrate, and the step of described first dry etching comprises: adopt one or more etching agents as described first dry etching in chlorine, hydrogen bromide, helium, boron chloride.
Optionally, described barrier bed is silicon oxide layer, and the step forming silicon oxide layer in described groove surfaces comprises: the step carrying out being formed described silicon oxide layer in the etching reaction cavity at described etching machine.
Optionally, comprise in the step of described groove surfaces capping oxidation silicon layer: in etching reaction cavity, pass into oxygen, to form silicon oxide layer.
Optionally, comprise in the step of described groove surfaces capping oxidation silicon layer: the source power of etching machine is greater than the bias power of etching machine.
Optionally, comprise in the step of described groove surfaces capping oxidation silicon layer: the difference of etching machine source power and bias power is greater than the difference of etching machine source power and bias power in the first dry etch step.
Optionally, the step of described second dry etching comprises: in etching machine, carry out described second dry etching, and the source power of etching machine is in the scope of 1000 watts to 3000 watts, and the bias power of etching machine is in the scope of 500 watts to 2000 watts.
Optionally, described substrate is silicon substrate, and described barrier bed is silicon oxide layer, and the step of described second dry etching comprises: adopt comprise carbon tetrafluoride, fluoroform, difluoromethane, argon gas, helium gas as the etching gas of described second dry etching.
Optionally, the step that described urniform groove carries out wet etching is comprised: adopt Tetramethylammonium hydroxide or potassium hydroxide solution to carry out wet etching to described urniform groove, to form Σ connected in star.
Optionally, in the process forming urniform groove, in described substrate processing, each time is step by step equal or not etc.
Optionally, formed in the repeatedly substrate processing of urniform groove, after the first dry etching of substrate processing once barrier bed that will be formed in a front substrate processing remove.
Optionally, formed in the repeatedly substrate processing of urniform groove, the time of each substrate processing is identical or different.
Compared with prior art, technical scheme of the present invention has the following advantages:
The etching of groove is divided into the repetition step of multistep isotropism and anisotropic dry etching, enhance the controllability of dry etching, the depth of groove difference of different size is reduced, the depth difference of the groove of the same size being positioned at crystal circle center and crystal round fringes can also be made to reduce.
In addition, formed in the step of urniform groove, in the process of the first dry etching, groove is expanded to horizontal direction and vertical direction simultaneously, makes the sidewall of groove have to the close depression of grid in the horizontal direction, in anisotropic second dry etching, the barrier bed of bottom portion of groove is removed, like this in upper substrate processing once, because recess sidewall has barrier bed, the substrate of bottom portion of groove then for exposing, like this in the first dry etching process of substrate processing each time afterwards, the removed amount of bottom portion of groove is greater than the removed amount of recess sidewall, thus groove vertically deepens more greatly and laterally that broadening is less, thus the width of groove is reduced to bottom gradually from recess, thus the close together of recess distance substrate surface, and depression can be made constantly close to grid through repeatedly such substrate processes, it is narrower that the pattern entirety of groove levels off to opening part more, there is close to opening part the depression of widening, from the urniform groove that the following width of recess reduces gradually, accordingly, when wet etching is carried out to described urniform groove, the recess correspondence of urniform groove forms the hexagonal tip of Σ connected in star, vertical range and the lateral separation of Σ connected in star formed like this are less, stressor layers is formed to form source region or drain region in described Σ connected in star, the performance of transistor can be optimized.
Further, in substrate processing, each time step by step can be unequal, can by the first dry etching in each substrate processing of regulation and control and time of the second dry etching, can also in conjunction with regulation and control source power, make the concave shape of recess sidewall different, to obtain the Σ connected in star with required vertical range and horizontal range.
Accompanying drawing explanation
Fig. 1 to Fig. 2 is the schematic diagram of a kind of Transistor forming method of prior art;
Fig. 3 is the flow chart of Transistor forming method one embodiment of the present invention;
Fig. 4 to Fig. 8 is the generalized section of the forming process of Transistor forming method shown in Fig. 3.
Embodiment
Prior art is formed in the process of Σ connected in star, how better to control the groove that dry etching forms uniform depth, and reduces the vertical range of Σ connected in star and lateral separation becomes problem demanding prompt solution.
In order to solve the problems of the technologies described above, the invention provides a kind of formation method of transistor, the urniform groove that sidewall has depression can be formed in the substrate, the vertical range of the Σ connected in star that wet etching is formed is carried out to described urniform groove and lateral separation less, in described Σ connected in star, form stressor layers to form source region or drain region, the performance of transistor can be optimized.And the etching of groove will be divided into the repetition step of multistep isotropism and anisotropic dry etching, enhance the controllability of dry etching, the depth difference of groove of the same size making the groove of different size or be positioned at crystal circle center and crystal round fringes reduces.
With reference to figure 3, show the flow chart of the formation method of transistor of the present invention, the formation method of transistor of the present invention comprises following roughly step:
Step S1, provides substrate;
Step S2, forms grid structure over the substrate;
Step S3, forms urniform groove in the substrate that described grid structure exposes; The process forming urniform groove comprises repeatedly substrate processing, and described substrate processing comprises carry out successively step by step following:
Step S3A: isotropic first dry etching is carried out, to form groove to the substrate that described grid structure exposes;
Step S3B: form barrier bed in described groove surfaces;
Step S3C: carry out anisotropic second dry etching to described groove, removes the barrier bed of bottom portion of groove.
Step S4, carries out wet etching to described urniform groove, to form Σ connected in star;
Step S5, forms stressor layers in described Σ connected in star, to form source region or drain region.
By above-mentioned steps, better can control the groove that dry etching forms uniform depth, and reduce vertical range and the lateral separation of Σ connected in star, and then improve the performance of transistor.
For enabling above-mentioned purpose of the present invention, feature and advantage more become apparent, and are described in detail specific embodiments of the invention below in conjunction with accompanying drawing.
With reference to figure 4, perform step S1, provide substrate 100, in the present embodiment, described substrate 100 is silicon substrate, and in other embodiments, described substrate 100 can also be other substrate such as germanium silicon layer substrate or silicon-on-insulator substrate, does not do any restriction to this present invention.
Continue with reference to figure 4, perform step S2, described substrate 100 forms grid structure 102.
In the present embodiment, described grid structure 102 comprises grid oxide layer 103, is positioned at grid 104 above grid oxide layer 103, is positioned at the side wall 106 of grid 104 sidewall and is positioned at the cap 105 of grid 104 upper surface.
Particularly, adopt chemical vapour deposition technique to form described grid oxide layer 103, the material of described grid oxide layer 103 is silica; Adopt chemical vapour deposition technique to form described grid 104, the material of described grid 104 is polysilicon; The material of described side wall 106 is silicon nitride, and the material of described cap 105 is titanium nitride, and the effect of described cap 105 is protection grid 104 and as the extension barrier layer of grid 104 in follow-up epitaxy technique.
It should be noted that, the concrete structure of the present invention to grid structure 102 does not limit, and in other embodiments, described grid structure 102 can also be made up of other parts comprising grid 104; The material of the present invention to each several part of grid structure 102 does not also limit, in other embodiments, the material of described grid oxide layer 103 can also be hafnium oxide, the material of described grid 104 can also be metal, described side wall 106 of stating can also be the stacked structure of silicon nitride and silica, and the material of described cap 105 can also be silicon nitride.
Perform step S3, in the substrate that described grid structure 102 exposes, form urniform groove 107.In the present embodiment, step S3 comprises substrate processing described in several times.Here composition graphs 4 to Fig. 7 in the present embodiment first time substrate processing be described in detail.
First continue with reference to figure 4, perform step S3A, isotropic first dry etching is carried out, to form groove 107 to the substrate 100 that described grid structure 102 exposes.
Particularly, the type of the first dry etching is plasma etching, in etching machine, carry out described first dry etching, because described substrate 100 is silicon substrate, adopt one or more etching agents as described first dry etching in chlorine, hydrogen bromide, helium, boron chloride.
In the process of plasma etching, by opening the source power of etching machine, high-frequency electric field can be formed, by etching agent if the ionization such as chlorine, hydrogen bromide is plasma, described substrate 100 is etched, the source power of independent unlatching etching machine, the effect of plasma etching shows as isotropism; And by opening the bias power of etching machine, the speed of the vertical direction of the plasma of described etching agent ionization can be increased, thus the anisotropy of plasma etching is strengthened.
In the process of the first dry etching, the source power of etching machine is 3000 watts, and the bias power of etching machine is 200 watts.The source power of such etching machine is much larger than bias power, and bias power is less, so the isotropism of the first dry etching is stronger.In the process of isotropic first dry etching, groove 107 is expanded to horizontal direction and vertical direction simultaneously, while the degree of depth of groove 107 is increased, the sidewall of groove 107 is also etched and is formed to the close depression of grid 104, after the first dry etching terminates, the circumference of described groove 107 is a curved surface.
It should be noted that, in order to obtain different etching effects, the source power of etching machine can be selected in the scope of 1500 watts to 3500 watts, the bias power of etching machine is being selected in the scope of 0 to 500 watts, but the concrete numerical value of the present invention to the source power of etching machine and bias power does not limit, as long as meet source power to be greater than bias power and the effect of plasma etching shows as isotropism.In addition, in other embodiments, for different substrate types, other etching agent can also be adopted to carry out the first dry etching.
With reference to figure 5, perform step S3B, form barrier bed on described groove 107 surface.
In the present embodiment, described barrier bed is silicon oxide layer 108.
Particularly, oxygen is passed in the same etching reaction cavity of the first dry etching, open the source power of etching machine, form high-frequency electric field, oxygen is ionized for plasma, ionization reacts for the oxygen of plasma and the silicon on described groove 107 surface, makes silicon form one deck silica by autoxidizable mode.Owing to not introducing etching agent in etching machine, so plasma can not cause damage to silicon substrate.
In the process forming silicon oxide layer 108, the source power of etching machine is 3500 watts, bias power is 0 watt, namely source power is much larger than bias power, and source power is now larger than the difference of source power and bias power in the first dry etching with the difference of bias power, so the formation of silica has very strong isotropism, to make silicon oxide layer 108, the surface of groove 107 is all covered.
In other embodiments, the source power of etching machine can be selected in the scope of 1500 watts to 3500 watts, the bias power of etching machine is being selected in the scope of 0 to 500 watts, but the concrete numerical value of the present invention to the source power of etching machine and bias power does not limit, as long as meet source power to be greater than bias power and the formation of silica shows as isotropism.
It should be noted that, in the present embodiment, described barrier bed is the silicon oxide layer 108 formed in the etching reaction cavity of etching machine, such benefit is, three of described substrate processing are all carried out step by step in same etching reaction chamber, do not need in substrate processing step to switch chamber, can ensure that substrate processing is carried out fast and avoids extraneous pollution.But the material of the present invention to barrier bed is not restricted, in other embodiments, barrier bed also can be other materials different from silicon materials etching selection ratio that can be formed at etching reaction cavity; The chamber of the present invention to barrier bed forming step place is not also restricted, and also can carry out the step of described formation barrier bed in other chambers.
With reference to figure 6, perform step S3C, anisotropic second dry etching is carried out to described groove 107, remove the barrier bed bottom groove 107.In the present embodiment, the silicon oxide layer 108 bottom groove 107 is removed.
Particularly, in the process of the second dry etching, described second dry etching is carried out in the same etching reaction cavity of the first dry etching, adopt comprise carbon tetrafluoride, fluoroform, difluoromethane, argon gas, helium gas as the etching gas of described second dry etching, one or more in carbon tetrafluoride, fluoroform, difluoromethane wherein can be selected as etching agent, carbon tetrafluoride, fluoroform, difluoromethane all have higher Selection radio to silica, can be relatively easy to remove the silicon oxide layer 108 bottom groove 107.The source power of etching machine is in the scope of 1000 watts to 3000 watts, and the bias power of etching machine is in the scope of 500 watts to 2000 watts.
In the process of the second dry etching, bias power is larger, the velocity component increase of the vertical direction of the plasma of etching agent ionization is very large, thus the silicon oxide layer 108 be positioned at bottom groove 107 formed in step S3B is removed by very strong second dry etching of the anisotropy of plasma etching, expose substrate 100.Because the anisotropy of the second dry etching is very strong, the damage that the silicon oxide layer 108 of groove 107 sidewall is etched is very little, and the silicon oxide layer 108 bottom groove 107 is removed clean, and the substrate 100 exposed after removing the silicon oxide layer 108 bottom groove 107 surface is smooth.
It should be noted that, in other embodiments, for different barrier bed types, other etching agent can also be adopted to carry out the second dry etching, and the present invention does not limit this.The source power of etching machine also can not in the scope of 1000 watts to 3000 watts, and the bias power of etching machine also can not in the scope of 500 watts to 2000 watts, and the effect of plasma etching shows as anisotropy.
In the present embodiment, step S3A, step S3B are equal with the time of step S3C, all between 1 to 500 milliseconds, such benefit is, substrate processing is carried out comparatively even, is convenient to control, in the process forming groove 107, other parameters after being convenient to regulate each time in substrate processing are to realize the control to groove 107 pattern, but the present invention is not restricted this, and in described substrate processing, each time step by step also can not be waited.After execution step S3C, continue to perform the step S3A in substrate processing next time, in step S3A in upper once substrate processing, the silicon oxide layer 108 of described groove 107 sidewall is removed by isotropic plasma etching, because groove 107 sidewall has the stop of silicon oxide layer 108, silicon substrate then for exposing bottom groove 107, like this in the step S3A afterwards each time in substrate processing, bottom groove 107, removed two are greater than the removed amount of side direction, and thus groove 107 is vertically deepened and laterally broadening is less.
Like this through repeatedly isotropic first dry etching, make groove 107 sidewall to be recessed in horizontal direction, vertical direction constantly close to grid 104, due to formation silicon oxide layer 108 repeatedly and the process of the second dry etching removing groove 107 bottom oxide silicon layer 108, make in the first dry etching each time afterwards, groove 107 vertically deepens more greatly and laterally that broadening is less, make the width of groove 107 from the recess reduction mild to bottom, after repeatedly substrate processing, it is narrower that the pattern entirety of final groove 107 levels off to opening part more, there is close to opening part the depression of widening, the urniform groove tightened up gently below recess, this shape matching is close to hexagonal configuration in Σ type groove, and be recessed in horizontal direction, vertical direction is grid 104 closely.
It should be noted that, the time of step S3 is about 1-3 minute, and the time of each substep of substrate processing is between 1 to 500 milliseconds, so the repeatedly substrate processing described in Transistor forming method of the present invention is actually the substrate processing step that hundreds of times or thousands of secondary circulations are carried out, the etching of groove 107 will be divided into the repetition step of a large amount of isotropism and anisotropic dry etching like this, the time of each substep is all shorter, enhance the controllability of dry etching, the shape of groove 107 can freely be controlled, and the depth difference of groove 107 of the groove 107 of different size or the same size that is positioned at crystal circle center and crystal round fringes reduces.
But the present invention does not limit the number of times of substrate processing in step S3, the time of step S3 and the time of each substep of substrate processing also not being limited, for obtaining the shape of the groove 107 needed, time substrate processing arbitrarily can be carried out.
After second time substrate processing and second time substrate processing in substrate processing each time, each time step by step can be identical with the corresponding time step by step in a front substrate processing, also can be different, that is repeatedly the time of substrate processing identical also can be different.Each time step by step can be identical with the corresponding time step by step in a front substrate processing, simpler to the control of equipment during production, each time step by step can be different from the corresponding time step by step in a front substrate processing, can more easily by changing the shape of each time controling groove 107 step by step in substrate processing each time, make to cave in and can be positioned at the different parts of groove 107 sidewall, after wet etching afterwards, in Σ type groove, the horizontal range of the tip of hexagonal shape and grid 104, vertical range also can freely control.
With reference to figure 7, perform step S4, wet etching is carried out, to form Σ connected in star 108 to described groove 107.
Particularly, Tetramethylammonium hydroxide (TMAH) solution is adopted to carry out wet etching as etching agent to described groove 107, adopt tetramethyl ammonium hydroxide solution to be as the benefit of etching agent, tetramethyl ammonium hydroxide solution has strong basicity, and etching process is comparatively stable.
Due to after step S3, the pattern of groove 107 is close to the hexagonal configuration of Σ connected in star, and through the Σ connected in star 108 pattern standard more that the wet etching of step S4 is formed, each Σ connected in star 108 shape with size levels off to unanimously.Groove 107 be recessed in horizontal direction, vertical direction closer to grid 104, after wet etching afterwards, the recess correspondence of urniform groove forms the hexagonal tip of Σ connected in star, in such Σ type groove 108, the tip of hexagonal shape is closer to grid 104, and namely vertical range (tip depth) D2 and lateral separation (proximity) D1 is less.And due to the uniform depth of groove 107 that formed in step S3 and controlling is strong, the depth difference of Σ connected in star 108 of the same size making the Σ connected in star 108 of different size or be positioned at crystal circle center and crystal round fringes is less.
In other embodiments, the etching agent of wet etching can also adopt potassium hydroxide (KOH) solution or other solution, and the present invention is not restricted this.
With reference to figure 8, perform step S5, epitaxial growth stressor layers 110 in described Σ connected in star, to form source region or drain region.
In the present embodiment, the material of described stressor layers 110 is germanium silicon, for providing compression stress to raceway groove.Because the tip of hexagonal configuration in Σ type groove 108 is closer to grid 104, vertical range D2 and lateral separation D1 is less, epitaxial growth Ge silicon layer in the Σ connected in star 108 that method formed is formed in the present invention, the stressor layers that quality is higher can be obtained, source region in Σ type groove or drain region are closer to grid 104, the stress produced is larger, is conducive to cmos device and improves carrier mobility, thus improve the performance of cmos device.The stressor layers higher to quality carries out that ion implantation forms source region or drain region and the transistor performance that obtains is better.And due to the Σ connected in star 108 of different size or the depth difference of Σ connected in star 108 of the same size that is positioned at crystal circle center and crystal round fringes less, the Σ connected in star 108 hexagonal shape difference of same size is less, make the final source region that formed or drain region performance more stable.
After epitaxial growth stressor layers 110, also need to adulterate to described stressor layers 110, to form source region or drain region.
For verifying the effect of Transistor forming method of the present invention, as shown in Figure 8, the CMOS transistor formed with Transistor forming method of the present invention is tested, measure vertical range D2 and the lateral separation D1 at the tip of hexagonal shape in the Σ connected in star formed, wherein vertical range D2 is less than 8 nanometers, and lateral separation D1 is close to 0 nanometer.The stress that the stressor layers formed in the Σ connected in star that vertical range D2 and lateral separation D1 is less produces is larger, effectively can improve carrier mobility by cmos device, thus improve the performance of cmos device.
Although the present invention discloses as above, the present invention is not defined in this.Any those skilled in the art, without departing from the spirit and scope of the present invention, all can make various changes or modifications, and therefore protection scope of the present invention should be as the criterion with claim limited range.
Claims (14)
1. a formation method for transistor, is characterized in that, comprising:
Substrate is provided;
Form grid structure over the substrate;
Urniform groove is formed in the substrate that described grid structure exposes;
Wet etching is carried out to described urniform groove, to form Σ connected in star;
Stressor layers is formed, to form source region or drain region in described Σ connected in star;
Wherein, the process forming urniform groove comprises repeatedly substrate processing, and described substrate processing comprises carry out successively step by step following:
Isotropic first dry etching is carried out, to form groove to the substrate that described grid structure exposes;
Barrier bed is formed in described groove surfaces;
Anisotropic second dry etching is carried out to described groove, removes the barrier bed of bottom portion of groove.
2. form method as claimed in claim 1, it is characterized in that, the step of described first dry etching comprises: in etching machine, carry out described first dry etching, and the source power of etching machine is greater than the bias power of etching machine.
3. form method as claimed in claim 1, it is characterized in that, the step of described first dry etching comprises: in etching machine, carry out described first dry etching, and the source power of etching machine is in the scope of 1500 watts to 3500 watts, and the bias power of etching machine is in the scope of 0 to 500 watts.
4. form method as claimed in claim 1 or 2, it is characterized in that, described substrate is silicon substrate, and the step of described first dry etching comprises: adopt one or more etching agents as described first dry etching in chlorine, hydrogen bromide, helium, boron chloride.
5. form method as claimed in claim 2, it is characterized in that, described barrier bed is silicon oxide layer, and the step forming silicon oxide layer in described groove surfaces comprises: the step carrying out being formed described silicon oxide layer in the etching reaction cavity at described etching machine.
6. form method as claimed in claim 5, it is characterized in that, comprise in the step of described groove surfaces capping oxidation silicon layer: in etching reaction cavity, pass into oxygen, to form silicon oxide layer.
7. form method as claimed in claim 5, it is characterized in that, comprise in the step of described groove surfaces capping oxidation silicon layer: the source power of etching machine is greater than the bias power of etching machine.
8. form method as claimed in claim 5, it is characterized in that, comprise in the step of described groove surfaces capping oxidation silicon layer: the difference of etching machine source power and bias power is greater than the difference of etching machine source power and bias power in the first dry etch step.
9. form method as claimed in claim 1, it is characterized in that, the step of described second dry etching comprises: in etching machine, carry out described second dry etching, and the source power of etching machine is in the scope of 1000 watts to 3000 watts, and the bias power of etching machine is in the scope of 500 watts to 2000 watts.
10. form method as claimed in claim 1, it is characterized in that, described substrate is silicon substrate, described barrier bed is silicon oxide layer, and the step of described second dry etching comprises: adopt comprise carbon tetrafluoride, fluoroform, difluoromethane, argon gas, helium gas as the etching gas of described second dry etching.
11. form method as claimed in claim 1, it is characterized in that, comprise the step that described urniform groove carries out wet etching: adopt Tetramethylammonium hydroxide or potassium hydroxide solution to carry out wet etching to described urniform groove, to form Σ connected in star.
12. form method as claimed in claim 1, it is characterized in that, in the process forming urniform groove, in described substrate processing, each time is step by step equal or not etc.
13. form method as claimed in claim 1, it is characterized in that, are formed in the repeatedly substrate processing of urniform groove, after the first dry etching of substrate processing once barrier bed that will be formed in a front substrate processing remove.
14. form method as claimed in claim 1, it is characterized in that, formed in the repeatedly substrate processing of urniform groove, the time of each substrate processing is identical or different.
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| CN110459477A (en) * | 2019-08-05 | 2019-11-15 | 上海华力集成电路制造有限公司 | The manufacturing method of semiconductor devices |
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| US20120244674A1 (en) * | 2011-03-23 | 2012-09-27 | Kim Dong Hyuk | Methods for fabricating semiconductor devices |
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