CN103972092B - The manufacture method of transistor and the method determining grid ambient side wall thickness - Google Patents
The manufacture method of transistor and the method determining grid ambient side wall thickness Download PDFInfo
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- CN103972092B CN103972092B CN201310036535.XA CN201310036535A CN103972092B CN 103972092 B CN103972092 B CN 103972092B CN 201310036535 A CN201310036535 A CN 201310036535A CN 103972092 B CN103972092 B CN 103972092B
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66636—Lateral single gate silicon transistors with source or drain recessed by etching or first recessed by etching and then refilled
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/10—Measuring as part of the manufacturing process
- H01L22/12—Measuring as part of the manufacturing process for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
- H01L22/26—Acting in response to an ongoing measurement without interruption of processing, e.g. endpoint detection, in-situ thickness measurement
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/6656—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using multiple spacer layers, e.g. multiple sidewall spacers
Abstract
The manufacture method that the present invention provides a kind of transistor and the method determining grid ambient side wall thickness, the wherein manufacture method of transistor, including: substrate is provided, substrate is formed grid, around grid, form side wall；The first sacrifice side wall is formed around side wall；Side wall is sacrificed as mask with grid, side wall and first, etched substrate, forming bowl-shape groove, side wall and the first gross thickness sacrificing side wall in the first substrate sacrificing side wall both sides makes bowl-shape recess edge distance in extrusion position enters the substrate below grid less than preset distance；The the first sacrifice side wall removing segment thickness forms the second sacrifice side wall, and the bowl-shape groove of wet etching forms sigma connected in star, and wherein, side wall and the second gross thickness sacrificing side wall can form sigma connected in star after guaranteeing the bowl-shape groove of wet etching；Remove the second sacrifice side wall, filling semiconductor material in sigma connected in star.The method using the present invention can improve the performance of device.
Description
Technical field
The invention belongs to field of semiconductor manufacture, particularly relate to the manufacture method of a kind of transistor and determine
The method of grid ambient side wall thickness.
Background technology
In existing semiconductor device fabrication process, owing to stress can change energy gap and the carrier of silicon materials
Mobility, therefore improves, by stress, the means that the performance of MOS transistor becomes more and more conventional.Tool
Body ground, by suitable proof stress, can improve carrier (electronics in nmos pass transistor, PMOS
Hole in transistor) mobility, and then improve driving electric current, it is greatly enhanced MOS transistor with this
Performance.For PMOS transistor, embedded silicon germanium technologies (Embedded SiGe can be used
Technology) produce compressive stress with the channel region at transistor, and then improve carrier mobility.Institute
Call embedded silicon germanium technologies and refer to embedding silicon in the region needing to be formed source electrode and drain electrode of Semiconductor substrate
Germanium material, utilizes the lattice mismatch between silicon and SiGe (SiGe) that channel region is produced compressive stress.Existing
Have in technology and have many patents about embedded silicon germanium technologies PMOS transistor and patent application, example
In the Chinese patent application document of Publication No. CN102097491A as disclosed in 15 days June in 2011
The forming method of the PMOS transistor of disclosed embedded silicon germanium technologies.
Fig. 1 is the sectional view of a kind of PMOS transistor that have employed embedded silicon germanium technologies, as it is shown in figure 1,
PMOS transistor includes grid 2, be formed at around grid 2 side wall 3 and be respectively formed at side wall 3 both sides
Source electrode 5, drain electrode 6, source electrode 5 and drain electrode 6 are to be made up of the silicon germanium material being filled in sigma connected in star 8.
But, the PMOS transistor performance utilizing prior art to be formed is bad.
Summary of the invention
The technical problem to be solved in the present invention is that the PMOS transistor performance utilizing prior art to be formed is bad.
For solving the problems referred to above, the invention provides the forming method of a kind of transistor, described method includes:
Substrate is provided, forms grid over the substrate, around described grid, form side wall；
The first sacrifice side wall is formed around side wall；
With described grid, side wall and the first sacrifice side wall as mask, etch described substrate, sacrifice first
The substrate of side wall both sides is formed bowl-shape groove, described side wall and the first gross thickness sacrificing side wall and makes institute
State bowl-shape recess edge distance in the substrate that extrusion position enters below described grid less than pre-spacing
From；
The the first sacrifice side wall removing segment thickness forms the second sacrifice side wall, bowl-shape recessed described in wet etching
Groove forms sigma connected in star, and wherein, side wall and the second gross thickness sacrificing side wall guarantee described wet etching
Sigma connected in star can be formed after bowl-shape groove；
Remove the second sacrifice side wall, filling semiconductor material in described sigma connected in star.
Optionally, the described first sacrifice side wall that formed around side wall includes:
The material layer sacrificing side wall is formed at described grid and side wall surface；
Carry out back carving to the material layer of described sacrifice side wall, form the first sacrifice side wall.
Optionally, the described first material sacrificing side wall is amorphous carbon.
Optionally, the forming method of the material layer of described sacrifice side wall be plasma activated chemical vapour deposition,
Ion evaporation sedimentation or sputtering method.
Optionally, the first sacrifice side wall and second removing described segment thickness sacrifices the method for side wall for grey
Change.
Optionally, described preset distance is 1nm.
Optionally, described semi-conducting material is germanium silicon material or carbofrax material.
Optionally, described side wall is single layer structure or laminated construction.
Optionally, the grid during described grid is front grid technique；Or, for the dummy grid in rear grid technique.
The present invention also provides for a kind of method determining grid ambient side wall thickness, utilizes the above-mentioned side forming transistor
Method is during forming transistor:
Obtain the first sacrifice side wall and the gross thickness of side wall formed, be the first measured value；
Set the thickness that should form total side wall around grid as first object value, according to described first measured value
The thickness of the first sacrifice side wall that should remove is determined with described first object value；
According to the thickness of the should remove the first sacrifice side wall determined, it is removed the first sacrificial of segment thickness
The step of domestic animal side wall, after forming the second sacrifice side wall, obtains the second sacrifice side wall and gross thickness of side wall,
It it is the second measured value；
Obtain the second measured value and the difference of first object value；
Redefining according to described difference and should forming the thickness of total side wall around grid is the second desired value.
Optionally, described substrate is divided into device region and measurement zone, described device region to be real over the substrate
Border forms the region of device, and described measurement zone is over the substrate for the region measured；
The transistor formed on described substrate is arranged in array, and described transistor is formed at described measurement zone.
Optionally, described determine according to the first measured value and described first object value should remove first sacrifice
The step of the thickness of side wall includes:
The difference of the first measured value and described first object value is the thickness of the first sacrifice side wall that should remove.
Optionally, determine that the method for described second desired value includes:
When described second measured value is less than first object value, the second desired value=first object value+described difference
Value；
When described second measured value is more than first object value, the second desired value=first object value-described difference
Value.
Optionally, the acquisition methods of described first measured value is:
Use optical feature dimension to measure device measuring first and sacrifice the gross thickness of side wall and side wall, or,
When side wall is definite value, uses optical feature dimension to measure device measuring first and sacrifice the thickness of side wall.
Optionally, the acquisition methods of described second measured value is:
Use optical feature dimension to measure device measuring second and sacrifice the gross thickness of side wall and side wall, or,
When side wall is definite value, uses optical feature dimension to measure device measuring second and sacrifice the thickness of side wall.
The present invention also provides for a kind of method forming transistor, including,
Substrate is provided；
Substrate is formed grid；
Forming side wall around described grid, the thickness of described side wall above-mentioned determines grid ambient side for utilizing
The thickness of total side wall that the method for wall thickness determines；
Form source electrode, drain electrode.
Compared with prior art, the invention have the advantages that
The present invention sacrifices side wall by formation first around side wall, sacrifices side wall with side wall and first and is
Mask etching substrate, after forming bowl-shape groove, removes part thick in the first substrate sacrificing side wall both sides
First sacrifice side wall of degree forms the second sacrifice side wall, then continues with side wall and the second sacrifice side wall for mask
The bowl-shape groove of wet etching, forms sigma connected in star.Around side wall, side wall, side are sacrificed in formation first
Wall and the first gross thickness sacrificing side wall can make the extrusion position at the edge of bowl-shape groove enter described grid
The distance in substrate below pole is less than preset distance, thus is not easy to destroy the structure of raceway groove, and then makes
The structure of raceway groove is not destroyed at the tip of the sigma connected in star that must be subsequently formed, and improves the transistor being subsequently formed
Performance.If directly sacrificing side wall as mask with side wall and first, bowl-shape recess etch is formed sigma
During connected in star, the gross thickness that side wall and first sacrifices side wall is the biggest so that the sigma being subsequently formed
The shape of connected in star is bad, serious in the case of, will be unable to form sigma connected in star, thus affect follow-up
The performance of the transistor formed.Therefore, the present invention, after forming bowl-shape groove, needs to sacrifice first
The thickness of side wall is thinned to the second sacrifice side wall, with side wall and second sacrifice side wall as mask, by bowl-shape recessed
Groove wet etching, thus form shape preferable sigma connected in star.Therefore the present invention is at whole making sigma
During connected in star, the technique that improve sigma connected in star makes precision, and then improves subsequent transistor
Performance.
Accompanying drawing explanation
Fig. 1 is the profile of a kind of PMOS transistor that have employed embedded silicon germanium technologies；
Fig. 2 is the Making programme figure of the transistor of the present invention；
Fig. 3 to Fig. 9 is the preparation method of transistor of the present invention cross-sectional view in the different production phases；
Figure 10 be the measurement zone of Semiconductor substrate grid and grid both sides formed sigma connected in star
Schematic top plan view；
Figure 11 be the device region of Semiconductor substrate grid and grid both sides formed sigma connected in star
Schematic top plan view.
Detailed description of the invention
Inventor finds occur that the bad reason of PMOS transistor performance is through research:
Please continue to refer to Fig. 1, the substrate below grid 2 is the channel region of PMOS transistor, sigma shape
Groove 8 has flute tips 81, the horizontal distance W between flute tips 81 and gate lateral wall 2a and side wall 3
Thickness relevant.During making transistor, the thickness of side wall 3 is not easily controlled, when side wall 3
When thickness is blocked up, the method for thinning side wall thicknesses can be used to make up；When the thickness of side wall 3 is crossed thin,
The flute tips being then subsequently formed enters the horizontal range meeting in the substrate below grid through gate lateral wall 2a
Exceeding preset distance, thus be easily destroyed channel region, the PMOS transistor content being subsequently formed is easily generated leakage
Electric current, the performance of the transistor that impact is subsequently formed.
In sum, inventor is through creative work, it is thus achieved that the manufacture method of a kind of transistor.Fig. 2
It it is the Making programme figure of the transistor of the present invention.Fig. 3 to Fig. 9 is that preparation method of transistor of the present invention is not
Cross-sectional view with the production phase.Below Fig. 3 to Fig. 9 is combined the present invention with Fig. 2
The manufacture method of transistor is described in detail.
Referring first to Fig. 3, perform step S11 in Fig. 2: provide substrate 20, on described substrate 20
Form grid 21, around described grid 21, form side wall 24.
The material of described substrate 20 can be monocrystal silicon (monocrystalline) substrate, it is also possible to be exhausted
Silicon (silicon on insulator) substrate on edge body.Certainly, it can also be that those skilled in the art institute is ripe
Other backing material known.
The material of grid 21 can be polysilicon or unformed silicon.Described grid is the grid in front grid technique；
Or, for the dummy grid in rear grid technique.In the present embodiment, grid 21 is the grid of front grid technique.
Then, in the present embodiment, in the substrate of the both sides of described grid 21, LDD structure (figure is formed
Do not show), in other embodiments, it is also possible to be formed without LDD structure.
In the present embodiment, after forming described LDD structure, around described grid 21, form side wall 24.
Please continue to refer to Fig. 3, in the present embodiment, the forming method of side wall 24 includes: shape on a substrate 20
Become the material layer (not shown) for forming side wall 24, carry out back described material layer carving (etch back),
Formation side wall 24 around grid 21.In the present embodiment, side wall 24 is single layer structure, described side wall
The material of 24 is silicon nitride.In other embodiments, side wall 24 can also be laminated construction, such as, side
The primer of wall 24 is silicon oxide, and quilting material is silicon nitride.
Then, refer to Fig. 4 and Fig. 5, perform step S12 in Fig. 2, around side wall 24, form the
One sacrifices side wall 25.
The first sacrifice side wall 25 is formed specifically comprises the processes of: at described grid 21 and side wall around side wall 24
24 surfaces form the material layer 25 ' sacrificing side wall, then carry out back the material layer 25 ' of described sacrifice side wall
Carve, form the first sacrifice side wall 25.
Sacrifice the forming method of material layer 25 ' of side wall include plasma activated chemical vapour deposition (PECVD),
Ion evaporation sedimentation or sputtering method etc., the common ground of all these methods is that synthesis temperature is low (is
400 DEG C or lower).In PECVD or ion evaporation sedimentation, can by Hydrocarbon (as propylene,
CH4、C2H2、C2H4、C2H6、C3H8Etc.) as raw material, in order to control to sacrifice the material of side wall
The quality of layer 25 ', usually adds hydrogen.In sputtering method, in order to control to sacrifice the material layer 25 ' of side wall
Quality, general add hydrogen or hydrocarbon gas.
In the present embodiment, the first material sacrificing side wall 25 is amorphous carbon, available O2And Cl2、O2
And HBr or O2And CF4Carry out back the material layer 25 ' sacrificing side wall carving to form the first sacrifice side wall 25.
Then, refer to Fig. 6, perform step S13 in Fig. 2, with described grid 21, side wall 24 and
First sacrifice side wall 25 is mask, etches described substrate 20, at the first substrate sacrificing side wall 25 both sides
Middle formation bowl-shape groove 26a, described side wall 24 and the first gross thickness sacrificing side wall 25 make described bowl-shape
Groove 26a edge distance in extrusion position 26b enters the substrate 20 below described grid 21 is little
In preset distance.
The forming method of bowl-shape groove 26a includes: sacrifice side wall 25 with grid 21, side wall 24 and first
For mask, utilize substrate 20 described in isotropic dry etching, at the first lining sacrificing side wall 25 both sides
The end, is formed bowl-shape groove 26a.Wherein, described anisotropic dry etch process parameter includes: etching
Gas includes Cl2And NF3, temperature is 40 DEG C ~ 60 DEG C, and bias power is 100W ~ 500W, biases and is
0V ~ 10V, the time is 5s ~ 50s.
In the present embodiment, preset distance is 1nm.When the thickness of side wall 24 is crossed thin, if directly with side
Substrate is performed etching by wall 24 for mask, and the extrusion position 26b at the bowl-shape groove 26a edge of formation enters
Enter the horizontal range in grid 21 lower substrate and can easily exceed 1nm, and then make the sigma being subsequently formed
The most advanced and sophisticated horizontal range entered in grid 21 lower substrate of connected in star is easier to more than 1nm, therefore, and this
The sigma connected in star formed in the case of Zhong can destroy the structure of raceway groove, and the transistor being subsequently formed can produce leakage
Electric current.In the present embodiment, around side wall 24, side wall 25, side wall 24 and first are sacrificed in formation first
It is described that the gross thickness of sacrifice side wall 25 can make the extrusion position 26b at the edge of bowl-shape groove 26a enter
The horizontal range in substrate 20 below grid 21 is less than 1nm, thus is not easy to destroy the structure of raceway groove,
And then making the tip of the sigma connected in star being subsequently formed not destroy the structure of raceway groove, raising is subsequently formed
The performance of transistor.
Further, sigma connected in star tip pass gate lateral wall, and and gate lateral wall between level
Distance has optimum range.If the distance between sigma connected in star tip and gate lateral wall is at optimum range
In, then the effect of the stress that the most advanced and sophisticated transistor to being subsequently formed of sigma connected in star applies is also optimal, wherein,
Optimum range is more than or equal to 0nm and less than or equal to 1nm.The method using the present embodiment, can be by
Distance between sigma connected in star tip and gate lateral wall is adjusted at optimum range, thus improves sigma
The technique of connected in star makes precision, and then can improve the performance of the transistor being subsequently formed further.
Then, refer to Fig. 7, perform step S14 in Fig. 2, remove the first sacrifice side of segment thickness
Wall 25 forms the second sacrifice side wall 25 ", bowl-shape groove 26a described in wet etching forms sigma connected in star
26, wherein, side wall 24 and second sacrifices side wall 25 " gross thickness guarantee the bowl-shape groove of described wet etching
Sigma connected in star 26 can be formed after 26a.
In the present embodiment, after forming bowl-shape groove 26a in the first substrate sacrificing side wall 25 both sides, also
Need to sacrifice side wall 25 to first to carry out back carving so that the first thickness sacrificing side wall 25 is decreased to be formed
Second sacrifices side wall 25 ".Wherein, O can be used2And N2、O2And HBr or O2And CF4Sacrificial to first
Domestic animal side wall 25 carries out back carving to form the second sacrifice side wall 25 ".
Form the second sacrifice side wall 25 " after, use wet etching bowl-shape groove 26a to form sigma connected in star
26.Particularly as follows: bowl-shape groove 26a is exposed to TMAH(Tetramethyl Ammonium Hydroxied,
Tetramethyl aqua ammonia) in aqueous solution, TMAH aqueous corrosion substrate 20, bowl-shape groove wet method is rotten
Lose into sigma connected in star 26.Wherein, the concentration of volume percent of TMAH aqueous solution is 2% ~ 20%,
Temperature is 30 DEG C ~ 60 DEG C, and the time is 100s ~ 300s.Concrete etch period can be according to sigma connected in star
Depending on the desired size of 26.
TMAH has higher corrosion rate, nontoxic pollution-free, convenient to operate, and the crystal orientation of TMAH
Selectivity is good, and its corrosion rate on crystal orientation<100>and<110>direction is very fast, and in other crystal orientation side
To, as the corrosion rate on crystal orientation<111>is very slow, therefore, available TMAH aqueous solution is at substrate
There is on different crystal orientations the characteristic of different etching speed, continue to etch bowl-shape groove 26a to form sigma
Connected in star 26.
In the present embodiment, when the thickness of side wall 24 is crossed thin, around side wall 24, formation first is sacrificed
Side wall 25, side wall 24 and first sacrifices the gross thickness of side wall 25 so that the sigma shape that is subsequently formed
The structure of raceway groove is not destroyed at the tip of groove, solve of the prior art because of the thickness of side wall 24 cross thin and
The problem making PMOS transistor hydraulic performance decline.But, in the present invention solve of the prior art because of
The thickness of side wall 24 cross thin and while making PMOS transistor degradation problem, it may appear that following defect:
If directly sacrificing side wall 25 as mask with side wall 24 and first, bowl-shape groove 26a corrosion is formed sigma
During connected in star 26, side wall 24 and the first gross thickness sacrificing side wall 25 can be the biggest so that follow-up
The shape of sigma connected in star formed is bad, serious in the case of, will be unable to form sigma connected in star,
Thus affect the performance of the transistor being subsequently formed.Therefore, in order to solve to form sigma connected in star
Problem, the present embodiment, after forming bowl-shape groove 26a, needs the thickness by first sacrifices side wall 25 to subtract
It is as thin as the second sacrifice side wall 25 ", sacrifice side wall 25 with side wall 24 and second " as mask, by bowl-shape groove
26a wet etching, thus form shape preferable sigma connected in star 26, therefore, the present embodiment is solving
Of the prior art make the same of PMOS transistor degradation problem because the thickness of side wall 24 crosses thin
Time, also solve the problem that cannot form shape preferable sigma connected in star, improve subsequent crystallographic further
The performance of pipe.
In the present embodiment, sacrifice side wall by formation around side wall first, sacrifice side with side wall and first
Wall is mask etching substrate, after forming bowl-shape groove, removes part in the first substrate sacrificing side wall both sides
First sacrifice side wall of thickness forms the second sacrifice side wall, then sacrifices side wall for mask continuation with side wall and second
The bowl-shape groove of wet etching, forms sigma connected in star.Therefore side wall and first sacrifices side wall, side wall and the
Two sacrifice side wall jointly acts on and through gate lateral wall, sigma connected in star tip can be entered the lining below grid
Horizontal range at the end is less than preset distance, and makes the shape of sigma connected in star preferably, thus improves
It is subsequently formed the performance of transistor.Further, can be by between sigma connected in star tip and gate lateral wall
Distance be adjusted in optimum scope, and it is also possible that the shape of sigma connected in star is preferable, thus
Improve the technique making precision making sigma connected in star, and then raising is subsequently formed transistor further
Performance.
After forming sigma connected in star 26, refer to Fig. 8 and Fig. 9, perform step S15 in Fig. 2,
Remove described second and sacrifice side wall 25 ", in described sigma connected in star 26, form semi-conducting material 27.
In the present embodiment, remove second sacrifice side wall 25 " method for ashing.Why use cineration technics,
It is because the infringement that other structure on substrate 20 causes by podzolic gas less, and technique is the simplest.
The technological parameter of cineration technics includes: O2 flow is 100sccm ~ 500sccm, and ashing power is
1000W ~ 2000W, the time is 60s ~ 120s.
Remove the second sacrifice side wall 25 " after, in sigma connected in star 26, form semi-conducting material 27.Tool
Body is: when the transistor being subsequently formed is PMOS transistor, and semi-conducting material 27 is germanium silicon (SiGe)
Material, silicon germanium material can introduce the compressive stress that between silicon and germanium silicon, lattice mismatch is formed, improve further
Compressive stress, thus improve the performance of PMOS transistor；When the transistor being subsequently formed is NMOS crystal
Guan Shi, semi-conducting material 27 is carborundum (SiC) material, and carbofrax material can introduce silicon and carbon silicon
Between the tension that formed of lattice mismatch, improve tension further, improve the performance of nmos pass transistor.
The formation process of semi-conducting material 27 is depositing operation or selective epitaxial growth process.The present invention's
In embodiment, when using selective epitaxial growth process to form germanium silicon material, the reactant of employing includes:
Silicon source gas SiH4、SiH2Cl2Or Si2H6, and ge source gas GeH4, it is used for forming germanium silicon material.For
In avoiding germanium silicon material or other need not form the local of germanium silicon and produce impurity, in described reactant also
Including HCl, and, in order to avoid the silicon on Semiconductor substrate 20 surface is oxidized, form oxide film shadow
Ring the performance of transistor, while using selective epitaxial growth process to form germanium silicon material, be also passed through hydrogen
Gas.
In an embodiment of the present invention, described selective epitaxial depositing operation forms the parameter bar of germanium silicon material
Part includes: temperature is 550 DEG C ~ 800 DEG C, and pressure is 5Torr ~ 20Torr, silicon source gas SiH2Cl2、SiH4
Or Si2H6Flow be 30sccm ~ 500sccm, ge source gas GeH4Flow be 5sccm ~ 500sccm,
The flow of HCl is 50sccm ~ 500sccm, H2Flow be 5slm ~ 50slm.
It should be noted that in other embodiments of the invention, if semi-conducting material 27 is carborundum,
The reactant using the carborundum of selective epitaxial growth process formation includes: SiH4With dimethylamine silane,
HCl and H can also be included2。
Formed after semi-conducting material 27 in sigma connected in star 26, carry out ion implanting, formed source electrode and
Drain electrode.
Present invention also offers a kind of method determining grid ambient side wall thickness, in the mistake forming transistor
Cheng Zhong, so that the sigma connected in star formed is most advanced and sophisticated and the position adjustment of gate lateral wall is to more next time
Good, and make the shape of sigma connected in star more preferable so that the technique forming sigma connected in star makes essence
Du Genggao.Particularly as follows:
In step S12 with reference to a upper embodiment, around side wall 24, form the first sacrifice side wall 25
After, measure the first sacrifice side wall 25 and gross thickness of side wall 24, be the first measured value.Such as, first
Measured value is 500 angstroms.
Side wall 25 is sacrificed as mask with described side wall 24 and first, etched substrate, sacrifice side wall first
The substrate of 25 both sides is formed bowl-shape groove 26a.Specifically refer to step S13 of an embodiment.
With reference to step S14 of a upper embodiment, after forming bowl-shape groove 26a, also there will be new defect:
If continuing to sacrifice side wall 25 as mask with side wall 24 and first, bowl-shape groove 26a will be unable to form sigma
The shape of connected in star.Therefore, in the present embodiment, in order to ensure the shape of the sigma connected in star being subsequently formed,
The the first sacrifice side wall 25 removing segment thickness is needed to form the second sacrifice side wall 25 ".Particularly as follows:
(1) thickness that should form total side wall around grid 21 is set as first object value, wherein, grid
Should form total side wall around 21 is that side wall 24 and second sacrifices side wall 25 ".According to first measured value measure and
First object value determines the thickness of the first sacrifice side wall 25 that should remove, specifically, the first measured value and the
The difference of one desired value is the thickness of the first sacrifice side wall 25 that should remove.Such as, should around grid 21
The first object value of the thickness forming total side wall is 300 angstroms, then should remove the thickness of the first sacrifice side wall 25
It it is 200 angstroms.
(2) according to the thickness of the should remove the first sacrifice side wall 25 determined, it is removed segment thickness
First sacrifice side wall 25 step, formed second sacrifice side wall 25 " after, measure second sacrifice side wall 25 "
With the gross thickness of side wall 24, it it is the second measured value.Remove part first to sacrifice side wall 25 to form second sacrificial
Domestic animal side wall 25 " after, the second measured value there will be the situation less than first object value, such as 280 angstroms, or greatly
In the situation of first object value, such as 320 angstroms.
(3) the second measured value and the difference of first object value are calculated.Such as, it is 280 when the second measured value
Angstrom time, the difference between the second measured value 280 angstroms and first object value 300 is 20 angstroms；When second measures
When value is 320 angstroms, the difference between the second measured value 320 angstroms and first object value 300 is also 20 angstroms.
(4) redefine according to described difference that should to form the thickness of total side wall around grid 21 be the second mesh
Scale value.
When described second measured value is less than first object value, the second desired value=described desired value+described difference
Value；Such as, when the second measured value is 280 angstroms, and first object value is 300 angstroms, difference is 20 angstroms,
Second+20 angstroms, desired value=300 angstrom=320 angstrom.
When described second measured value is more than first object value, the second desired value=described desired value-described difference
Value.Such as, when the second measured value is 320 angstroms, and first object value is 300 angstroms, difference is 20 angstroms,
Second-20 angstroms, desired value=300 angstrom=280 angstrom.
After should forming the desired value of total side wall thicknesses around the grid 21 that described difference redefines, i.e.
After determining the second desired value, then perform step (1) to the operation of step (4) so that in upper once shape
During becoming sigma connected in star, total side wall thicknesses that grid 21 surrounding is formed is more accurate.The present embodiment
In, need circulation step (1) to step (4), until total side wall thicknesses that grid 21 surrounding is formed is permissible
Till making the most advanced and sophisticated position with gate lateral wall of the sigma connected in star being subsequently formed be in optimum range, thus
During making transistor, the technique improving sigma connected in star makes precision, and then improves this crystal
The performance of pipe.
In the present embodiment, after forming the first sacrifice side wall 25 around side wall 24, it is thus achieved that the first measured value
During, the gross thickness that can measure the first sacrifice side wall 25 and side wall 24 obtains the first measured value.When
When side wall 24 is definite value, it is also possible to directly measure the thickness of the first sacrifice side wall 25, then plus side wall 24
Thickness, obtain the first measured value.
Form the second sacrifice side wall 25 " after, it is thus achieved that during the second measured value, the second sacrifice can be measured
Side wall 25 " and the gross thickness of side wall 24 obtain the second measured value.When side wall 24 is definite value, it is also possible to straight
Connect and measure the second sacrifice side wall 25 " thickness, then plus the thickness of side wall 24, obtain the second measured value.
With reference to Figure 10 and Figure 11, in the present embodiment, employing optical feature dimension measurement equipment (Optical CD,
OCD) the first measured value and the second measured value are obtained.Optical feature dimension is measured equipment and can only be arranged in matrix
The object of row detects.Therefore, in the present embodiment, on the same substrate, in order to be able to measure on this substrate
The processing technology of device on this substrate is not the most affected while total side wall thicknesses around grid.Quasiconductor is being provided
After substrate, this substrate is divided into device region (with reference to Figure 10) and measurement zone (with reference to Figure 11), described device
Part district is the follow-up region being actually formed device on substrate, described measurement zone be follow-up on substrate for entering
The region that row is measured, the transistor formed on the substrate of measurement zone needs to be arranged in array.
With reference to Figure 10, the grid 21 formed on the substrate of device region, the side wall around grid, described side
The first sacrifice side wall around wall, the bowl-shape groove 26a in the first substrate sacrificing side wall both sides are not
The most arranged in arrays.With reference to Figure 11, the substrate of measurement zone forms grid 21, at grid 21
Side wall around, first around described side wall sacrifices side wall, in the first substrate sacrificing side wall both sides
Bowl-shape groove 26a be arranged in arrays, so as to use optical feature dimension measure equipment carry out
Measure.Wherein, the grid of the transistor of total side wall and measurement zone around the grid in the transistor of device region
The most total side wall forming step is identical.It should be noted that the effect of the transistor of measurement zone is simply measured
Side wall thicknesses around grid, might not have the function of device region transistor.Certainly, real at other
Executing in example, the transistor of measurement zone can also have the function of transistor.The present embodiment use optics special
Levy dimension measuring apparatus to obtain the method for the first measured value and the second measured value there is the advantage of measurement in real time,
Structure to be measured need not be carried out that section etc. is destructive to be processed, simplify technique, reduce expense can
Real-time monitoring, to be adjusted etch process parameters in time, improves work efficiency.
In other embodiments, it would however also be possible to employ other measurement equipment obtain the first measured value and second and measure
Value, nor affects on the enforcement of the present invention.
Present invention also offers the manufacture method of a kind of transistor, including:
Substrate is provided, the substrate of device region is formed grid；Total side wall, institute is formed around described grid
The thickness stating total side wall is the thickness that described in above-described embodiment, method determines；Form source electrode, drain electrode.
Above by the explanation of embodiment, professional and technical personnel in the field should be able to be made to be more fully understood that the present invention,
And can reproduce and use the present invention.Those skilled in the art can according to principle specifically described herein
To above-described embodiment as various changes and modifications to be without departing from the spirit and scope of the present invention
Obviously.Therefore, the present invention should not be construed as being limited to above-described embodiment shown in this article, its
Protection domain should be defined by appending claims.
Claims (16)
1. the manufacture method of a transistor, it is characterised in that including:
Substrate is provided, forms grid over the substrate, around described grid, form side wall；
The first sacrifice side wall is formed around side wall；
With described grid, side wall and the first sacrifice side wall as mask, etch described substrate, sacrifice first
The substrate of side wall both sides is formed bowl-shape groove, described side wall and the first gross thickness sacrificing side wall and makes institute
State bowl-shape recess edge distance in the substrate that extrusion position enters below described grid less than pre-spacing
From；
The the first sacrifice side wall removing segment thickness forms the second sacrifice side wall, bowl-shape recessed described in wet etching
Groove forms sigma connected in star, and wherein, side wall and the second gross thickness sacrificing side wall guarantee described wet etching
Sigma connected in star can be formed after bowl-shape groove；
Remove the second sacrifice side wall, filling semiconductor material in described sigma connected in star.
Method the most according to claim 1, it is characterised in that described formation the first sacrifice around side wall
Side wall includes:
The material layer sacrificing side wall is formed at described grid and side wall surface；
Carry out back carving to the material layer of described sacrifice side wall, form the first sacrifice side wall.
Method the most according to claim 1, it is characterised in that the described first material sacrificing side wall is non-
Brilliant carbon.
Method the most according to claim 2, it is characterised in that the formation of the material layer of described sacrifice side wall
Method is plasma activated chemical vapour deposition, ion evaporation sedimentation or sputtering method.
Method the most according to claim 3, it is characterised in that remove the first sacrifice of described segment thickness
It is ashing that side wall and second sacrifices the method for side wall.
Method the most according to claim 1, it is characterised in that described preset distance is 1nm.
Method the most according to claim 1, it is characterised in that described semi-conducting material be germanium silicon material or
Carbofrax material.
Method the most according to claim 1, it is characterised in that described side wall is single layer structure or lamination knot
Structure.
Method the most according to claim 1, it is characterised in that described grid is the grid in front grid technique；
Or, for the dummy grid in rear grid technique.
10. the method determining grid ambient side wall thickness, it is characterised in that including:
The method described in any one of claim 1-9 is utilized to form transistor；
During forming transistor:
Obtain the first sacrifice side wall and the gross thickness of side wall formed, be the first measured value；
Set the thickness that should form total side wall around grid as first object value, according to described first measured value
The thickness of the first sacrifice side wall that should remove is determined with described first object value；
According to the thickness of the should remove the first sacrifice side wall determined, it is removed the first sacrificial of segment thickness
The step of domestic animal side wall, after forming the second sacrifice side wall, obtains the second sacrifice side wall and gross thickness of side wall,
It it is the second measured value；
Obtain the second measured value and the difference of first object value；
Redefining according to described difference and should forming the thickness of total side wall around grid is the second desired value.
11. methods according to claim 10, it is characterised in that described substrate is divided into device region and measurement zone,
Described device region is the region being actually formed device over the substrate, and described measurement zone is over the substrate
For the region measured；
The transistor formed on described substrate is arranged in array, and described transistor is formed at described measurement zone.
12. methods according to claim 10, it is characterised in that described according to the first measured value with described
One desired value determines that the step of the thickness of the should remove first sacrifice side wall includes:
The difference of the first measured value and described first object value is the thickness of the first sacrifice side wall that should remove.
13. methods according to claim 10, it is characterised in that determine the method bag of described second desired value
Include:
When described second measured value is less than first object value, the second desired value=first object value+described second
Measured value and the difference of first object value；
When described second measured value is more than first object value, the second desired value=first object value-described the
Two measured values and the difference of first object value.
14. methods according to claim 10, it is characterised in that the acquisition methods of described first measured value is:
Use optical feature dimension to measure device measuring first and sacrifice the gross thickness of side wall and side wall, or, when
When side wall is definite value, uses optical feature dimension to measure device measuring first and sacrifice the thickness of side wall.
15. methods according to claim 10, it is characterised in that the acquisition methods of described second measured value is:
Use optical feature dimension to measure device measuring second and sacrifice the gross thickness of side wall and side wall, or, when
When side wall is definite value, uses optical feature dimension to measure device measuring second and sacrifice the thickness of side wall.
The manufacture method of 16. 1 kinds of transistors, it is characterised in that including:
Substrate is provided；
Substrate is formed grid；
Forming side wall around described grid, the thickness of described side wall is described in any one of claim 10～15
The thickness of total side wall that method determines；
Form source electrode, drain electrode.
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| CN101743627A (en) * | 2007-03-30 | 2010-06-16 | 英特尔公司 | Methods of forming improved epi fill on narrow isolation bounded source/drain regions and structures formed thereby |
| CN102810482A (en) * | 2011-06-02 | 2012-12-05 | 中芯国际集成电路制造(北京)有限公司 | Method for manufacturing semiconductor devices |
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| CN102810482A (en) * | 2011-06-02 | 2012-12-05 | 中芯国际集成电路制造(北京)有限公司 | Method for manufacturing semiconductor devices |
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