CN104716168B - Semiconductor devices with recombination region - Google Patents

Semiconductor devices with recombination region Download PDF

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Publication number
CN104716168B
CN104716168B CN201410754510.8A CN201410754510A CN104716168B CN 104716168 B CN104716168 B CN 104716168B CN 201410754510 A CN201410754510 A CN 201410754510A CN 104716168 B CN104716168 B CN 104716168B
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semiconductor devices
drift region
raceway groove
region band
conduction type
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CN104716168A (en
Inventor
R.巴布尔斯克
H.许斯肯
P.伊尔西格勒
J.G.拉文
H-J.舒尔策
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Infineon Technologies AG
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Infineon Technologies AG
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Abstract

The present invention relates to the semiconductor devices with recombination region.Semiconductor devices includes the pn-junction between drift region band and charge carrier transport area in the semiconductor body.It accesses raceway groove and long-lasting electric charge carrier path is provided, the long-lasting electric charge carrier path is connected drift region band with recombination region by the Disengagement zone between drift region band and recombination region.It accesses raceway groove and adjusts the plasma density in drift region band and recombination region.

Description

Semiconductor devices with recombination region
Background technology
In semiconductor devices as semiconductor diode, IGFET(Isolated-gate field effect transistor (IGFET))And IGBT(Insulated gate bipolar Transistor)Forward bias pn-junction at, mobile charge carrier fills semiconductor region in the both sides of pn-junction.In these areas It is at least one to be formed with the drift region band along direction of current flow sizable extension and rather low impurity concentration In the case of, electric charge carrier forms electric charge carrier plasma.It is anti-when pn-junction is switched to reverse bias from forward bias Electric charge carrier plasma is removed from drift region band to restoring current.Reverse recovery current facilitates the dynamic of semiconductor devices Handoff loss.Semiconductor devices with improved device property is desirably provided.
Invention content
Embodiment is related to including the semiconductor devices of pn-junction, and the pn-junction is in the semiconductor body in charge carrier transport Between area and drift region band.Access raceway groove(access channel)Long-lasting electric charge carrier path, the long-lasting electric charge are provided Drift region band is connect by carrier path by the Disengagement zone between drift region band and recombination region with recombination region.
Those skilled in the art are by reading the following detailed description and by checking that attached drawing will recognize additional spy It seeks peace advantage.
Description of the drawings
Attached drawing is included to provide further understanding and being combined in this specification and form the explanation for the present invention A part for book.Attached drawing illustrates the embodiment of the present invention and together with the description principle used to explain the present invention.The present invention's Other embodiments and expected advantage will be easy to be fully realized for various reasons, because they become more preferably to manage by reference to the following detailed description Solution.
Figure 1A is the schematic cross of a part for the semiconductor devices with pn-junction of the various aspects for illustrated embodiment Section view.
Figure 1B is regarding with the schematic cross-section of a part for the relevant semiconductor devices of vertical pn-junction according to embodiment Figure.
Fig. 1 C are regarded according to the schematic cross-section of embodiment and the part of the relevant semiconductor devices of horizontal pn-junction Figure.
Fig. 2A is according to embodiment and the semiconductor diode relevant semiconductor device for carrying desaturation unit in front side The schematic cross-sectional view of a part for part.
Fig. 2 B are according to embodiment and the semiconductor diode relevant semiconductor device for carrying desaturation unit in rear side The schematic cross-sectional view of a part for part.
Fig. 2 C are according to embodiment and the semiconductor diode phase for both carrying desaturation unit in front side and rear side The schematic cross-sectional view of a part for the semiconductor devices of pass.
Fig. 2 D are two pole of semiconductor with the desaturation unit with the fill part including being electrically connected according to embodiment Manage the schematic cross-sectional view of a part for relevant semiconductor devices.
Fig. 2 E be according to embodiment with using the semiconductor diode of the desaturation unit of load electrode relevant The schematic cross-sectional view of a part for semiconductor devices.
It is that Fig. 2 F are foundation further embodiment relevant partly with semiconductor diode that is carrying desaturation unit in front side The schematic cross-sectional view of a part for conductor device.
Fig. 3 A are the schematic cross-sectional views with a part for the relevant semiconductor devices of IGFET according to embodiment.
Fig. 3 B are the schematic cross-sectional views with a part for the relevant semiconductor devices of IGBT according to embodiment.
Fig. 3 C are according to embodiment and RC-IGBT(Reverse-conducting IGBT)A part for relevant semiconductor devices is shown Meaning property viewgraph of cross-section.
Fig. 4 A are the semiconductors of the semiconductor diode of the equally distributed compact desaturation unit of offer according to embodiment The diagrammatic plan view of main body.
Fig. 4 B are the semiconductor bodies of the semiconductor diode of the desaturation unit of the offer shape of stripes according to embodiment Diagrammatic plan view.
Fig. 4 C are showing for the semiconductor body of the semiconductor diode of the offer class grid desaturation unit according to embodiment Meaning property plan view.
Fig. 4 D are partly leading for the semiconductor diode of the compact desaturation unit of the offer uneven distribution according to embodiment The diagrammatic plan view of phosphor bodies.
Fig. 5 A are the semiconductor bodies of the semiconductor devices comprising equally distributed compact desaturation and transistor unit Diagrammatic plan view.
Fig. 5 B are the signals of the semiconductor body of the semiconductor devices of the transistor comprising regular arrangement and desaturation unit Property plan view.
Fig. 5 C are the desaturation unit comprising mesh shape and the transistor unit that is formed in the mesh of desaturation unit Semiconductor devices semiconductor body diagrammatic plan view.
Fig. 5 D are half of the semiconductor devices comprising class framework desaturation unit and equally distributed tight transistor unit The diagrammatic plan view of conductor main body.
Specific implementation mode
In detailed description below referring to the attached drawing, attached drawing forms part of it and wherein by graphic Mode shows that the particular embodiment of the present invention can be put into practice wherein.It is understood that and other embodiments may be used and can To carry out the change of structure or logic without departing from the scope of the present invention.Such as the feature that one embodiment is illustrated or is described It can be used in other embodiments or be used together with other embodiments to generate another embodiment.It is intended that this hair Bright includes such modifications and changes.Example is described using specific language, is not construed as limiting appended right It is required that range.Attached drawing is disproportionate and only for graphic purpose.For clarity, identical element is in different drawings It is referred to by corresponding reference marker, if without in addition stating.
Term " having ", " containing ", "comprising", " comprising " etc. be it is opening, and term instruction statement structure, Elements or features occur but without excluding additional elements or features.Article " one(a)", " one(an)" and " should (the)" be intended to comprising plural number and odd number, unless the context clearly dictates otherwise.
Term " electrical connection " describes the lasting low ohm connection between the element of electrical connection, such as in the element being related to Between be in direct contact or via metal and/or high doping semiconductor low ohm connection.Term " being electrically coupled " includes adaptation The element being electrically coupled is may be provided in one or more intervening elements of signal transmission(Such as it is controllable with temporarily Low ohm connection is provided in one state and the element of high ohm electrically decoupling is provided in the second state)Between.
Attached drawing illustrates relative doping concentration by instruction with doping type " n " or " p " adjacent "-" or "+".Such as “n-" indicate more lower than the doping concentration of " n " doped region doping concentration and " n+" doped region has and more higher than " n " doped region mix Miscellaneous concentration.The doped region of identical relative doping concentration need not absolute doping concentration having the same.Such as two different " n " Doped region can have identical or different absolute doping concentration.
Figure 1A shows a part for semiconductor devices 500, the semiconductor devices 500 can be semiconductor diode, IGFET(For example include the FET with metal gates in common meaning(Field-effect transistor)With with nonmetallic grid The MOSFET of FET(Mos field effect transistor))Or IGBT(Such as RB-IGBT(Reverse blocking IGBT)Or RC-IGBT(Reverse-conducting IGBT)).The semiconductor body 100 of semiconductor devices 500 is from single-crystal semiconductor material(For example, conduct Example, silicon(Si), silicon carbide(SiC), germanium(Ge), Si Ge crystal(SiGe), gallium nitride(GaN)Or GaAs(GaAs))It provides.
Pn-junction 171 is formed in semiconductor body 100 between charge carrier transport area 115 and drift region band 120, Middle charge carrier transport area 115 with the first conduction type and drift region band 120 with the first conduction type, described first Conduction type is the opposite of the second conduction type.In embodiment illustrated, the first conduction type is N-shaped and second is conductive Type is p-type.According to other embodiments, the first conduction type can be p-type and the second conduction type can be N-shaped.
Charge carrier transport area 115 can be the anode region of semiconductor diode or the electric current stream that control passes through IGBT The body region of the IGFET units of dynamic IGFET units or IGFET.
Impurity concentration in drift region band 120 can be less than the impurity concentration in charge carrier transport area 115 with So that depletion region predominantly extends into drift region band 120 from pn-junction 171 when 171 reverse bias of pn-junction.Foundation embodiment, Mean impurity concentration in charge carrier transport area 115 be impurity concentration in drift region band 120 at least ten times.As Example, the impurity concentration in drift region band 120 can be at most 1 × 1015(1E15)cm-3, such as at most 1 × 1014(1E14) cm-3
Semiconductor devices 500 is further included with pn-junction 171 every the recombination region of a distance 190.Table in recombination region 190 At face or even on the surface of recombination region 190 hereinafter, recombination rate(Recombination velocity)Than at typical semiconductor-insulator interface Recombination rate higher.Such as the recombination velocity at perfect silicon-silicon oxide interface in 30cm/s to 100cm/s in the range of. At the more highdensity trap of silicon-silicon oxide interface, recombination velocity can reach up at most 104The value of cm/s.As for Dai Di, according to embodiment, the surface recombination rate or surface recombination velocity (S.R.V.) of recombination region 190 are the charges in semiconductor body 100 At least the 0.5% of the saturated velocity of carrier.It is based in the situation of silicon in semiconductor body 100, surface recombination velocity (S.R.V.) can be At least 5 × 104(5E04) cm/s, for example it is more than 1 × 105(1E05)Cm/s or at least 1 × 106(1E06)cm/s.
It recombination region 190 can be by metal or metallic compound(Such as conductive metal silicide, as CoSi2、HfSi2、 MoSi2、NiSi2、PdSi2、PtSi2、TaSi2、TiSi2、WSi2Or ZrSi2)Composition contains the metal or metallic compound And can have high-temperature stability so that recombination region 190 can in the early stage of manufacturing process the stage be provided.According to other Embodiment, recombination region 190 can be made of aluminium or contain aluminium, such as Al, AlSi or AlSiCu, can be in an economical manner It is deposited and is etched.
According to further embodiment, recombination region 190 is the single-crystal semiconductor material of deformation, the single crystal semiconductor of the deformation Material such as by deposit amorphous, monocrystalline, crystallite or polycrystalline semiconductor material or by by impurity with high implantation dosage and/or Implantation Energy is injected into semiconductor body 100 to provide, wherein controlling subsequent manufacturing process to ensure that impaired crystal exists Desired composite attribute is maintained in the semiconductor devices 500 of completion.
Recombination region 190 can with conductive structure dielectric insulation or can not with conductive structure dielectric insulation, it is described to lead Electric structure is electrically connected to the face terminals of semiconductor devices 500.According to embodiment, recombination region 190 can be floating.
Disengagement zone 195 spatially detaches recombination region 190 with drift region band 120 in semiconductor body 100.Disengagement zone 195 can form homojunction or hetero-junctions with drift region band 120.According to embodiment, Disengagement zone 195 and drift region band 120 have Complementary conductivity type.According to another embodiment, 120 conduction type having the same of Disengagement zone 195 and drift region band, wherein Average net impurity concentration in Disengagement zone 195 can be at least high as the impurity concentration in drift region band 120.According to implementation Example, the average net impurity concentration in Disengagement zone 195 are at least twice of the mean impurity concentration in drift region band 120, example As at least ten times.Impurity concentration in Disengagement zone 195 can be in the range of the impurity concentration in charge carrier transport area 115 It is interior or identical as the impurity concentration in charge carrier transport area 115.
Persistently recombination region 190 is structurally joining together with drift region band 120 by Disengagement zone 195 by access raceway groove 184, and Highly conductive path is provided for the minority charge carriers in Disengagement zone 195.For example for p-type Disengagement zone 195, access raceway groove 184 provide conducting channel for electronics, and for N-shaped Disengagement zone 195, access raceway groove 184 provides conductive path for hole.
Persistently access raceway groove 184 can be the doped channel containing fixed impurity, and the fixed impurity has permission respective The type of the electric current flowing of electric charge carrier.It can contain alms giver's original such as the N-shaped access raceway groove 184 of p-type Disengagement zone 195 Son.It can contain acceptor atom for the p-type access raceway groove 184 of N-shaped Disengagement zone 195.Donor atom or acceptor atom can mistakes Compensate the Background impurity concentration of the conduction type of Disengagement zone 195.
According to further embodiment, persistently accessing raceway groove 184 can have and 195 phase of Disengagement zone about fixed foreign atom With conduction type, and adjacent field structure contains fixed charge carrier, the electric field of the fixed charge carrier along The mobile minority charge carriers of Disengagement zone 195, wherein transoid ditch are locally accumulated in inversion channel with the interface of field structure Road provides conductive path for respective charge carrier type.For example, the positive fixed charge carrier in adjacent field structure Electronics can be accumulated in inversion channel, the inversion channel abuts separation structure 180 and is electricity in p-type Disengagement zone 195 Son provides path.Negative fixed charge carrier in adjacent field structure can accumulate hole in inversion channel, described Inversion channel abuts field structure and provides path in the N-shaped Disengagement zone 195 of adjacent field structure for hole.In each situation In, respective inversion channel forms access raceway groove 184, to be a type between drift region band 120 and recombination region 190 Electric charge carrier provides lasting conductive path.
When 171 forward bias of pn-junction, charge carrier transport area 115 is by p-type electric charge carrier(Hole)It is injected into Drift region band 120 and N-shaped electric charge carrier(Electronics)It is injected into from opposite side into drift region band 120.The charge of injection carries Stream forms electric charge carrier plasma in drift region band 120, and the electric charge carrier plasma is in semiconductor diode Situation in ensure low forward resistance or ensure low ON state electricity in as the situation of IGFET or the semiconductor switch device of IGBT Resistance.When pn-junction 171 is switched to reverse bias from forward bias, reverse recovery current removes electric charge carrier plasma, The reverse recovery loss of middle generation facilitates the handoff loss of semiconductor devices 500.
By the way that drift region band 120 to be connect with recombination region 190, access raceway groove 184 reduces the charge in drift region band 120 Carrier plasma density.When 171 forward bias of pn-junction, Disengagement zone 195 and charge carrier transport area 115 as to The potential barrier of electronics in electric charge carrier plasma is effective so that the efficiency of recombination region 190 is predominantly limited by access The characteristic of raceway groove 184.For the pn-junction 171 of forward bias, potential barrier can be quite high to minimize recombination region 190 to semiconductor device The influence of the characteristic of part 500.Disengagement zone 195 can be doped enough to height effective recombination rate so that at recombination region 190 Only by the minority charge carriers current limit by accessing raceway groove 184.
Figure 1B is related to the transversal device with pn-junction 171, and the pn-junction 171 is in the first surface with semiconductor body 100 Extend in 101 vertical planes.Charge carrier transport area 115, drift region band 120 and Disengagement zone 195 can abut directly against First surface 101.Separation structure 180(Such as shallow trench insulation)Charge carrier transport area 115 and Disengagement zone 195 can be divided From.N-shaped access raceway groove 184 can be between pn-junction 171 and recombination region 190 Disengagement zone 195 upright projection in semiconductor It is formed at the first surface 101 of main body 100.
Fig. 1 C are related to the vertical devices with pn-junction 171, and the pn-junction 171 is in the first surface with semiconductor body 100 It is formed in 101 parallel planes.Charge carrier transport area 115 and Disengagement zone 195 can be in first surface 101 and pn-junctions It is formed between 171.Separation structure 180 can be extended downwardly at least from first surface 101 to pn-junction 171.It recombination region 190 can be straight It is adjoining to connect separation structure 180.Separation structure 180 can contain fixed charge carrier, the fixed charge carrier along with The interface of separation structure 180 induces the access raceway groove 184 of minority charge carriers in Disengagement zone 195.
As an alternative or in addition, access raceway groove 184 can contain the conduction type opposite with the conduction type of Disengagement zone 195 Fixed impurity.Donor atom and/or acceptor atom can be after forming the slot for separation structure 180 and in filling for dividing It is introduced into from solid phase for example, by following manner before the slot of structure 180:Plasma deposition, to be more than with normal slope The ion beam mutation of 3.5 degree of implant angle, epitaxial growth or to external diffusion.
Graphic semiconductor devices is vertical semiconductor diode 501 in fig. 2, the vertical semiconductor diode 501 The anode region 115a of drift region band 120 and the second conduction type with the first conduction type.Anode region 115a can be used as figure The charge carrier transport area 115 of 1A to 1C is effective.Anode region 115a and the formation of drift region band 120 and semiconductor body The parallel pn-junction 171 of 100 first surface 101.The normal of first surface 101 define vertical direction and with first surface 101 Parallel direction is horizontal direction.
The heavy doping pedestal layer of first conduction type(pedestal layer)130 drift region band 120 and with the first table It is formed between the opposite second surface 102 in face 101.Mean impurity concentration in drift region band 120 as example can 1 × 1012(1E12)cm-3With 1 × 1015(1E15)cm-3Between.Impurity concentration in pedestal layer 130 can be at least 5 as example ×1017(5E17)cm-3.Distance between first surface 101 and second surface 102 is limited by semiconductor diode 501 and is advised Surely the nominal breakdown voltage that is used for and 45 μm, such as at least 90 μm can be more than.It is right about the material of semiconductor body 100 The description of the semiconductor devices 500 of Figure 1A is referred to.
First load electrode 310 is disposed at the side of first surface 101 and abuts directly against first surface 101 and anode Area 115a.First load electrode 310 can form the anode terminal A of semiconductor diode 501 or can be electrically connected or thermocouple Close the anode terminal A of semiconductor diode 501.Second load electrode 320 abuts directly against second surface 102 and pedestal layer 130. Second load electrode 320 can form cathode terminal K or can be electrically connected or be electrically coupled to cathode terminal K.
Each of first load electrode 310 and the second load electrode 320 can be made of materials described below or containing following Material:As main(It is one or more)Ingredient, aluminium(Al), copper(Cu)Or the alloy of aluminium or copper(Such as AlSi, AlCu or AlSiCu).According to other embodiments, at least one of the first load electrode 310 and the second load electrode 320 can contain: Nickel(Ni), titanium(Ti), tungsten(W), silver(Ag), gold(Au), platinum(Pt), and/or palladium(Pd), as main(It is one or more)At Point.Such as first at least one of load electrode 310 and the second load electrode 320 can include two or more sublayers, Wherein each sublayer contains one or more of Ni, Ti, Ag, Au, Pt, W and Pd as main(It is one or more)Ingredient, Such as silicide, nitride and/or alloy.
Semiconductor diode 501 can include that semiconductor body 100 can be extended into from first surface 101 downwards at least To one or more desaturation cells Ds C1A, DC1B of pn-junction 171.
Each desaturation cells D C1A, DC1B include be buried in semiconductor body 100 and with pn-junction 171 every one section away from Recombination region 190 from arrangement.It can be with anode region 115a with identical with the Disengagement zone 195 that pn-junction 171 detaches by recombination region 190 Impurity concentration.
Unit insulator 188 can be by 310 dielectric insulation of recombination region 190 and the first load electrode.Unit insulator 188 It can be between first surface 101 and recombination region 190 or at least some parts are above first surface 101.From first surface 101 It can includes downwards fill part 189 and insulation at least to the separation structure 180 of pn-junction 171 to extend into semiconductor body 100 Body portion 185, the insulator portion 185 insulate the adjacent material of fill part 189 and semiconductor body 100.
Insulator portion 185 can include one of such as dielectric substance of silica, silicon oxynitride or silicon nitride or Multiple sublayers.Fill part 189 can include one or more dielectric substances, intrinsic material or conductive material, example Such as the polysilicon of doping.Can be floating or can be electrically connected to each other in the conductive fill part 189 of desaturation cells D C1A, DC1B.
According to embodiment, desaturation cells D C1A, DC1B can be rotational symmetry about vertical axis of symmetry.For example it goes to satisfy Lateral cross region with cells D C1A, DC1B can be polygon(Such as with or without radiused corners rectangular or Hexagon)Or circle, wherein fill part 189 can surround recombination region 190 in all horizontal directions.According to other implementations Example, desaturation cells D C1A, DC1B is the striped for the active region that semiconductor diode 501 is extended through in horizontal direction, One pair of which separation structure 180 extends on the opposite side of the recombination region of shape of stripes 190.
Desaturation cells D C1A, DC1B includes lasting access raceway groove 184, and the lasting access raceway groove 184 is by recombination region 190 It is structurally joining together by Disengagement zone 195 with drift region band 120 and is provided for the minority charge carriers in Disengagement zone 195 Highly conductive path.Access raceway groove 184 can abut directly against recombination region 190.According to other embodiments, the first conduction type it is heavily doped Access raceway groove 184 can be structurally joining together by miscellaneous bonding pad with recombination region 190 respectively.
In the forward bias pattern of pn-junction 171, positive voltage is applied to anode terminal A and negative voltage is applied in To cathode terminal K.Hole is injected into anode region 115a and by the pn-junction of forward bias 171 by the first load electrode 310 Into drift region band 120.Electron injection is entered drift region band 120 by the second load electrode 320 by pedestal layer 130.It is drifting about The High Density Charge carrier plasma generated in zone 120 ensures the low forward resistance of semiconductor diode 501.
Access raceway groove 184 along separation structure 180 from drift region band 120 to respective recombination region 190 is in 190 He of recombination region It is to electronically form conductive path between drift region band 120.The charge that high surface recombination rate at recombination region 190 reduces electronics carries Flow the sub- service life.Thus, access raceway groove 184 reduces the number of the electronics in drift region band 120 and controls electric charge carrier etc. Plasma density.
When semiconductor diode 501 is switched to reverse bias from forward bias, reverse recovery charge ratio does not have desaturation list First DC1A, DC1B's is lower.Semiconductor diode 501 faster and with lower reverse recovery current reaches blocking state.Due to multiple Close area 190 and 310 permanent insulation of the first load electrode, desaturation cells D C1A, DC1B can bear high blocking voltage and Short circuit condition does not occur for the transition period to blocking mode.
It can pass through drift region band 120 by the charge flowing of the access raceway groove 184 of desaturation cells D C1A, DC1B Be saturated under forward current --- the forward current is less than, at or above in the tables of data for the device being related to repetition pulse Load current such as periodic load electric current(As for example appeared in rectifier or half-bridge application)Defined maximum impulse load Electric current --- so that opposite desaturation efficiency can be suitable for different application requirements.For semiconductor diode, maximum arteries and veins It can be maximum diode pulse current I to rush load currentFPulsOr maximum mean on-state current IFAVM.Until saturation, flowing is logical The number for crossing the electric charge carrier for the access raceway groove 184 being related to depends on electric charge carrier plasma density and with forward direction Electric current or ON state current and increase.More than saturation, the electronic current by accessing raceway groove 184 only changes a little.
It is saturated below maximum impulse load current if the charge by accessing raceway groove 184 is flowed, opposite desaturation Efficiency is low for high current and accesses raceway groove 184 in the forward current or ON state current close to maximum impulse load current It is lower to allow quite high electric charge carrier plasma density.Opposite desaturation efficiency is turning off in identical desaturation unit Period increases with forward current is reduced so that transition stage of the desaturation efficiency between forward condition and blocking state In be high.
If by accessing the charge flowing of raceway groove 184 in maximum impulse load current or more than maximum impulse load current It but is below the overcurrent of permission(Such as the surge current of permission)And be saturated, then with respect to desaturation efficiency to until maximum rated The operation of value remains height, and the low switching within the scope of whole operation is caused to be lost.Meanwhile for the high charge that overcurrent generates Carrier density provides high surge current durability(ruggedness).
According to another embodiment, semiconductor diode 501 includes to be less than maximum arteries and veins for reducing carrying for handoff loss It rushes the first desaturation cells D C1A of the desaturation electric current of load current and surpasses for improving carrying for surge current durability Cross the second desaturation cells D C1B of the desaturation electric current of maximum impulse load current.
According to further embodiment, semiconductor diode includes desaturation unit, and the N-shaped of the desaturation unit accesses ditch Contain deep grade alms giver as selenium in road(Se)Or sulphur(S)Atom.Deep grade alms giver is only in a certain minimum temperature or in a certain minimum temperature Fang Zuowei alms giver is effective.Desaturation unit containing Se and/or S atom is only in instruction localized hyperthermia condition(Such as by The electric current silk occurred during dynamic avalanche in semiconductor diode 501(current filament)Caused by focus incident) Temperature at start reduce electric charge carrier plasma density.Desaturation unit containing S and/or Se can be with partial cancellation warm Point event.
Semiconductor diode 501 can include the different types of desaturation unit based on different dopant types.
Access raceway groove 184 can uniquely be formed at the side of the separation structure 180 of recombination region 190 or can edge It includes further part separation structure 180, and wherein unit insulator 188 can include section, the section block along from The access raceway groove 184 that the outer edge for the separation structure 180 that recombination region 190 is avoided extends leaves unused(idle)Part 184x so that Idle part 184x does not negatively affect device parameters.As an alternative or in addition, the second conduction type heavy doping channel stop Area can extend into anode region 115a along the outer edge of separation structure 180 from first surface 101.As an alternative or in addition, from The foreign section for the insulator portion 185 that recombination region 190 is avoided can be thicker to the inner section of recombination region 190 with specific surface.
Any electrical contact of the current potential of conductive fill part 189 for switching separation structure 180 or any control structure Missing significantly reduce manufacture complexity and promote even in such as Fig. 2 B it is graphic it is opposite with first surface 101 partly The implementation of desaturation cells D C at the rear side of conductor main body 100.
The semiconductor diode 502 of Fig. 2 B includes the desaturation cells D C being formed on the cathode side of device or on rear side.
The separation structure 180 of desaturation cells D C extends into half from the second surface 102 being directed towards cathode electrode Conductor main body 100 can include filling downwards at least to the homojunction 172 between drift region band 120 and pedestal layer 130 Part 189 and the insulator portion 185 that the adjacent material of fill part 189 and semiconductor body 100 insulate.Fill part 189 can insulate or can be electrically connected with the second load electrode 320 with the second load electrode 320.The conductive-type of drift region band 120 The Disengagement zone 195 of type detaches recombination region 190 with drift region band 120.About further details, the description of Fig. 2A is joined It examines.
For the minority charge carriers in Disengagement zone 195, persistently accessing raceway groove 184 directly will by Disengagement zone 195 Drift region band 120 and recombination region 190 are structurally joining together or by the heavy doping bonding pad of the second conduction type by drift region band 120 are structurally joining together with recombination region 190.Access raceway groove 184 provides highly conductive path by N-shaped Disengagement zone 195 for hole.
P-type, which accesses raceway groove 184, can contain fixed acceptor atom, and the fixed acceptor atom can be defined with overcompensation and be detached The N-shaped Background impurity concentration in area 195.
According to further embodiment, persistently accessing raceway groove 184 can have and 195 phase of Disengagement zone about fixed foreign atom Same conduction type, and separation structure 180 can contain negative fixed charge carrier, in adjacent separation structure 180 N-shaped Disengagement zone inversion channel in accumulate hole.It is hole between drift region band 120 and recombination region 190 to access raceway groove 184 Form lasting conductive path.
Since for low ohm metal to semiconductor contact, the impurity concentration ratio in n-type semiconductor portion is partly led in p-type Impurity concentration higher in body portion, so cathode emitter efficiency is typically than anode efficiency higher.Therefore, on the cathode side Desaturation cells D C be that height is efficient.It can ignore for reducing carrier lifetime using increased Leakage Current as cost Alternative technology, such as by platinum(Pt)Atoms permeating enters semiconductor body 100.
Graphic semiconductor diode 503 combines the desaturation unit on front side as described in reference to figure 2A in fig. 2 c The DC1 and desaturation cells D C2 on rear side as described in reference to figure 2B.Desaturation cells D C1 on front side can with Desaturation cells D C2 on rear side is in size, population density(population density)And/or the internal upper difference of configuration.
Different from the separation structure 180 of the semiconductor diode 501 in Fig. 2A, graphic semiconductor diode in figure 2d The separation structure 180 of desaturation cells D C in 504 includes that may be electrically coupled to for example conducting oneself with dignity for the first load electrode 310 The conductive fill part 189 of doped polycrystalline silicon materials is effective so that separation structure 180 can be made as anode electrode It is effective for collocation structure.
The electronics of electric charge carrier plasma is directly released into the first load by the semiconductor diode 505 in Fig. 2 E Electrode 310 is to reduce the plasma density before the 115a of anode region.Forward drop increases under low forward current, institute State the free charge of less dense of the low forward current instruction before the 115a of anode region and low emitter efficiency.For high positive Electric current, forward drop reduces, because of high-caliber free charge carrier and emitter efficiency occurred frequently.Semiconductor diode 505 The injection dependence of the emitter efficiency of reversion is shown:It is inefficient and efficient under high forward current under low forward current Rate, however tradition p doping controlled diode shows emitter efficiency with increasing due to more compound in the 115a of anode region Add the strong attenuation of forward current.In blocking mode, access raceway groove 184 can be completely exhausted.
Fig. 2 F diagrams Disengagement zone 195 has the embodiment of the conduction type of drift region band 120.In this case, ditch is accessed Road 184 is hole channel, such as the p doped regions band along separation structure 180 or the inversion channel that is formed by electric field, the electric field It is generated by separation structure 180.
Graphic semiconductor devices is the vertical IGFET 511 with transistor unit TC, the transistor in figure 3 a Unit TC includes the gate electrode 150 being arranged in slot structure, and the slot structure extends into semiconductor master from first surface 101 Body 100.The field plate 160 that slot structure can include or can be not included between gate electrode 150 and second surface 102, Middle field dielectric 202 insulate field plate 160 and gate electrode 150 and semiconductor body 100.Field plate 160 can it is floating or Field plate current potential is may be electrically coupled to, the field plate current potential can be applied to the source potential of source electrode.
Semiconductor body 100 includes the source area 110 for the first conduction type for abutting directly against first surface 101.Body region 115b detaches source area 110 with drift region band 120, the charge of semiconductor devices of the body region 115b as Figure 1A to 1C Carrier transport area 115 is effective.Contact structures 305 extend into semiconductor by the opening in dielectric medium structure 220 Main body 100 by the first load electrode 310 to be electrically connected to both source area 110 and body region 115b.
First load electrode 310 can be the source terminal S of semiconductor devices 500 or can be electrically coupled or be electrically connected to The source terminal S of semiconductor devices 500.Second load electrode 320 can be drain terminal D or may be electrically coupled to drain electrode end Sub- D.The gate electrode 150 of transistor unit TC is electrically coupled to each other and can be electrically connected or be electrically coupled to gate terminal G.
As can be interspersed in reference to the desaturation cells D C described in figure 2A semiconductor devices 500 active region 610 it Among interior transistor unit TC.According to other embodiments, desaturation cells D C is main or uniquely along in 610 He of active region Transition region 650 between fringe region 690 and formed, the fringe region 690 is without any transistor unit and directly adjacent The outer surface of the semiconductor body 100 of first surface 101 and second surface 102 is connect in succession.
According to embodiment, desaturation cells D C, which may be embodied in structure, to be connected recombination region 190 and accesses the of raceway groove 184 The bonding pad 182 of one conduction type.Bonding pad 182 can correspond to source area 110 about shape and impurity dose.Recombination region 190 can along extend into semiconductor body 100 and result from filler ditch dielectric medium structure 220 protrusion 221 Formed, the filler ditch can together with the contact groove for contact structures 305 with the material of dielectric medium structure 220 come shape At.Protrusion 221 can extend into Disengagement zone 195 and can have depth identical with the ditch for contact structures 305. According to other embodiments, protrusion 221 can extend deeper into semiconductor body 100 than contact structures 305 or with multiple The table top for closing area 190 is not higher than the table top with source area 110 so that the drift more closer than contact structures 305 of recombination region 190 Zone 120.
It is close that desaturation cells D C reduces the plasma generated in drift region band 120 in the ON state of transistor unit TC Spend and improve the switching characteristic of IGFET 511.Tradeoff between quiescent dissipation and dynamic loss can be modified and fit Together in application requirement.
By the charge flowing of the access raceway groove 184 of desaturation cells D C can by being less than of drift region band 120, locate In or more than being saturated under the drain current of maximum impulse load current specified in the data sheet for the IGFET 511 being related to, with Opposite desaturation efficiency is enable to be suitable for the different application requirements being such as described in detail about Fig. 2A.It is maximum for IGFET Pulse load electric current is pulse drain current ID,puls
In figure 3b, graphic semiconductor devices is IGBT 512 of the body region with 115b with transistor unit TC, The body region band 115b is effective as charge carrier transport area 115 in the sense that Figure 1A to 1C.It can be electrically connected Emitter terminal E can be formed or can be by thermocouple by being connected to the first load electrode 310 of both source area 110 and body region 115b Close or be electrically connected to emitter terminal E.Pedestal layer 130 has the conduction type opposite with the conduction type of drift region band 120, than It is p-type such as in the situation of graphic n-channel IGBT.Collection can be formed by abutting directly against the second load electrode 320 of pedestal layer 130 Electrode terminal C may be electrically coupled to collector terminal C.The gate electrode 150 of transistor unit TC and by gate electrode 150 It can be disposed in extend into from first surface 101 with the gate-dielectric 205 of 100 dielectric insulation of semiconductor body and partly lead Phosphor bodies 100 are downwards at least in the slot of pn-junction 171.Gate electrode 150 can be electrically connected to each other and can be electrically coupled or It is electrically connected to gate terminal G.
Body region 115b can be the striped extended along horizontal direction.It is at least one for each transistor unit TC Gate electrode 150 extends on a cross side of body region 115b.Gate electrode 150 is disposed in embodiment illustrated On the opposite side of body region 115b.Other embodiments can provide the transistor list with rotational symmetry lateral cross region Member, wherein transverse cross-sectional area can be polygon, such as the rectangular or hexagon of with or without radiused corners, round or ellipse Circle.
IGBT 512 includes desaturation cells D C as described above.Transistor unit TC's and desaturation cells D C is transversal It face region can be with cross-sectional shape having the same.According to further embodiment, desaturation cells D C and transistor unit TC tools There are identical cross-sectional shape and region.Idle area 175 can be formed between desaturation cells D C and transistor unit TC. It idle area 175 can be with the conduction type of Disengagement zone 181 and body region 115b.
Dielectric medium structure 220 can abut directly against first surface 101 and can be by recombination region 190 and the first load electrode 310 and/or be arranged on the surface of the dielectric medium structure 220 opposite with semiconductor body 100 other metal structures insulation.Electricity The conductive structure that dielectric structure 220 can would sit idle for area 175 and be arranged at the side of first surface 101 insulate.
Similar with the IGFET of Fig. 3 A, desaturation cells D C is reduced in the ON state of transistor unit TC in drift region band 120 The plasma density of middle generation and the switching characteristic for improving IGBT 512.
By the charge flowing of the access raceway groove 184 of desaturation cells D C can by being less than of drift region band 120, locate In or more than being saturated under the collector current of maximum impulse load current specified in the data sheet for the IGBT 512 being related to, with Opposite desaturation efficiency is enable to be suitable for the different application requirements being such as described in detail about Fig. 2A.It is maximum for IGBT Pulse load electric current is pulse collector current IC,puls
Fig. 3 C are related to the RC-IGBT 513 with pedestal layer 130, and the pedestal layer 130 includes the of the first conduction type Second zone 132 of one zone 131 and the second conduction type.Second load electrode 320 abuts directly against the first zone 131 and second Both zone 132.Not not having one or some or all of may be electrically coupled to the first load electrode 310 in idle area 175.For Further details refer to the description of IGBT 512 in figure 3b.
RC-IGBT 513 includes integrated fly-wheel diode, and the integrated fly-wheel diode carries:The first of pedestal layer 130 Zone 131 is effective as cathodic region;With the body region 115b for being connected to the first load electrode 310 and(If can apply 's)Idle area 175, is effective as anode region.When the pn-junction 171 between body region 115b and drift region band 120 is reversed RC-IGBT 513 is in forward bias pattern when biasing, and RC-IGBT just thinks that suitable grid potential is applied to grid electricity Electric current is just conducted when pole 150.In back bias mode, the integrated fly-wheel diode of RC-IGBT conducts electric current, no matter it is applied to Voltage at gate electrode 150.
In the back bias mode of RC-IGBT 513, internal pn-junction 171 is forward biased and drift region band 120 It is filled by mobile charge carrier.When RC-IGBT 513 is switched to forward blocking mould from back bias mode or diode mode Electric charge carrier must be discharged from drift region band 120 when formula.The notable portion of desaturation cells D C discharge mobile charge carriers Point.Recombination region 190 does not negatively affect the blocking characteristics of RC-IGBT 513 to the connection of drift region band 120.If semiconductor Device 500 is used as the switch in half-bridge configuration, then can avoid short circuit condition.
By the charge flowing of the access raceway groove 184 of desaturation cells D C can by being less than of drift region band 120, locate In or more than in the data sheet for the RC-IGBT 513 being related to the reversed of maximum impulse load current as defined in backward dioded It is saturated under electric current, so that opposite desaturation efficiency can be suitable for the different application requirements being such as described in detail about Fig. 2A. For the backward dioded of RC-IGBT, maximum impulse load current is diode pulse current IF,puls
Fig. 4 A to 4D are related to the arrangement of the desaturation cells D C in semiconductor diode.
Fig. 4 A show compact desaturation cells D C, and two of which lateral dimension is than the semiconductor master of semiconductor devices 500 The correspondence lateral dimension of the active region 610 of body 100 significantly smaller.Semiconductor body 100 includes active region 610 and edge Region 690, the fringe region 690 is between active region 610 and the outer surface 103 of semiconductor body 100.There is no any sun The fringe region 690 of polar region surround comprising(It is one or more)The active region 610 of anode region.
Compact desaturation cells D C can be disposed in along the diagonal line of rectangular shaped semiconductor main body 100 or come along edge In the row and column of the aturegularaintervals of orientation.Desaturation cells D C can be approximate equivalent.The population density of desaturation cells D C can be with It is uniform across entire active region 610, wherein desaturation cells D C can have equivalent access raceway groove 184.According to real Example is applied, the charge carriers electron current in desaturation cells D C can increase with the distance for being reduced to fringe region.Such as Desaturation cells D C can have different width.Such as the access raceway groove of the desaturation cells D C closer to fringe region 690 184 can be more wider than the access raceway groove 184 of the desaturation cells D C further from fringe region 690.
According to other embodiments, the population density of desaturation cells D C can be in the central part of active region 610 more It is low and finer and close to increase dynamic durability and improve in the outer portion of the active region of adjacent edge region 690 610 Temperature Distribution in the semiconductor device.
Fig. 4 B show the desaturation cells D C of shape of stripes, and the desaturation cells D C of the shape of stripes is with the center of rule To centre distance(Pitch)It is arranged and is directed along one in the outer edge of semiconductor body 100.
Fig. 4 C show the cells D C of the mesh shape of multiple subdivisions with the anode region 115b formed in mesh.Net The size in hole can be uniform across entire active region 610 or can be dropped with the distance for being reduced to fringe region 690 It is low.
Compact desaturation cells D C is arranged in the central part of active region 610 with more low group volume density in fig. 4d And it is arranged with more high population density in the part for the active region 610 for being directed to fringe region 690.
Fig. 5 A to 5D are related to being used for IGFET and IGBT(Including RC-IGBT)Transistor unit TC and desaturation cells D C Arrangement.
Fig. 5 A are related to the transistor unit TC in equally spaced row and column in the pattern of the matroid of rule and go to satisfy With the arrangement of cells D C.Desaturation cells D C and transistor unit TC can be alternatively arranged along every row and along each column. Other than outermost desaturation cells D C and transistor unit TC, each transistor unit TC can abut four desaturation lists First DC and vice versa.The arrangement can be similar to checkerboard pattern, wherein transistor unit TC be assigned to white field and Desaturation cells D C is assigned to black field.According to other embodiments, the outermost row and column of adjacent edge region 690 can wrap Containing desaturation cells D Cs more more than transistor unit TC to support the desaturation of fringe region 690.
Fig. 5 B are related to the transistor unit TC and desaturation cells D C of shape of stripes, can be parallel to semiconductor body One in 100 edge and extend and can be arranged with the pitch of rule.
Fig. 5 C show to be formed the desaturation cells D C of grid, and wherein transistor unit TC is arranged in mesh.Another reality The pattern of reversion can be provided by applying example, and wherein transistor unit forms grid and desaturation unit is formed in the mesh of grid In.
Fig. 5 D show the tight transistor unit TC of the regular arrangement in the central part of active region 610 and are being directed to The class framework desaturation cells D C arranged in the outer portion 619 of the active region 610 of fringe region 690.
The semiconductor devices for manufacturing the embodiment of Fig. 2 B and 2C includes to form drift region band and charge in the semiconductor substrate Carrier transport area, wherein drift region band and charge carrier transport area form pn-junction.Form recombination region and in recombination region and drift Move the Disengagement zone between zone.Form the access raceway groove that long-lasting electric charge carrier path is provided, long-lasting electric charge carrier road Diameter connects recombination region and Disengagement zone.Desaturation unit including recombination region and access raceway groove can be in the front side of semiconductor substrate And/or it is formed at rear side.
Although having illustrated and having described specific embodiment herein, those of ordinary skill in the art will recognize more The embodiment of kind alternative and/or equivalence can replace shown and described specific embodiment without being detached from the present invention Range.This application is intended to cover any adaptation or the change of specific embodiments discussed herein.Therefore it is intended that the hair Bright is limited by claim and its equivalent.

Claims (20)

1. a kind of semiconductor devices, including:
Pn-junction is formed between drift region band and charge carrier transport area in the semiconductor body;
Recombination region;With
Raceway groove is accessed, configuration is shaped as long-lasting electric charge carrier path, and the long-lasting electric charge carrier path passes through in recombination region Disengagement zone between drift region connects recombination region and drift region band.
2. the surface recombination velocity (S.R.V.) of the semiconductor devices of claim 1, wherein composite construction is in the semiconductor body At least the 0.5% of the saturated velocity of electric charge carrier.
3. the surface recombination velocity (S.R.V.) of the semiconductor devices of claim 1, wherein composite construction is at least 5 × 104cm/s。
4. the semiconductor devices of claim 1, further comprises:Separation structure extends logical from the surface of semiconductor body It crosses Disengagement zone and at least to drift region band and abuts directly against access raceway groove downwards.
5. the semiconductor devices of claim 4, wherein:
Disengagement zone has the conduction type with the conduction type complementation of drift region band;
Accessing raceway groove has the conduction type of drift region band;And
Separation structure extends into drift region band from the first surface of semiconductor body.
6. the semiconductor devices of claim 4, wherein:
Disengagement zone has the conduction type of drift region band;
Accessing raceway groove has the conduction type opposite with the conduction type of drift region band;And
Separation structure extends into drift region band from the second surface of semiconductor body.
7. the semiconductor devices of claim 4, wherein:
First Disengagement zone has the conduction type with the conduction type complementation of drift region band;
First access raceway groove has the conduction type of drift region band;
First separation structure extends into drift region band from the first surface of semiconductor body;
Second Disengagement zone has the conduction type of drift region band;
Second access raceway groove has the conduction type opposite with the conduction type of drift region band;And
Second separation structure extends into drift region band from the second surface opposite with first surface of semiconductor body.
8. the semiconductor devices of claim 4, wherein separation structure are made of dielectric and/or intrinsic material.
9. the semiconductor devices of claim 4, wherein separation structure include insulating with the electrode dielectric of semiconductor devices Conductive material.
10. the semiconductor devices of claim 4, wherein separation structure include being electrically connected to the electrode of semiconductor devices to lead Electric material.
11. the semiconductor devices of claim 1, wherein access raceway groove has the conduction opposite with the conduction type of Disengagement zone Type.
12. the semiconductor devices of claim 4, wherein:
Accessing raceway groove has the conduction type of Disengagement zone;And
Fixed charge in separation structure induces electric field, the electric field along separation structure stored charge carrier type freedom Electric charge carrier, the charge carrier type correspond to the conductive-type opposite with the conduction type in charge carrier transport area Type.
13. the semiconductor devices of claim 1, wherein access raceway groove is configured such that the electric charge stream by accessing raceway groove It moves and is saturated under the load current higher than maximum impulse load current by drift region band.
14. the semiconductor devices of claim 1, wherein access raceway groove is configured such that the electric charge stream by accessing raceway groove It moves and is saturated under the load current less than maximum impulse load current by drift region band.
15. the semiconductor devices of claim 1, wherein:
The access raceway groove of first desaturation unit, which is configured such that, to be flowed by the charge for accessing raceway groove by drift region band The load current higher than maximum impulse load current under be saturated;And
The access raceway groove of second desaturation unit, which is configured such that, to be flowed by the charge for accessing raceway groove by drift region band The load current less than maximum impulse load current under be saturated.
16. metallic atom is contained in the semiconductor devices of claim 1, wherein recombination region.
17. the semiconductor devices of claim 1, wherein access raceway groove contains deep grade alms giver.
18. the semiconductor devices of claim 1, wherein:
Access raceway groove and recombination region form desaturation unit and semiconductor devices further comprises arranging in the active areas Multiple desaturation units;And
Charge carriers electron current in desaturation unit increases, the fringe region with the distance for being reduced to fringe region Around active region and there is no desaturation unit.
19. the semiconductor devices of claim 1, wherein:
Semiconductor devices is diode;And
Charge carrier transport area is electrically connected to load electrode.
20. the semiconductor devices of claim 1, further comprises:
FET unit, including it is electrically connected to the source area of load electrode, and
Wherein charge carrier transport area includes the body region for detaching source area with drift region band.
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Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100117117A1 (en) * 2008-11-10 2010-05-13 Infineon Technologies Ag Vertical IGBT Device
US9024413B2 (en) * 2013-01-17 2015-05-05 Infineon Technologies Ag Semiconductor device with IGBT cell and desaturation channel structure
US9419080B2 (en) 2013-12-11 2016-08-16 Infineon Technologies Ag Semiconductor device with recombination region
US9543389B2 (en) * 2013-12-11 2017-01-10 Infineon Technologies Ag Semiconductor device with recombination region
WO2016114043A1 (en) * 2015-01-13 2016-07-21 富士電機株式会社 Semiconductor device and method for manufacturing same
DE102015111347B4 (en) 2015-07-14 2020-06-10 Infineon Technologies Ag SUSTAINABLE SEMICONDUCTOR DEVICE WITH TRANSISTOR CELLS AND AUXILIARY CELLS
DE102015117994B8 (en) 2015-10-22 2018-08-23 Infineon Technologies Ag Power semiconductor transistor with a fully depleted channel region
DE102016112018B4 (en) 2016-06-30 2020-03-12 Infineon Technologies Ag Power semiconductor device with completely depleted channel regions
JP6635900B2 (en) * 2016-09-13 2020-01-29 株式会社東芝 Semiconductor device
JP6988175B2 (en) * 2017-06-09 2022-01-05 富士電機株式会社 Silicon Carbide Semiconductor Device and Method for Manufacturing Silicon Carbide Semiconductor Device
DE102018106992B3 (en) * 2018-03-23 2019-07-04 Infineon Technologies Ag SILICON CARBIDE SEMICONDUCTOR ELEMENT
JP2020034521A (en) * 2018-08-31 2020-03-05 ソニーセミコンダクタソリューションズ株式会社 Light receiving element and distance measuring system

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6400003B1 (en) * 1998-02-12 2002-06-04 Koninklijke Philips Electronics N.V. High voltage MOSFET with geometrical depletion layer enhancement
CN103515384A (en) * 2012-06-21 2014-01-15 英飞凌科技股份有限公司 Semiconductor device with charge carrier lifetime reduction means

Family Cites Families (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6037628A (en) * 1997-06-30 2000-03-14 Intersil Corporation Semiconductor structures with trench contacts
DE10060428B4 (en) 2000-12-05 2006-07-06 Infineon Technologies Ag By field effect controllable in both directions blocking semiconductor device and method for its production
JP4823435B2 (en) 2001-05-29 2011-11-24 三菱電機株式会社 Semiconductor device and manufacturing method thereof
JP2006245243A (en) * 2005-03-02 2006-09-14 Fuji Electric Device Technology Co Ltd Semiconductor device and manufacturing method thereof
DE102009047808B4 (en) 2009-09-30 2018-01-25 Infineon Technologies Austria Ag Bipolar semiconductor device and method for producing a semiconductor diode
US20120261746A1 (en) 2011-03-14 2012-10-18 Maxpower Semiconductor, Inc. Double-Trench Vertical Devices and Methods with Self-Alignment Between Gate and Body Contact
JP2013235891A (en) 2012-05-07 2013-11-21 Denso Corp Semiconductor device
US8921931B2 (en) 2012-06-04 2014-12-30 Infineon Technologies Austria Ag Semiconductor device with trench structures including a recombination structure and a fill structure
US9362349B2 (en) * 2012-06-21 2016-06-07 Infineon Technologies Ag Semiconductor device with charge carrier lifetime reduction means
US8710620B2 (en) 2012-07-18 2014-04-29 Infineon Technologies Ag Method of manufacturing semiconductor devices using ion implantation
US9024413B2 (en) 2013-01-17 2015-05-05 Infineon Technologies Ag Semiconductor device with IGBT cell and desaturation channel structure
US9245984B2 (en) 2013-01-31 2016-01-26 Infineon Technologies Ag Reverse blocking semiconductor device, semiconductor device with local emitter efficiency modification and method of manufacturing a reverse blocking semiconductor device
US9209109B2 (en) 2013-07-15 2015-12-08 Infineon Technologies Ag IGBT with emitter electrode electrically connected with an impurity zone
US9337827B2 (en) 2013-07-15 2016-05-10 Infineon Technologies Ag Electronic circuit with a reverse-conducting IGBT and gate driver circuit
US9666663B2 (en) 2013-08-09 2017-05-30 Infineon Technologies Ag Semiconductor device with cell trench structures and contacts and method of manufacturing a semiconductor device
US9076838B2 (en) 2013-09-13 2015-07-07 Infineon Technologies Ag Insulated gate bipolar transistor with mesa sections between cell trench structures and method of manufacturing
US9082629B2 (en) 2013-09-30 2015-07-14 Infineon Technologies Ag Semiconductor device and method for forming a semiconductor device
US9147727B2 (en) 2013-09-30 2015-09-29 Infineon Technologies Ag Semiconductor device and method for forming a semiconductor device
US9105679B2 (en) 2013-11-27 2015-08-11 Infineon Technologies Ag Semiconductor device and insulated gate bipolar transistor with barrier regions
US9385228B2 (en) 2013-11-27 2016-07-05 Infineon Technologies Ag Semiconductor device with cell trench structures and contacts and method of manufacturing a semiconductor device
US9419080B2 (en) 2013-12-11 2016-08-16 Infineon Technologies Ag Semiconductor device with recombination region
US9543389B2 (en) 2013-12-11 2017-01-10 Infineon Technologies Ag Semiconductor device with recombination region

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6400003B1 (en) * 1998-02-12 2002-06-04 Koninklijke Philips Electronics N.V. High voltage MOSFET with geometrical depletion layer enhancement
CN103515384A (en) * 2012-06-21 2014-01-15 英飞凌科技股份有限公司 Semiconductor device with charge carrier lifetime reduction means

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