JP2006245243A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To make the resistance component of a channel region comparable to that of a silicon device, to enable the semiconductor device to be manufactured according to the manufacturing process of a silicon device, and make the variations in the threshold of the semiconductor device comparable to those of a silicon device, in a power semiconductor device whose drift region consisting of a wide band-gap semiconductor, such as gallium nitride. <P>SOLUTION: A first semiconductor layer 3 of gallium nitride is laminated on a support substrate 2 of silicon, and a second semiconductor layer 4 of silicon is laminated further thereon. A surface structure of the semiconductor device is fabricated in this second semiconductor layer 4 by using existing advanced processing technologies, such as microfabrication technology for silicon, etc. Further, a high breakdown voltage structure, wherein the second semiconductor layer 4 is removed to expose the first semiconductor layer 3, is provided in the peripheral portion of the chip. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly, to a power semiconductor device having a drift region made of a semiconductor material having a wider band gap than silicon (hereinafter referred to as a wide band gap semiconductor) and a manufacturing method thereof.

Conventionally, gallium nitride (GaN) -based compound semiconductors have been used as semiconductor materials in semiconductor conductive elements for high-frequency devices. For example, in Patent Document 1, a buffer layer made of high-resistance aluminum gallium nitride (Al _x Ga _1-x N, 0 <x ≦ 1) and an undoped gallium nitride are sequentially formed on a p-type conductive substrate made of silicon. And a surface barrier layer (carrier supply layer) made of n-type aluminum gallium nitride (Al _y Ga _1-y N, 0 <y ≦ 1), and Schottky on the surface barrier layer A heterojunction field-effect transistor having a configuration in which a gate electrode having a property is selectively formed is disclosed.

  Recently, in the field of power semiconductor devices, attempts have been made to use wide band gap semiconductors such as gallium nitride compound semiconductors. For example, in an insulated gate bipolar transistor disclosed in Patent Document 2, a p-type semiconductor layer and an n-type semiconductor layer made of a gallium nitride compound semiconductor are sequentially stacked on a substrate crystal, and on this n-type semiconductor layer, A p-type impurity diffusion region and an n-type impurity diffusion region made of a gallium nitride compound semiconductor having a wider band gap than the n-type semiconductor layer are selectively formed. The gate electrode is formed through an insulating layer from the exposed surface of the n-type semiconductor layer to the exposed surface of the p-type impurity diffusion region, and the emitter electrode and the collector electrode are respectively an upper surface of the n-type impurity diffusion region and p It is formed on the lower surface of the type semiconductor layer.

JP 2004-363563 A JP-A-11-354786

However, the semiconductor device disclosed in Patent Document 2 has a drawback that the resistance component of the channel region is significantly larger than that of a device using normal silicon (hereinafter referred to as a silicon device). The reason is that the mobility of the inversion layer obtained in the MOS (metal-oxide film-insulated gate made of semiconductor) structure using silicon is about several hundred cm ² / Vs (about 500 cm ² / Vs). On the other hand, the mobility of the inversion layer in the case of using a gallium nitride compound semiconductor is as low as about several tens of cm ² / Vs. The same applies to the case where silicon carbide (SiC) is used as the semiconductor conductor material.

  Moreover, it is not easy to introduce impurities into a wide band gap semiconductor such as gallium nitride or silicon carbide by ion implantation. Silicon carbide requires heat treatment at a high temperature of 1600 ° C. In addition, since the crystal structure of gallium nitride becomes unstable at high temperatures, heat treatment must be performed at a temperature of 1000 ° C. or lower. Therefore, the impurity introduced into gallium nitride by the ion implantation method cannot be activated. Therefore, for example, in manufacturing the semiconductor device disclosed in Patent Document 2, a metal organic chemical vapor deposition (MOCVD) method or molecular beam epitaxy (MBE) is formed on an n-type gallium nitride compound semiconductor layer serving as a drift region. ) Method or the like to form an impurity diffusion region of a p-type or n-type gallium nitride compound semiconductor.

  At that time, it is necessary to perform some selective growth or selective etching in order to secure the breakdown voltage by keeping the conductivity type of the semiconductor at the end of the chip at n-type, and there is a problem that the manufacturing process becomes complicated. . Furthermore, because of the poor controllability of the impurity density when growing a gallium nitride crystal, devices using gallium nitride (hereinafter referred to as gallium nitride devices) have a variation in threshold values compared to silicon devices. Will become very large. Therefore, for example, when a large capacity circuit is configured by connecting gallium nitride devices in parallel, there is a possibility that problems such as non-uniform current sharing may occur.

  Further, since the semiconductor device disclosed in Patent Document 1 is an element having a lateral HEMT structure for a high-frequency device, the channel region has high mobility, but is preferably used as a high-breakdown-voltage switching element with the same configuration. Absent. For example, in the semiconductor device disclosed in Patent Document 1, since the gate has a Schottky structure, when a gate voltage of +2 V or more is applied, the Schottky junction is biased in the forward direction, and the gate current increases and breaks down. End up. Further, the gate voltage is negatively biased to cut off the two-dimensional gas channel, so that the gate is required to be long in order to increase the breakdown voltage. Therefore, the higher the breakdown voltage, the larger the gate capacitance, and the high-speed switching performance is lost.

  In order to solve the above-described problems caused by the prior art, the present invention provides a power semiconductor device in which the drift region is composed of a wide band gap semiconductor such as gallium nitride and the resistance component of the channel region is the same as that of a silicon device, and a method for manufacturing the same The purpose is to provide. It is another object of the present invention to provide a power semiconductor device having a configuration in which the drift region is formed of a wide band gap semiconductor such as gallium nitride and can be manufactured by a silicon device manufacturing process, and a manufacturing method thereof. Another object of the present invention is to provide a power semiconductor device in which the drift region is formed of a wide band gap semiconductor such as gallium nitride and the variation in threshold is comparable to that of a silicon device, and a manufacturing method thereof.

  In order to solve the above-described problems and achieve the object, a semiconductor device according to a first aspect of the present invention includes a first semiconductor layer made of a semiconductor material having a wider bandgap than silicon, and the first semiconductor layer. A second semiconductor layer made of stacked silicon, a surface structure portion of one or more semiconductor elements formed in the second semiconductor layer, and the first semiconductor layer more than the second semiconductor layer. And a pressure-resistant structure portion provided in an outer region.

  A semiconductor device according to a second aspect of the present invention is the semiconductor device according to the first aspect, wherein the breakdown voltage structure portion is a structure in which the second semiconductor layer is partially removed and the first semiconductor layer is exposed. It is characterized by being. According to a third aspect of the present invention, there is provided a semiconductor device according to the second aspect of the present invention, wherein an impurity region having a conductivity type different from that of the first semiconductor layer is formed in the exposed portion of the first semiconductor layer of the breakdown voltage structure portion. Is provided so as to surround the periphery of the second semiconductor layer.

  A semiconductor device according to a fourth aspect of the present invention is the semiconductor device according to the third aspect, wherein the breakdown voltage structure portion is electrically connected to the impurity region by an insulating film that covers the first semiconductor layer. A conductive portion insulated from the first semiconductor layer is provided. According to a fifth aspect of the present invention, there is provided the semiconductor device according to the second aspect, wherein the exposed portion of the first semiconductor layer exposed in the breakdown voltage structure portion is from the second semiconductor layer to the first semiconductor layer. It is formed into a frustum shape that becomes wider as it approaches.

  A semiconductor device according to a sixth aspect of the present invention is the semiconductor device according to any one of the first to fifth aspects, wherein the band gap is greater than that of silicon between the first semiconductor layer and the second semiconductor layer. One or more semiconductor layers made of a wide semiconductor material are provided. A semiconductor device according to a seventh aspect of the present invention is the semiconductor device according to any one of the first to sixth aspects, wherein the first semiconductor layer is made of a semiconductor material having a band gap of 3 eV or more. And According to an eighth aspect of the present invention, in the semiconductor device according to the seventh aspect, the first semiconductor layer is made of a gallium nitride-based compound semiconductor material.

  A semiconductor device according to a ninth aspect of the present invention is the semiconductor device according to any one of the first to eighth aspects, wherein the first semiconductor layer is stacked on a support substrate. The semiconductor device according to a tenth aspect of the present invention is the semiconductor device according to the ninth aspect, wherein the support substrate is made of silicon. A semiconductor device according to an eleventh aspect of the present invention is the semiconductor device according to any one of the first to tenth aspects, wherein the second semiconductor layer has an insulated gate semiconductor element having a metal-insulating film-semiconductor structure. A surface structure portion is formed.

  According to a twelfth aspect of the present invention, there is provided a method for manufacturing a semiconductor device, comprising: growing a silicon on a first semiconductor layer made of a semiconductor material having a wider band gap than silicon; and laminating a second semiconductor layer; Forming a trench forming mask on the second semiconductor layer; etching the second semiconductor layer to form a trench; and when the first semiconductor layer is exposed at the bottom of the trench. Etching is stopped, and after removing the mask, the bottom of the trench is deeper than the interface between the first semiconductor layer and the second semiconductor layer using the remaining portion of the second semiconductor layer as a mask. And etching the first semiconductor layer in a self-aligning manner until it becomes.

  According to a thirteenth aspect of the present invention, there is provided a method for manufacturing a semiconductor device, comprising: a first main surface having a surface structure portion of one or more semiconductor elements including a first conductivity type impurity diffusion region and a gate portion; In manufacturing a semiconductor device having a back electrode on the main surface, silicon is grown on a first semiconductor layer of a first conductivity type made of a semiconductor material having a wider bandgap than silicon, and a second conductivity type second semiconductor is formed. Laminating the semiconductor layer, forming a trench forming mask on the second semiconductor layer, etching the second semiconductor layer to form a trench, and forming the trench at the bottom of the trench. Etching is stopped when the first semiconductor layer is exposed; and after the mask is removed, the bottom of the trench is connected to the first semiconductor layer and the first semiconductor layer using the remaining portion of the second semiconductor layer as a mask. 2 semiconductor layers Etching the first semiconductor layer in a self-aligned manner until it becomes deeper than the interface; forming a gate insulating film on the inner surface of the trench; and connecting the inner part of the gate insulating film to the conductor in the trench And a step of filling with.

  According to a fourteenth aspect of the present invention, there is provided a semiconductor device manufacturing method according to the thirteenth aspect, wherein the gate insulating film is formed by a chemical vapor deposition method. According to a fifteenth aspect of the present invention, in the semiconductor device manufacturing method according to the thirteenth aspect, the gate insulating film is formed by a sputtering method.

  According to the first to eleventh aspects of the present invention, since the surface structure portion of the semiconductor element can be manufactured using existing advanced processing technology such as silicon micromachining technology, the surface structure portion is relatively complicated. Even a simple structure can be easily manufactured. Further, by producing the surface structure portion of the semiconductor element using a silicon process that has already established accurate controllability such as an ion implantation method and a thermal diffusion treatment, variation in threshold value can be extremely reduced.

  Further, since the inversion layer region is made of silicon, high inversion layer mobility comparable to that of silicon can be obtained. Therefore, the resistance component in the inversion layer region can be suppressed to be almost as low as that of the conventional silicon device. Further, since the thickness of the first semiconductor layer can be reduced to about 1/10 of the thickness of the conventional silicon device, for example, a vertical MIS type semiconductor device using the first semiconductor layer as a drift layer. , The resistance component of the drift layer in the on-resistance can be reduced to about 1/10 that of the conventional silicon device. Therefore, the overall on-resistance obtained by adding the resistance component of the drift layer to the resistance component of the drift layer and other portions can be greatly reduced.

  According to the inventions of claims 2 to 5, the first semiconductor layer is made of a wide band gap semiconductor such as gallium nitride, and by forming the breakdown voltage structure portion in the first semiconductor layer on the outer periphery of the chip, A higher device breakdown voltage can be obtained with shorter dimensions than when the first semiconductor layer is made of silicon. Therefore, the ratio of the invalid area of the chip can be greatly reduced.

  According to the invention of claim 11, since the gate breakdown voltage of the insulated gate semiconductor element is determined by the breakdown voltage of the gate insulating film, both positive and negative voltages of about several tens of volts can be applied to the gate electrode. . Further, since the gate structure does not depend on the element breakdown voltage, high-speed switching performance can be obtained even with a high breakdown voltage element.

  According to the inventions of claims 12 to 15, the surface structure portion of the semiconductor element can be manufactured using an existing advanced processing technique such as a silicon micro-processing technique. In particular, a trench of a semiconductor element having a trench structure, such as a trench gate type semiconductor element having a gate insulating film and a gate electrode in the trench, has a bottom from the interface between the first semiconductor layer and the second semiconductor layer. Can be easily formed to be deep. In addition, a gate insulating film can be easily formed on the inner surface of the trench.

  According to the semiconductor device and the manufacturing method thereof according to the present invention, the power semiconductor device in which the drift region is formed of a wide band gap semiconductor such as gallium nitride has the following effects. That is, the resistance component of the channel region can be made comparable to that of the silicon device. Further, it can be manufactured by a silicon device manufacturing process. Further, the variation in threshold value can be made comparable to that of a silicon device.

  Exemplary embodiments of a semiconductor device and a method for manufacturing the same according to the present invention will be explained below in detail with reference to the accompanying drawings. Note that, in the following description of the embodiments and the accompanying drawings, the same reference numerals are given to the same components, and duplicate descriptions are omitted.

  FIG. 1 is a cross-sectional view showing the entire semiconductor device according to the present invention. As shown in FIG. 1, a first semiconductor layer 3 serving as a drift layer is stacked on the drain electrode 1 and the support substrate 2, and a second semiconductor layer 4 is stacked on the first semiconductor layer 3. ing. A surface structure portion of the semiconductor element is formed in the second semiconductor layer 4. The type of the semiconductor element is not particularly limited, but here, as an example, a vertical power MOSFET (insulated gate field effect transistor having a metal-oxide film-semiconductor structure) is used. The support substrate 2 is not particularly limited, but is an n-type silicon substrate, for example. In the case of a vertical semiconductor element, the support substrate 2 is preferably a low resistance material.

  The first semiconductor layer 3 is, for example, a wide band gap semiconductor having a band gap of 3 eV or more, and is not particularly limited. For example, the first semiconductor layer 3 can be made of an n-type gallium nitride semiconductor, n-type silicon carbide, or n-type diamond (C). ing. Here, the gallium nitride based semiconductor includes aluminum gallium nitride in addition to gallium nitride. The second semiconductor layer 4 serving as the p base layer is made of p-type silicon. A trench 5 that penetrates through the second semiconductor layer 4 from the surface of the second semiconductor layer 4 and reaches the first semiconductor layer 3 is formed. The bottom of the trench 5 is deeper than the interface between the first semiconductor layer 3 and the second semiconductor layer 4.

A gate insulating film 6 is formed on the inner surface of the trench 5, and the inner side thereof is filled with a gate electrode 7. The gate insulating film 6 is made of, for example, silicon dioxide (SiO ₂ ), silicon nitride (Si ₃ N ₄ ), aluminum nitride (AlN), magnesium oxide (MgO), or hafnium oxide (HfO ₂ ). The gate electrode 7 is made of polysilicon, aluminum (Al), nickel (Ni), titanium (Ti), tungsten (W), molybdenum (Mo), platinum (Pt), palladium (Pd), chromium (Cr), iridium. It is made of a metal such as (Ir), gold (Au), silver (Ag) or zinc (Zn), or an alloy or silicide thereof.

  In the second semiconductor layer 4, an n-type impurity diffusion region 8 serving as a source region is formed outside the trench 5. A p-type impurity diffusion region 9 is formed next to the n-type impurity diffusion region 8 in the second semiconductor layer 4. The gate electrode 7 is covered with an insulating film 10 and is insulated from the source electrode 11 in contact with both the n-type impurity diffusion region 8 and the p-type impurity diffusion region 9.

As shown in FIG. 1 and FIG. 2 which is an enlarged view thereof, the breakdown voltage structure has a structure in which the first semiconductor layer 3 is exposed at the outer periphery of the chip. In order to manufacture such a structure, the second semiconductor layer 4 may be selectively dry etched, and the etching may be terminated when the first semiconductor layer 3 is exposed. When the first semiconductor layer 3 is made of gallium nitride, dry etching may be performed using a fluorine-based reaction gas such as CF ₄ .

  Alternatively, when the crystal orientation of silicon constituting the second semiconductor layer 4 is the <111> direction, wet anisotropy using an alkaline solution, for example, potassium hydroxide (KOH) solution, instead of dry etching Etching may be performed. In this case, an island-shaped second semiconductor layer 4 made of silicon having a crystal orientation of <111> is formed. Regardless of the formation method, a breakdown voltage of about 600 V can be secured by providing such a breakdown voltage structure with the first semiconductor layer 3 exposed without providing a breakdown voltage structure such as a guard ring.

  In manufacturing the power MOSFET according to the present embodiment, a silicon device manufacturing process having a similar configuration can be applied. However, since the material of the portion where the trench 5 can be opened is changed from silicon to a wide band gap semiconductor such as gallium nitride during the formation of the trench 5, a trench gate structure is manufactured as follows, for example.

3 to 8 are cross-sectional views illustrating a procedure for manufacturing a trench gate structure. First, an etching mask 12 made of, for example, a silicon oxide film (SiO ₂ ) or a photoresist is stacked on the surface of the second semiconductor layer 4 stacked on the first semiconductor layer 3. When the etching mask 12 is a silicon oxide film, an oxide film is generated by a thermal oxidation method or an oxide film is deposited by a chemical vapor deposition (CVD) method. Then, a trench etching pattern is formed on the etching mask 12 (FIG. 3).

  Next, anisotropic etching such as RIE (reactive etching) is performed to form a trench 5 in the second semiconductor layer 4 (FIG. 4). FIG. 4 shows a state in the middle of etching. During this etching, when it is detected that the first semiconductor layer 3 is exposed at the bottom of the trench 5, the etching is stopped (FIG. 5). Then, the etching mask 12 is removed. Thereafter, the first semiconductor layer 3 is etched in a self-aligning manner using the remaining silicon of the second semiconductor layer 4 as a mask to deepen the trench 5 (FIG. 6). This second-stage etching may be anisotropic etching by RIE, or isotropic etching by normal dry etching.

When the trench formation is completed, a gate insulating film 6 is formed (FIG. 7). At this time, a CVD method or a sputtering method may be used. For example, when the first semiconductor layer 3 is made of gallium nitride or silicon carbide, gallium oxide (Ga ₂ O ₃ ) or dioxide by thermal oxidation, respectively. Silicon may be produced. Next, a conductor to be the gate electrode 7 is deposited by CVD or sputtering (FIG. 8). Then, the gate insulating film 6 and the gate electrode 7 are formed into a desired pattern to complete a trench gate structure. The subsequent processes are the same as those of a normal silicon device such as a MOSFET having a trench gate structure.

  FIG. 9 is a cross-sectional view showing another configuration of the pressure-resistant structure. 9 includes a p-type impurity region 13 serving as a guard ring so as to surround the second semiconductor layer 4 along the outer periphery of the chip, in a part of the exposed portion of the first semiconductor layer 3. It is provided. In the illustrated example, the number of guard rings is one, but two or more guard rings may be provided. By providing the breakdown voltage structure shown in FIG. 9, a higher breakdown voltage than that shown in FIG. 2 can be obtained.

  FIG. 10 is a cross-sectional view showing another configuration of the pressure-resistant structure portion. The breakdown voltage structure shown in FIG. 10 is the same as the breakdown voltage structure shown in FIG. 9 except that the exposed portion of the first semiconductor layer 3 is covered with an insulating film 14 and becomes a guard ring through the opening of the insulating film 14. The field plate 15 is brought into contact with the type impurity region 13. The insulating film 14 is made of, for example, silicon dioxide, silicon nitride, or aluminum nitride.

FIG. 11 is a cross-sectional view showing another configuration of the pressure-resistant structure. 11 has a frustum shape (mesa shape) in which the first semiconductor layer 3 becomes wider as the terminal portion of the first semiconductor layer 3 approaches the support substrate 2 from the second semiconductor layer 4. ) Bevel structure. In order to form the terminal portion of the first semiconductor layer 3 in such a shape, as shown in FIG. 12, the second semiconductor layer 4 and the first semiconductor layer 3 near the second semiconductor layer 4 are formed. The first semiconductor layer 3 is isotropically dry-etched with the portion covered with the etching mask 16, and the etching may be terminated when the support substrate 2 is exposed. As the etching mask 16, for example, a photoresist may be used, or a silicon oxide film or a nitride film (Si ₃ N ₄ ) may be used.

  As described above, according to the embodiment, the surface structure portion of the semiconductor element can be manufactured by using existing advanced processing technology such as silicon micromachining technology. Even a complicated structure can be easily manufactured. For example, the variation in threshold value can be made extremely small by fabricating the surface structure portion of the MOSFET using a silicon process that has already established accurate controllability such as ion implantation and thermal diffusion.

  On the other hand, when the second semiconductor layer 4 is not silicon but silicon carbide, it is necessary to perform heat treatment at a high temperature of 1600 ° C. or higher when forming the impurity diffusion region provided in the surface structure portion of the semiconductor element. There is. For this reason, a high-performance heat treatment apparatus is required, and there are disadvantages that the cost of the apparatus is increased, and that heating and cooling to a predetermined temperature takes time, and throughput is reduced. In addition, when the second semiconductor layer 4 is gallium nitride, the gallium nitride becomes unstable in a high temperature environment of 1000 ° C. or higher, and thus the surface structure portion of the semiconductor element is manufactured at a temperature lower than 1000 ° C. There is a need. In that case, it is extremely difficult to produce an impurity diffusion region, particularly a p-type impurity diffusion region by a general method such as an ion implantation method.

  According to the embodiment, since the inversion layer region is made of silicon, high inversion layer mobility comparable to that of silicon can be obtained. Therefore, the resistance component in the inversion layer region can be suppressed to be almost as low as that of the conventional silicon device. Furthermore, since the thickness of the first semiconductor layer 3 can be reduced to about 1/10 of the thickness of a conventional silicon device, for example, a vertical MIS type having the first semiconductor layer 3 as a drift layer. When a semiconductor device is manufactured, the resistance component of the drift layer in the on-resistance can be approximately 1/10 that of a conventional silicon device. Therefore, the overall on-resistance obtained by adding the resistance component of the drift layer to the resistance component of the drift layer and other portions can be greatly reduced.

  For example, in a conventional MOSFET with a withstand voltage of 600 V made of silicon, the theoretical limit value of the on-resistance is 53 mΩcm. Further, analysis using simulation or the like shows that about 92% of the on-resistance, that is, 48.8 mΩcm is occupied by the resistance component of the drift layer. The remaining 4.2 mΩcm is a resistance component other than the drift layer, such as channel resistance. Here, if the thickness of the drift layer is 1/10 of the conventional one, even if the resistivity of the drift layer is the same as the conventional one, the overall on-resistance is 9.1 mΩcm ( = 48.8 mΩcm × (1/10) +4.2 mΩcm).

Further, according to the embodiment, by forming the breakdown voltage structure portion in the first semiconductor layer 3 on the outer peripheral portion of the chip, a high element breakdown voltage can be obtained with a short dimension. For example, when the first semiconductor layer 3 is made of a wide bandgap semiconductor such as gallium nitride, an electric field strength that is an order of magnitude higher than when the first semiconductor layer 3 is made of silicon is allowed. Therefore, for example, if the first semiconductor layer 3 is made of gallium nitride and an attempt is made to obtain a withstand voltage of 600 V, the width of the withstand voltage structure portion is sufficient to be 50 μm or less. As an example, in a square chip having a side length of 3 mm (area is 9.0 mm ² ), if the width of the pressure-resistant structure is 50 μm, the effective area of the chip is 8.41 mm ² (= (3-0.05 × 2) ² ), and the proportion of the invalid area is 6.6%.

On the other hand, when the first semiconductor layer 3 is made of silicon, since the band gap of silicon is 1.1 eV, the maximum electric field is set to 0.3 MV / cm or less to obtain a high breakdown voltage. There is a need. Therefore, for example, if a breakdown voltage of 600 V is to be obtained, the width of the breakdown voltage structure portion is 300 μm or more. If the width of the pressure-resistant structure is 300 μm, the effective area of the chip is 5.76 mm ² (= (3-0.3 × 2) ² ) for a square chip with a side length of 3 mm, and the proportion of the ineffective area Will be 36%. Therefore, according to the embodiment, the ratio of the ineffective area of the chip can be greatly reduced.

  In addition, according to the embodiment, since the gate breakdown voltage is determined by the breakdown voltage of the gate insulating film 6, both positive and negative voltages of about several tens of volts can be applied to the gate electrode 7. Further, since the gate structure does not depend on the element breakdown voltage, high-speed switching performance can be obtained even with a high breakdown voltage element.

  As described above, the present invention is not limited to the above-described embodiment, and various modifications can be made. For example, the material of the support substrate 2 may be the same as the material of the first semiconductor layer 3. That is, when the first semiconductor layer 3 is made of gallium nitride, the support substrate 2 may also be made of gallium nitride. In this case, the support substrate 2 and the first semiconductor layer 3 may be separate, and the first semiconductor layer 3 may be epitaxially grown on the support substrate 2. Alternatively, the support substrate 2 and the first semiconductor layer 3 are the same, and the support substrate 2 including the first semiconductor layer 3 may be used.

Further, when the first semiconductor layer 3 is made of gallium nitride, the support substrate 2 is made of silicon, silicon carbide, or sapphire (Al ₂ O ₃ ), and between the support substrate 2 and the first semiconductor layer 3. A buffer layer made of aluminum nitride or the like may be provided. Further, when the semiconductor element is a horizontal element, the support substrate 2 may be made of an insulating material. Further, the number of semiconductor elements formed in the second semiconductor layer 4 may be one, or may be three or more. Further, a semiconductor element other than a MOSFET, for example, an IGBT (Insulated Gate Bipolar Transistor) or a Schottky diode may be manufactured. It should be noted that the present invention holds true even if the p-type and n-type conductivity types are reversed.

  As described above, the semiconductor device and the manufacturing method thereof according to the present invention are useful for power semiconductor devices used for power conversion devices such as inverters, power supply devices such as various industrial machines, automobile igniters and the like.

It is sectional drawing which shows the whole semiconductor device concerning this invention. It is sectional drawing which expands and shows the pressure | voltage resistant structure part of FIG. It is sectional drawing explaining the preparation procedures of the trench gate structure of FIG. It is sectional drawing explaining the preparation procedures of the trench gate structure of FIG. It is sectional drawing explaining the preparation procedures of the trench gate structure of FIG. It is sectional drawing explaining the preparation procedures of the trench gate structure of FIG. It is sectional drawing explaining the preparation procedures of the trench gate structure of FIG. It is sectional drawing explaining the preparation procedures of the trench gate structure of FIG. It is sectional drawing which shows another structure of a pressure | voltage resistant structure part. It is sectional drawing which shows another structure of a pressure | voltage resistant structure part. It is sectional drawing which shows another structure of a pressure | voltage resistant structure part. It is sectional drawing explaining the formation method of the pressure | voltage resistant structure part of FIG.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Drain electrode 2 Support substrate 3 1st semiconductor layer 4 2nd semiconductor layer 5 Trench 12 Mask for trench formation 13 Impurity region 14 Insulating film 15 Conductive part (field plate)

Claims (15)

A first semiconductor layer made of a semiconductor material having a wider band gap than silicon;
A second semiconductor layer made of silicon stacked on the first semiconductor layer;
A surface structure portion of one or more semiconductor elements formed in the second semiconductor layer;
A breakdown voltage structure provided in a region of the first semiconductor layer outside the second semiconductor layer;
A semiconductor device comprising:   2. The semiconductor device according to claim 1, wherein the breakdown voltage structure has a structure in which the second semiconductor layer is partially removed and the first semiconductor layer is exposed.   An impurity region having a conductivity type different from that of the first semiconductor layer is provided in an exposed portion of the first semiconductor layer in the breakdown voltage structure so as to surround the second semiconductor layer. The semiconductor device according to claim 2.   The withstand voltage structure portion is provided with a conductive portion electrically connected to the impurity region and insulated from the first semiconductor layer by an insulating film covering the first semiconductor layer. The semiconductor device according to claim 3.   The exposed portion of the first semiconductor layer exposed in the pressure-resistant structure portion is shaped into a frustum shape that becomes wider as it approaches the first semiconductor layer from the second semiconductor layer. The semiconductor device according to claim 2.   6. One or more semiconductor layers made of a semiconductor material having a wider band gap than silicon are provided between the first semiconductor layer and the second semiconductor layer. The semiconductor device as described in any one.   The semiconductor device according to claim 1, wherein the first semiconductor layer is made of a semiconductor material having a band gap of 3 eV or more.   The semiconductor device according to claim 7, wherein the first semiconductor layer is made of a gallium nitride-based compound semiconductor material.   The semiconductor device according to claim 1, wherein the first semiconductor layer is stacked on a support substrate.   The semiconductor device according to claim 9, wherein the support substrate is made of silicon.   11. The semiconductor according to claim 1, wherein a surface structure portion of an insulated gate semiconductor element having a metal-insulating film-semiconductor structure is formed in the second semiconductor layer. apparatus. A step of growing silicon on the first semiconductor layer made of a semiconductor material having a wider band gap than silicon and laminating the second semiconductor layer;
Forming a trench forming mask on the second semiconductor layer;
Etching the second semiconductor layer to form a trench, and stopping the etching when the first semiconductor layer is exposed at the bottom of the trench;
After the mask is removed, the first semiconductor is used until the bottom of the trench becomes deeper than the interface between the first semiconductor layer and the second semiconductor layer using the remaining portion of the second semiconductor layer as a mask. Etching the layer in a self-aligning manner;
A method for manufacturing a semiconductor device, comprising: In manufacturing a semiconductor device having a surface structure portion of one or more semiconductor elements having a first conductivity type impurity diffusion region and a gate portion on the first main surface and having a back electrode on the second main surface. ,
Growing a second conductive type second semiconductor layer by growing silicon on a first conductive type first semiconductor layer made of a semiconductor material having a wider band gap than silicon; and
Forming a trench forming mask on the second semiconductor layer;
Etching the second semiconductor layer to form a trench, and stopping the etching when the first semiconductor layer is exposed at the bottom of the trench;
After removing the mask, using the remaining portion of the second semiconductor layer as a mask, the first semiconductor until the bottom of the trench becomes deeper than the interface between the first semiconductor layer and the second semiconductor layer. Etching the layer in a self-aligning manner;
Forming a gate insulating film on the inner surface of the trench;
Filling an inner portion of the gate insulating film of the trench with a conductor;
A method for manufacturing a semiconductor device, comprising:   14. The method of manufacturing a semiconductor device according to claim 13, wherein the gate insulating film is formed by chemical vapor deposition. The method of manufacturing a semiconductor device according to claim 13, wherein the gate insulating film is formed by a sputtering method.

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