CN104716133A - Positive and negative high-voltage-resistant port ESD structure and equivalent circuit based on SCR structure - Google Patents
Positive and negative high-voltage-resistant port ESD structure and equivalent circuit based on SCR structure Download PDFInfo
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- CN104716133A CN104716133A CN201310695014.5A CN201310695014A CN104716133A CN 104716133 A CN104716133 A CN 104716133A CN 201310695014 A CN201310695014 A CN 201310695014A CN 104716133 A CN104716133 A CN 104716133A
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- 239000000758 substrate Substances 0.000 claims abstract description 5
- 238000009792 diffusion process Methods 0.000 claims description 29
- 101000668165 Homo sapiens RNA-binding motif, single-stranded-interacting protein 1 Proteins 0.000 claims description 20
- 102100039692 RNA-binding motif, single-stranded-interacting protein 1 Human genes 0.000 claims description 20
- 101100365087 Arabidopsis thaliana SCRA gene Proteins 0.000 claims description 14
- 101150105073 SCR1 gene Proteins 0.000 claims description 14
- 101100134054 Saccharomyces cerevisiae (strain ATCC 204508 / S288c) NTG1 gene Proteins 0.000 claims description 14
- 230000001960 triggered effect Effects 0.000 claims description 10
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 8
- 229910052760 oxygen Inorganic materials 0.000 claims description 8
- 239000001301 oxygen Substances 0.000 claims description 8
- 230000015556 catabolic process Effects 0.000 claims description 5
- 238000005204 segregation Methods 0.000 abstract 2
- 108010063955 thrombin receptor peptide (42-47) Proteins 0.000 description 7
- 238000000034 method Methods 0.000 description 2
- 230000002159 abnormal effect Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
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Abstract
The invention discloses a positive and negative high-voltage-resistant port ESD structure and an equivalent circuit based on an SCR structure. The port ESD structure comprises a P-shaped substrate, a first N-shaped buried layer and a second N-shaped buried layer; the first N-shaped buried layer, a first N + active area and a second N + active area are connected to a power electric potential through a first N trap and a second N trap respectively, and segregation is formed by the first N-shaped buried layer and a first P trap; the second N-shaped buried layer, a third N + active area and a fourth N + active area are connected to the power electric potential through a third N trap and a fourth N trap respectively, and segregation is formed by the second N-shaped buried layer and a second P trap; in use, the first N + active area, the second N + active area, the third N + active area and the fourth N + active area are all connected with a power source; a P+ active area is connected to the ground; active areas are connected with a port PAD; the active areas are connected with gate oxides; the active areas are connected to the ground. By means of the port ESD structure and the equivalent circuit, the port can be supported to work in a positive and negative voltage state, and meanwhile the ESD capacity is good.
Description
Technical field
The invention belongs to ESD device field, more specifically, relate to a kind of port ESD structure based on the resistance to positive or negative high voltage of SCR structure and equivalent electric circuit thereof.
Background technology
Along with reducing of semiconductor processing dimensions, the gap of device operating voltages and puncture voltage is more and more less, and electrostatic leakage (ESD) problem of integrated circuit is more and more significant.The operating voltage of IC port is between 0V and supply voltage under normal circumstances, thus when the ESD structure of port also only needs to ensure that port voltage is between 0V and supply voltage, ESD device does not have leakage current.And in some interface chips, there will be port voltage higher than supply voltage or the negative pressure lower than zero potential, ESD structure now will ensure the positive or negative high voltage that can bear port, meet ESD class requirement simultaneously.But the design of ESD protection at present, mainly for high voltage bearing requirement, does not relate to substantially to the design of resistance to positive/negative-pressure ability.Do not have the port of resistance to positive or negative high voltage ESD to protect, interface chip is difficult to when system is applied meet ESD requirement of shelter.
Summary of the invention
For above defect or the Improvement requirement of prior art, the invention provides a kind of port ESD device based on the resistance to positive or negative high voltage of SCR structure, also can meet the requirement of ESD protection Design while its object is to make signal port ESD structure have resistance to positive or negative high voltage characteristic, solve the technical problem not having the port of resistance to positive or negative high voltage ESD to protect in prior art thus.
The invention provides a kind of port ESD structure based on the resistance to positive or negative high voltage of SCR structure, comprise P type substrate, the first N-type buried layer and the second N-type buried layer; Described first N-type buried layer is received power supply potential and is formed with a P trap with a N+ active area, the 2nd N+ active area by a N trap, the 2nd N trap respectively and isolates; Described second N-type buried layer is received power supply potential and is formed with the 2nd P trap with the 3rd N+ active area, the 4th N+ active area by the 3rd N trap, the 4th N trap respectively and isolates; During application, a described N+ active area, described 2nd N+ active area, described 3rd N+ active area and described 4th N+ active area all connect power supply; P+ active area ground connection, active area meets port PAD, together with active area, grid oxygen are received with active area, grid oxygen, active area ground connection.
Present invention also offers a kind of equivalent electric circuit based on above-mentioned port ESD structure, comprise the first triode Q1, the second triode Q2, the 3rd triode Q3, the 4th triode Q4, the first resistance R1, the second resistance R2 and the 3rd resistance R3; The emitter of described first triode Q1 is connected to the base stage of described first triode Q1 by the first resistance R1, the collector electrode of described first triode Q1 is connected to the collector electrode of described 4th triode Q4 by the second resistance R2 of being sequentially connected in series and the 3rd resistance R3; The grounded emitter of described 4th triode Q4; The base stage of described second triode Q2 is connected to the link of described first triode Q1 and described resistance R2, the collector electrode of described second triode Q2 is connected to the base stage of described first triode Q1, and the emitter of described second triode Q2 is connected to the emitter of described 3rd triode Q3; Described second resistance R2 and described 3rd resistance R3 is connected in series the link that end is connected to described second triode Q2 and described 3rd triode Q3; The base stage of described 3rd triode Q3 is connected to the collector electrode of described 4th triode Q4, and the base stage of described 4th triode Q4 is connected rear also ground connection with the collector electrode of described 3rd triode Q3.
Wherein, described first triode Q1, described second triode Q2, described first resistance R1 and described second resistance R2 constitute the first SCR structure SCR1; Described 3rd triode Q3, described 4th triode Q4 and described 3rd resistance R3 constitute the second SCR structure SCR2.
Wherein, when an esd event occurs, when the voltage on PAD is greater than the puncture voltage between N-diffusion region and P trap; Described first SCR structure SCR1 is triggered, the P trap in described second SCR structure SCR2 and the diode forward conducting of N-diffusion region, and ESD electric current flows on GND by being reversed the SCR2 puncturing SCR1 and the forward conduction set out.
Wherein, when port voltage lower than GND current potential and absolute value is less than the puncture voltage between N-diffusion region and P trap time, described second SCR structure SCR2 can not be triggered, wholely form ESD structure by described second SCR structure SCR2 and described first SCR structure SCR1 and do not have leakage current, can not impact work port under negative pressure;
Wherein, when an esd event occurs, port voltage lower than GND current potential and absolute value is greater than the puncture voltage between N-diffusion region and P trap time, N-diffusion region in described second SCR structure SCR2 and the diode of P trap breakdown, described second SCR structure SCR2 is triggered, P trap in described first SCR structure SCR1 and the diode forward conducting of N-diffusion region, ESD electric current flows out from PAD port.
The present invention can support that port working is in positive/negative-pressure state, has good ESD ability simultaneously.
Accompanying drawing explanation
Fig. 1 is the ESD device cross-sectional view that prior art provides.
Fig. 2 is the equivalent circuit theory figure of the ESD device that prior art provides.
Fig. 3 is the cross-sectional view of the port ESD device based on the resistance to positive or negative high voltage of SCR structure that the embodiment of the present invention provides.
Fig. 4 is the equivalent circuit theory figure of the port ESD device based on the resistance to positive or negative high voltage of SCR structure that the embodiment of the present invention provides.
Embodiment
In order to make object of the present invention, technical scheme and advantage clearly understand, below in conjunction with drawings and Examples, the present invention is further elaborated.Should be appreciated that specific embodiment described herein only in order to explain the present invention, be not intended to limit the present invention.In addition, if below in described each execution mode of the present invention involved technical characteristic do not form conflict each other and just can mutually combine.
Embodiments provide a kind of port of resistance to positive or negative high voltage based on SCR structure ESD method for designing, while there is resistance to positive or negative high voltage characteristic, also can meet the requirement of ESD protection Design; Compared with prior art, not only solve the problem of the resistance to positive or negative high voltage of port, also solve ESD protection question.
Current high pressure port has multiple ESD structure, and wherein a kind of structure just as shown in Figure 1.This structure comprises P type substrate 1, N-type buried layer 2, and N-type buried layer is received power supply potential by N trap 3,19 and N+ active area 4,18 and formed isolation.When applying, active area 11,12,13 meets port PAD, P+ active area 5,17 and N+ active area 8,15 ground connection, grid oxygen 10,14 ground connection.P+ active area 12 is as emitter, N-diffusion region 9 is as base stage, and P trap 6, as collector, forms longitudinal PNP triode, in this PNP triode, base N-diffusion region 9 is by N+ active area 11,13 as contact, and collector P trap 6 is by P+ active area 5,17 conduct contact; N-diffusion region 9 is as collector, and P trap 6 is as base stage, and N+ active area 8,15, as emitter, forms horizontal NPN triode, wherein P trap 6 respectively by PB7,16 and N+ active area 8,15 form PN junction.This longitudinal P NP and horizontal NPN just forms SCR structure (SCR).When applying as shown in Figure 2, port PAD is received in the P+ active area 12 in N-diffusion region 9, N+ active area 11 and 13, and GND is received in the P+ active area 5,17 in P trap and the N+ active area 8 and 17 in PB.When esd event occurs, port voltage reaches the puncture voltage (puncture voltage between N-diffusion region and P trap needs lower than internal circuit device puncture voltage, higher than port normal working voltage) of N-diffusion region 9 and P trap 6, and the knot between N-diffusion region 9 and P trap 6 is breakdown.P trap has pulse current injectingt, and voltage is elevated, and horizontal NPN pipe conducting, whole SCR structure is triggered, ESD electric current of releasing.When port voltage drops to lower than junction breakdown voltage between N-diffusion region 9 and P trap 6, SCR structure is closed, and only has minimum insignificant leakage current.Grid oxygen 10 and 14 object of structure shown in Fig. 1 is to make N-diffusion region 9 form weak transoid, thus reduces the puncture voltage of N-active area and P trap, reduces the trigger voltage of SCR structure.But as can be seen from its equivalent electric circuit Fig. 2, this structure is also inapplicable and need the port of resistance to negative pressure.When PAD voltage is lower than GND0.7V, the diode forward conducting formed by P trap and N-diffusion region in Fig. 2, produces big current between PAD and GND, causes chip operation abnormal.
The present invention can support that port working is in positive/negative-pressure state, has good ESD ability simultaneously.Its cross-section structure as shown in Figure 3.This structure comprises P type substrate 1, N-type buried layer 2,38, and N-type buried layer is received power supply potential and P trap 6,13 respectively by N trap 3,19,33,37 and N+ active area 4,18,21,36 and formed and isolate.When applying, N+ active area 4,18,21,36 all connects power supply, P+ active area 29 ground connection, and active area 11,12,13 meets port PAD, active area 5,8,15,17, grid oxygen 10,14 and active area 24,26,33,35, together with grid oxygen 28,32 receives, active area 29,30,31 ground connection.Equivalent electric circuit as shown in Figure 4.Each triode generation type in this equivalent electric circuit is the same with Fig. 1.When esd event occurs, when the voltage on PAD is greater than the puncture voltage between N-diffusion region and P trap (the puncture voltage needs between N-diffusion region and P trap are lower than internal circuit device puncture voltage, higher than port normal working voltage), SCR1 shown in Fig. 4 is triggered, P trap in SCR2 and the diode forward conducting of N-diffusion region, ESD electric current flows on GND by being reversed the SCR2 puncturing SCR1 and the forward conduction set out.When port voltage is less than the puncture voltage between N-diffusion region and P trap lower than GND current potential, absolute value, SCR2 can not be triggered, and wholely forms ESD structure by SCR2 and SCR1 and does not have leakage current, can not impact work port under negative pressure; When esd event occurs, when port voltage is greater than the puncture voltage between N-diffusion region and P trap lower than GND current potential, absolute value, N-diffusion region in SCR2 and the diode of P trap breakdown, SCR2 is triggered, P trap in SCR1 and the diode forward conducting of N-diffusion region, ESD electric current flows out from PAD port.
The present invention adopts the technique of typical BCDMOS0.5um, port voltage scope-24V ~ 31V, the ESD ability 4000V of support.
Those skilled in the art will readily understand; the foregoing is only preferred embodiment of the present invention; not in order to limit the present invention, all any amendments done within the spirit and principles in the present invention, equivalent replacement and improvement etc., all should be included within protection scope of the present invention.
Claims (6)
1. based on a port ESD structure for the resistance to positive or negative high voltage of SCR structure, it is characterized in that, comprise P type substrate (1), the first N-type buried layer (2) and the second N-type buried layer (38); Described first N-type buried layer (2) is received power supply potential and is formed with a P trap (6) with a N+ active area (4), the 2nd N+ active area (18) by a N trap (3), the 2nd N trap (19) respectively and isolates; Described second N-type buried layer (38) is received power supply potential and is formed with the 2nd P trap (13) with the 3rd N+ active area (21), the 4th N+ active area (36) by the 3rd N trap (33), the 4th N trap (37) respectively and isolates;
During application, a described N+ active area (4), described 2nd N+ active area (18), described 3rd N+ active area (21) and described 4th N+ active area (36) all connect power supply; P+ active area (29) ground connection, active area (11,12,13) meets port PAD, active area (5,8,15,17), grid oxygen (10,14) and active area (24,26,33,35), grid oxygen (28,32) are received together, active area (29,30,31) ground connection.
2. based on an equivalent electric circuit for port ESD structure according to claim 1, it is characterized in that, comprise the first triode Q1, the second triode Q2, the 3rd triode Q3, the 4th triode Q4, the first resistance R1, the second resistance R2 and the 3rd resistance R3;
The emitter of described first triode Q1 is connected to the base stage of described first triode Q1 by the first resistance R1, the collector electrode of described first triode Q1 is connected to the collector electrode of described 4th triode Q4 by the second resistance R2 of being sequentially connected in series and the 3rd resistance R3; The grounded emitter of described 4th triode Q4;
The base stage of described second triode Q2 is connected to the link of described first triode Q1 and described resistance R2, the collector electrode of described second triode Q2 is connected to the base stage of described first triode Q1, and the emitter of described second triode Q2 is connected to the emitter of described 3rd triode Q3;
Described second resistance R2 and described 3rd resistance R3 is connected in series the link that end is connected to described second triode Q2 and described 3rd triode Q3;
The base stage of described 3rd triode Q3 is connected to the collector electrode of described 4th triode Q4, and the base stage of described 4th triode Q4 is connected rear also ground connection with the collector electrode of described 3rd triode Q3.
3. equivalent electric circuit as claimed in claim 2, it is characterized in that, described first triode Q1, described second triode Q2, described first resistance R1 and described second resistance R2 constitute the first SCR structure SCR1; Described 3rd triode Q3, described 4th triode Q4 and described 3rd resistance R3 constitute the second SCR structure SCR2.
4. equivalent electric circuit as claimed in claim 3, is characterized in that, when an esd event occurs, when the voltage on PAD is greater than the puncture voltage between N-diffusion region and P trap; Described first SCR structure SCR1 is triggered, the P trap in described second SCR structure SCR2 and the diode forward conducting of N-diffusion region, and ESD electric current flows on GND by being reversed the SCR2 puncturing SCR1 and the forward conduction set out.
5. the equivalent electric circuit as described in claim 3 or 4, it is characterized in that, when port voltage lower than GND current potential and absolute value is less than the puncture voltage between N-diffusion region and P trap time, described second SCR structure SCR2 can not be triggered, wholely form ESD structure by described second SCR structure SCR2 and described first SCR structure SCR1 and do not have leakage current, can not impact work port under negative pressure.
6. the equivalent electric circuit as described in claim 3 or 4 or 5, it is characterized in that, when an esd event occurs, port voltage lower than GND current potential and absolute value is greater than the puncture voltage between N-diffusion region and P trap time, N-diffusion region in described second SCR structure SCR2 and the diode of P trap breakdown, described second SCR structure SCR2 is triggered, and the P trap in described first SCR structure SCR1 and the diode forward conducting of N-diffusion region, ESD electric current flows out from PAD port.
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Cited By (7)
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| CN105957833A (en) * | 2016-05-16 | 2016-09-21 | 深圳市国微电子有限公司 | Low trigger positive and negative voltage resistant silicon controlled rectifier (SCR) electro-static discharge (ESD) protection device and technology method thereof |
| CN105977253A (en) * | 2016-05-16 | 2016-09-28 | 深圳市国微电子有限公司 | Multi-trigger positive and negative voltage resisting SCR ESD protection device and technological method therefor |
| CN106847809A (en) * | 2017-02-23 | 2017-06-13 | 无锡新硅微电子有限公司 | For rectification bridge construction integrated on piece |
| CN108550573A (en) * | 2018-05-29 | 2018-09-18 | 矽力杰半导体技术(杭州)有限公司 | Electrostatic protection device and its manufacturing method |
| CN109494247A (en) * | 2018-12-17 | 2019-03-19 | 无锡麟力科技有限公司 | The two-way interlayer isolation well of low power consumption and high reliability |
| CN113937099A (en) * | 2021-10-13 | 2022-01-14 | 无锡市晶源微电子有限公司 | High holding voltage ESD protection device |
| CN116247007A (en) * | 2023-05-09 | 2023-06-09 | 合肥晶合集成电路股份有限公司 | Method for manufacturing semiconductor device |
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Cited By (12)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN105957833A (en) * | 2016-05-16 | 2016-09-21 | 深圳市国微电子有限公司 | Low trigger positive and negative voltage resistant silicon controlled rectifier (SCR) electro-static discharge (ESD) protection device and technology method thereof |
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| CN109494247A (en) * | 2018-12-17 | 2019-03-19 | 无锡麟力科技有限公司 | The two-way interlayer isolation well of low power consumption and high reliability |
| CN113937099A (en) * | 2021-10-13 | 2022-01-14 | 无锡市晶源微电子有限公司 | High holding voltage ESD protection device |
| CN113937099B (en) * | 2021-10-13 | 2022-10-11 | 无锡市晶源微电子有限公司 | High holding voltage ESD protection device |
| CN116247007A (en) * | 2023-05-09 | 2023-06-09 | 合肥晶合集成电路股份有限公司 | Method for manufacturing semiconductor device |
| CN116247007B (en) * | 2023-05-09 | 2023-09-12 | 合肥晶合集成电路股份有限公司 | Method for manufacturing semiconductor device |
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