CN113937099A - High holding voltage ESD protection device - Google Patents
High holding voltage ESD protection device Download PDFInfo
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- CN113937099A CN113937099A CN202111190949.9A CN202111190949A CN113937099A CN 113937099 A CN113937099 A CN 113937099A CN 202111190949 A CN202111190949 A CN 202111190949A CN 113937099 A CN113937099 A CN 113937099A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0292—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using a specific configuration of the conducting means connecting the protective devices, e.g. ESD buses
Abstract
The invention relates to a high-maintenance-voltage ESD protection device which comprises a first NMOS (N-channel metal oxide semiconductor) tube (NM1), a second NMOS tube (NM2), a first triode (NPN1), a second triode (NPN2) and a diode (D1), wherein the first NMOS tube (NM1) and the second NMOS tube (NM2) are connected in series, and the first triode (NPN1) and the second triode (NPN2) are connected in series; the drain of the first NMOS tube (NM1), the collector of the first triode (NPN1) and the cathode of the diode (D1) are connected, and the first NMOS tube is connected with a first terminal (PAD 1); the grid electrodes of the first NMOS transistor (NM1) and the second NMOS transistor (NM2), the source electrode of the second NMOS transistor (NM2) and the emitter electrode of the second triode (NPN2) are connected, and the first NMOS transistor (NM1) and the second NMOS transistor (NM2) are connected with the second terminal (PAD 2). The invention greatly improves the holding voltage under the premise of unchanged starting voltage.
Description
Technical Field
The invention relates to a high-maintenance-voltage ESD protection device.
Background
GGMOS (Gate Grounded MOS) is widely used as an ESD protection (electrostatic discharge protection) device in various CMOS integrated circuits, in which NMOS has higher robustness than PMOS, but NMOS has lower holding voltage than PMOS due to larger flyback characteristic. The general 5V GGNMOS has a holding voltage of about 5-6V, which can basically meet the requirement for an integrated circuit operating at 5V, but for an integrated circuit operating above 6V, the low holding voltage may cause the circuit to latch, resulting in circuit burnout.
The series connection structure also improves the starting voltage of the protection structure, so that the protection effect on an internal circuit cannot be achieved, and meanwhile, the area is greatly increased due to the series connection of a plurality of GGNMOSs.
Disclosure of Invention
The invention aims to provide an ESD protection device with high maintenance voltage, which can greatly improve the maintenance voltage on the premise of not changing the starting voltage.
Based on the same inventive concept, the invention has two independent technical schemes:
1. an ESD protection device comprises a first NMOS transistor (NM1), a second NMOS transistor (NM2), a first triode (NPN1), a second triode (NPN2) and a diode (D1),
the first NMOS transistor (NM1) and the second NMOS transistor (NM2) are connected in series, and the first triode (NPN1) and the second triode (NPN2) are connected in series;
the drain of the first NMOS tube (NM1), the collector of the first triode (NPN1) and the cathode of the diode (D1) are connected, and the first NMOS tube is connected with a first terminal (PAD 1);
the grid electrodes of the first NMOS transistor (NM1) and the second NMOS transistor (NM2), the source electrode of the second NMOS transistor (NM2) and the emitter electrode of the second triode (NPN2) are connected, and the first NMOS transistor (NM1) and the second NMOS transistor (NM2) are connected with the second terminal (PAD 2).
Further, the substrate of the first NMOS tube (NM1), the base of the first triode (NPN1) and the anode of the diode (D1) are connected to form a junction A; the substrate of the second NMOS transistor (NM2) and the base of the second triode (NPN2) are connected to form a junction B.
Further, a first resistor (R1) is connected between the junction A and the junction B; a second resistor (R2) is connected between the junction B and the second terminal (PAD 2).
Furthermore, the silicon wafer structure comprises a P trap (102), wherein a first N + diffusion region (103), a second N + diffusion region (104), a third N + diffusion region (105) and a first P + diffusion region (106) are sequentially arranged in the P trap (102) at intervals, a first polycrystal (108) is arranged above a silicon surface between the first N + diffusion region (103) and the second N + diffusion region (104), and a second polycrystal (109) is arranged above a silicon surface between the second N + diffusion region (104) and the third N + diffusion region (105).
Further, the first N + diffusion region (103), the second N + diffusion region (104), the first poly (108) and the P-well (102) form a first NMOS transistor (NM1), the first N + diffusion region (103) serves as a drain of the first NMOS transistor (NM1), the second N + diffusion region (104) serves as a source of the first NMOS transistor (NM1), the P-well (102) serves as a substrate of the first NMOS transistor (NM1), and the first poly (108) serves as a gate of the first NMOS transistor (NM 1);
the second N + diffusion region (104), the third N + diffusion region (105), the second polycrystal (109) and the P well (102) form a second NMOS transistor (NM2), the second N + diffusion region (104) serves as the drain of the second NMOS transistor (NM2), the third N + diffusion region (105) serves as the source of the second NMOS transistor (NM2), the P well (102) serves as the substrate of the second NMOS transistor (NM2), and the second polycrystal (109) serves as the gate of the second NMOS transistor (NM 2).
Furthermore, a parasitic tube formed by the first N + diffusion region (103), the second N + diffusion region (104) and the P well (102) is used as a first triode (NPN1), the first N + diffusion region (103) is used as a collector of the first triode (NPN1), and the second N + diffusion region (104) is used as an emitter of the first triode (NPN 1);
the parasitic tube formed by the second N + diffusion region (104), the third N + diffusion region (105) and the P well (102) is used as a second triode (NPN2), the second N + diffusion region (104) is used as a collector of the second triode (NPN2), and the third N + diffusion region (105) is used as an emitter of the second triode (NPN 2).
Further, in a region of the P well (102) between the first P + diffusion region (106) and the first N + diffusion region (103), a parasitic diode is formed as a diode (D1), and parasitic resistances are formed as a first resistance (R1) and a second resistance (R2).
Further, the first N + diffusion region (103) is connected to a first terminal (PAD 1); the first poly (108), the second poly (109), the third N + diffusion region (105), and the first P + diffusion region (106) are all connected to a second terminal (PAD 2).
Furthermore, the P well (102) is diffused in the deep N well (101), a fourth N + diffusion region (107) is arranged in the deep N well (101), and the fourth N + diffusion region (107) is connected with the first terminal (PAD 1); the deep N-well (101) is diffused within the silicon substrate (100).
2. A high sustaining voltage ESD protection device comprising at least 2 of said devices, each device being connected in series with the second terminal of one device terminating the first terminal of the other device.
The invention has the following beneficial effects:
the breakdown voltage of the diode (D1) is the same as that of a single GGNMOS, so that the starting voltage of the ESD structure is close to that of the single GGNMOS, and an internal circuit can be effectively protected; the maintaining voltage is equivalent to the sum of two single GGNMOS, so that the maintaining voltage is greatly improved, and stronger ESD robustness is kept; meanwhile, the area of the device is only slightly increased compared with that of a single GGNMOS (gate-oxide-semiconductor transistor), and is far smaller than the sum of the areas of the two GGNMOSs; the deep N well completely isolates the P well from the silicon substrate, and the ESD protection with higher maintenance voltage can be realized through a plurality of ESD protection devices.
Drawings
FIG. 1 is a schematic diagram of an equivalent circuit according to a first embodiment of the present invention;
FIG. 2 is a schematic structural diagram according to a first embodiment of the present invention;
FIG. 3 is a TLP graph of the present invention and a conventional GGNMOS;
FIG. 4 is an equivalent circuit diagram of a second embodiment of the present invention; (ii) a
Fig. 5 is a schematic structural diagram of a second embodiment of the present invention.
Detailed Description
The present invention is described in detail with reference to the embodiments shown in the drawings, but it should be understood that these embodiments are not intended to limit the present invention, and those skilled in the art should understand that functional, methodological, or structural equivalents or substitutions made by these embodiments are within the scope of the present invention.
The first embodiment is as follows:
as shown in fig. 1, the ESD protection device includes a first NMOS transistor NM1, a second NMOS transistor NM2, a first transistor NPN1, a second transistor NPN2, and a diode D1, wherein the first NMOS transistor NM1 and the second NMOS transistor NM2 are connected in series, and the first transistor NPN1 and the second transistor NPN2 are connected in series; the drain of the first NMOS tube NM1, the collector of the first triode NPN1 and the cathode of the diode D1 are connected, and the first NMOS tube NM1 is connected with the first terminal PAD 1; the grid electrodes of the first NMOS tube NM1 and the second NMOS tube NM2, the source electrode of the second NMOS tube NM2 and the emitter electrode of the second triode NPN2 are connected, and the first NMOS tube NM1 and the second NMOS tube NM2 are connected with the second terminal PAD 2. The substrate of a first NMOS tube NM1, the base of a first triode NPN1 and the anode of a diode D1 are connected to form a junction A; the substrate of the second NMOS transistor NM2 and the base of the second triode NPN2 are connected to form a junction B. A first resistor R1 is connected between the junction A and the junction B; and a second resistor R2 is connected between the junction B and the second terminal PAD 2.
As shown in fig. 2, the P-well 102 is included, a first N + diffusion region 103, a second N + diffusion region 104, a third N + diffusion region 105 and a first P + diffusion region 106 are sequentially arranged in the P-well 102 at intervals, a first polycrystal 108 is arranged above a silicon surface between the first N + diffusion region 103 and the second N + diffusion region 104, and a second polycrystal 109 is arranged above a silicon surface between the second N + diffusion region 104 and the third N + diffusion region 105. The first N + diffusion region 103, the second N + diffusion region 104, the first poly 108 and the P-well 102 constitute a first NMOS transistor NM1, the first N + diffusion region 103 serves as a drain of the first NMOS transistor NM1, the second N + diffusion region 104 serves as a source of the first NMOS transistor NM1, the P-well 102 serves as a substrate of the first NMOS transistor NM1, and the first poly 108 serves as a gate of the first NMOS transistor (NM 1); the second N + diffusion region 104, the third N + diffusion region 105, the second poly 109, and the P-well 102 constitute a second NMOS transistor NM2, the second N + diffusion region 104 serves as a drain of the second NMOS transistor NM2, the third N + diffusion region 105 serves as a source of the second NMOS transistor NM2, the P-well 102 serves as a substrate of the second NMOS transistor NM2, and the second poly 109 serves as a gate of the second NMOS transistor NM 2. A parasitic tube formed by the first N + diffusion region 103, the second N + diffusion region 104 and the P-well 102 is used as a first triode NPN1, the first N + diffusion region 103 is used as a collector of the first triode NPN1, and the second N + diffusion region 104 is used as an emitter of the first triode NPN 1; the parasitic transistor formed by the second N + diffusion region 104, the third N + diffusion region 105 and the P-well 102 serves as a second transistor NPN2, the second N + diffusion region 104 serves as a collector of the second transistor NPN2, and the third N + diffusion region 105 serves as an emitter of the second transistor NPN 2. In the region of the P well 102 between the first P + diffusion region 106 and the first N + diffusion region 103, a parasitic diode is formed as the diode D1, and parasitic resistances are formed as the first resistor R1 and the second resistor R2. The first N + diffusion region 103 is connected to a first terminal PAD 1; the first poly 108, the second poly 109, the third N + diffusion region 105, and the first P + diffusion region 106 are all connected to a second terminal PAD 2. The P well 102 is diffused in the deep N well 101, a fourth N + diffusion region 107 is arranged in the deep N well 101, and the fourth N + diffusion region 107 is connected with a first terminal PAD 1; the deep N-well 101 is diffused within the silicon substrate 100.
When the ESD protection structure is used for ESD protection of an integrated circuit, the first terminal PAD1 is connected with a high level, the second terminal PAD2 is connected with a low level (grounded), and the gates of the first NMOS transistor NM1 and the second NMOS transistor NM2 are connected with the second terminal PAD2, so that the ESD protection structure does not work when the integrated circuit works normally. When static electricity occurs, as the voltage of the PAD1 at the first terminal rises, the diode D1 breaks down, the breakdown voltage is the same as that of a single conventional GGMOS, current flows through the first resistor R1 and the second resistor R2, and then the first triode NPN1 and the second triode NPN2 are conducted, so that the effect of discharging ESD energy is achieved. The flyback occurs after the first triode NPN1 and the second triode NPN2 are conducted, because the first triode NPN1 and the second triode NPN2 are connected in series, the maintaining voltage from the first terminal PAD1 to the second terminal PAD2 is close to the sum of the maintaining voltage of the first triode NPN1 and the second triode NPN2, the maintaining voltage is 9.5V-10.5V and is far higher than the maintaining voltage of a single conventional GGNMOS, and meanwhile, the strong ESD robustness of the conventional GGNMOS is kept. As shown in fig. 3, the TLP curves of the conventional GGNMOS and the ESD protection device of the invention are shown, the holding voltage of the conventional GGNMOS is about 5.5V, and the holding voltage of the ESD protection device of the invention is about 10V, so that the large improvement is realized, and the failure current It2 is equivalent to that of the conventional GGMOS, and the TLP curves have strong robustness.
Example two:
an ESD protection device comprising at least 2 devices of the structure of the embodiment, the devices being connected in series with each other, the second terminal of one device being terminated to the first terminal of another device. As shown in fig. 4 and 5, in the second embodiment, two ESD protection devices having the structure of the second embodiment are used. As shown in fig. 4, another ESD protection device includes a third NMOS transistor NM21, a fourth NMOS transistor NM22, a third transistor NPN21, a fourth transistor NPN22, a second diode D21, a third resistor R21, and a fourth resistor R22. As shown in fig. 5, another ESD protection device structure includes a deep N-well 121, a P-well 122, N + diffusion regions 123, 124, 125, 127, and poly 128, 129. The serial maintaining voltage is the maintaining voltage of a single NPN tube multiplied by the number of NPN, and in this embodiment, the maintaining voltage is the sum of the maintaining voltages of two ESD protection devices, and reaches about 20V.
It will be evident to those skilled in the art that the invention is not limited to the details of the foregoing illustrative embodiments, and that the present invention may be embodied in other specific forms without departing from the spirit or essential attributes thereof. The present embodiments are therefore to be considered in all respects as illustrative and not restrictive, the scope of the invention being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein.
Claims (10)
1. An ESD protection device is characterized by comprising a first NMOS transistor (NM1), a second NMOS transistor (NM2), a first triode (NPN1), a second triode (NPN2) and a diode (D1),
the first NMOS transistor (NM1) and the second NMOS transistor (NM2) are connected in series, and the first triode (NPN1) and the second triode (NPN2) are connected in series;
the drain of the first NMOS tube (NM1), the collector of the first triode (NPN1) and the cathode of the diode (D1) are connected, and the first NMOS tube is connected with a first terminal (PAD 1);
the grid electrodes of the first NMOS transistor (NM1) and the second NMOS transistor (NM2), the source electrode of the second NMOS transistor (NM2) and the emitter electrode of the second triode (NPN2) are connected, and the first NMOS transistor (NM1) and the second NMOS transistor (NM2) are connected with the second terminal (PAD 2).
2. The ESD protection device of claim 1, wherein: a first NMOS tube (NM1) substrate, a first triode (NPN1) base electrode and a diode (D1) anode are connected to form a junction A; the substrate of the second NMOS transistor (NM2) and the base of the second triode (NPN2) are connected to form a junction B.
3. The ESD protection device of claim 2, wherein: a first resistor (R1) is connected between the junction A and the junction B; a second resistor (R2) is connected between the junction B and the second terminal (PAD 2).
4. The ESD protection device of claim 1, wherein: the silicon surface between the first N + diffusion region (103) and the second N + diffusion region (104) is provided with a first polycrystal (108), and the silicon surface between the second N + diffusion region (104) and the third N + diffusion region (105) is provided with a second polycrystal (109).
5. The ESD protection device of claim 4, wherein: the first N + diffusion region (103), the second N + diffusion region (104), the first polycrystal (108) and the P well (102) form a first NMOS transistor (NM1), the first N + diffusion region (103) serves as the drain of the first NMOS transistor (NM1), the second N + diffusion region (104) serves as the source of the first NMOS transistor (NM1), the P well (102) serves as the substrate of the first NMOS transistor (NM1), and the first polycrystal (108) serves as the grid of the first NMOS transistor (NM 1);
the second N + diffusion region (104), the third N + diffusion region (105), the second polycrystal (109) and the P well (102) form a second NMOS transistor (NM2), the second N + diffusion region (104) serves as the drain of the second NMOS transistor (NM2), the third N + diffusion region (105) serves as the source of the second NMOS transistor (NM2), the P well (102) serves as the substrate of the second NMOS transistor (NM2), and the second polycrystal (109) serves as the gate of the second NMOS transistor (NM 2).
6. The ESD protection device of claim 4, wherein:
a parasitic tube formed by the first N + diffusion region (103), the second N + diffusion region (104) and the P well (102) is used as a first triode (NPN1), the first N + diffusion region (103) is used as a collector of the first triode (NPN1), and the second N + diffusion region (104) is used as an emitter of the first triode (NPN 1);
the parasitic tube formed by the second N + diffusion region (104), the third N + diffusion region (105) and the P well (102) is used as a second triode (NPN2), the second N + diffusion region (104) is used as a collector of the second triode (NPN2), and the third N + diffusion region (105) is used as an emitter of the second triode (NPN 2).
7. The ESD protection device of claim 4, wherein:
in a region of the P-well (102) between the first P + diffusion region (106) and the first N + diffusion region (103), a parasitic diode is formed as a diode (D1), and parasitic resistances are formed as a first resistance (R1) and a second resistance (R2).
8. The ESD protection device of claim 4, wherein: the first N + diffusion region (103) is connected to a first terminal (PAD 1); the first poly (108), the second poly (109), the third N + diffusion region (105), and the first P + diffusion region (106) are all connected to a second terminal (PAD 2).
9. The ESD protection device of claim 4, wherein: the P well (102) is diffused in the deep N well (101), a fourth N + diffusion region (107) is arranged in the deep N well (101), and the fourth N + diffusion region (107) is connected with a first terminal (PAD 1); the deep N-well (101) is diffused within the silicon substrate (100).
10. An ESD protection device characterized by: comprising at least 2 ESD protection devices according to any of claims 1 to 9, the devices being connected in series with each other.
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| US5455436A (en) * | 1994-05-19 | 1995-10-03 | Industrial Technology Research Institute | Protection circuit against electrostatic discharge using SCR structure |
| US20020130365A1 (en) * | 2001-03-14 | 2002-09-19 | Chartered Semiconductor Manufacturing Ltd. | Novel UMOS-like gate-controlled thyristor structure for ESD protection |
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Address after: No. 5, Xijin Road, Xinwu District, Wuxi City, Jiangsu Province, 214028 Patentee after: Wuxi Jingyuan Microelectronics Co.,Ltd. Address before: Room 209, building a, block 106-c, national high tech Industrial Development Zone, Wuxi City, Jiangsu Province, 214028 Patentee before: Wuxi Jingyuan Microelectronics Co.,Ltd. |