CN104682879A - Fully-differential low noise amplifier - Google Patents
Fully-differential low noise amplifier Download PDFInfo
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- CN104682879A CN104682879A CN201310610709.9A CN201310610709A CN104682879A CN 104682879 A CN104682879 A CN 104682879A CN 201310610709 A CN201310610709 A CN 201310610709A CN 104682879 A CN104682879 A CN 104682879A
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Abstract
The invention discloses a fully-differential low noise amplifier. The fully-differential low noise amplifier comprises a differential cascode CMOS (Complementary Metal-Oxide-Semiconductor Transistor) amplifier, wherein the sources of common-source input tubes are connected with the two ends of a first inductor respectively; the inductance value middle point of the first inductor is grounded through a first resistor; the grids of common-gate tubes are connected to an identical bias voltage; the drains of the common-gate tubes are connected with an output load network, and output a pair of differential radiofrequency amplifying signals; the drains of the common-gate tubes are further connected to a four-phase fully-differential RC orthogonal signal generating circuit; and the four-phase fully-differential RC orthogonal signal generating circuit converts the pair of differential radiofrequency amplifying signals into four-phase orthogonal output signals. Through adoption of the fully-differential low noise amplifier, output of a fully-differential four-phase orthogonal signal can be realized, and the noise figure can be lowered below 1dB. The fully-differential low noise amplifier can be widely applied to an image rejection receiver.
Description
Technical field
The present invention relates to a kind of semiconductor integrated circuit, particularly relate to a kind of fully differential low noise amplifier.
Background technology
As shown in Figure 1, be existing band source electrode degeneracy inductance fully differential low noise amplifier structure chart; NMOS tube 101 and 102 is a pair difference common source input pipe, PMOS 103 and 104 is to common bank tube, NMOS tube 101 and PMOS 103 form a road cascade cmos amplifier, NMOS tube 102 and PMOS 104 form another road cascade cmos amplifier, two-way cascade cmos amplifier composition difference cascode cmos amplifier.
NMOS tube 101 with 102 source electrode be connected a feedback inductance Ls respectively, two feedback inductance Ls connect current source Ibias, form input resonant network between the grid source electric capacity of feedback inductance Ls and NMOS tube 101 and 102, and obtain a true impedance to realize the coupling of input impedance.
Differential input signal Vin is respectively by 50ohm(ohm) signal resistance, capacitance Cb and inductance L g be input to the grid of NMOS tube 101 and 102.Inductance L g further adjusts inductance for inputting tuning providing.
The grid of PMOS 103 and 104 is directly biased by supply voltage VDD, realizes common gate configuration; Connect choke induction Ld between the source electrode of PMOS 103 and 104 and supply voltage VDD, the source electrode of PMOS 103 and 104 exports a pair differential output signal VOUT.
Mirror image suppresses the image-reject mixer in receiver to require to produce the low noise amplifier of quadrature phase signal, existing band source electrode degeneracy inductance fully differential low noise amplifier as shown in Figure 1 can only export a pair differential signal Vout, cannot be applied to mirror image and suppress in receiver.
Summary of the invention
Technical problem to be solved by this invention is to provide a kind of fully differential low noise amplifier, can realize fully differential four phase orthogonal signalling and export, noise factor (Noise figure, NF) can be reduced to below 1dB, can be widely used in mirror image and suppress in receiver.
For solving the problems of the technologies described above, fully differential low noise amplifier provided by the invention comprises:
Difference cascode cmos amplifier, comprises the first NMOS tube, the second NMOS tube, the 3rd NMOS tube and the 4th NMOS tube.
Described first NMOS tube and described second NMOS tube are a pair difference common source input pipe, and described first NMOS tube is connected a pair differential radio frequency input signal with the grid of described second NMOS tube; Described first NMOS tube is connected the two ends of the first inductance respectively with the source electrode of described second NMOS tube, and the inductance value mid point of described first inductance is by the first grounding through resistance.
Described 3rd NMOS tube and described 4th NMOS tube are a pair bank tube altogether, the grid of described 3rd NMOS tube and described 4th NMOS tube all connects the first identical bias voltage, the source electrode of described 3rd NMOS tube connects the drain electrode of described first NMOS tube, and the source electrode of described 4th NMOS tube connects the drain electrode of described second NMOS tube; Described 3rd NMOS tube is connected output loading network with the drain electrode of described 4th NMOS tube; The drain electrode of described 3rd NMOS tube exports positive radio frequency amplifying signal, the drain electrode of described 4th NMOS tube exports anti-phase radio frequency amplifying signal, described positive radio frequency amplifying signal and described anti-phase radio frequency amplifying signal partner differential radio frequency amplifying signal, the drain electrode of described 3rd NMOS tube and described 4th NMOS tube is also connected to four phase fully differential RC orthogonal signalling and produces circuit, and described four phase fully differential RC orthogonal signalling produce circuit and differential radio frequency amplifying signal described in a pair is converted to four phase positive blending output signals.
Described four phase fully differential RC orthogonal signalling produce circuit and comprise the first capacitance group, the second capacitance group, the 3rd capacitance group, the 4th capacitance group, the 5th capacitance group, the 6th capacitance group, the second resistance and the 3rd resistance.
The first end of described first capacitance group connects described positive radio frequency amplifying signal, and the second end of described first capacitance group exports first-phase output signal.
The first end of described second capacitance group connects described anti-phase radio frequency amplifying signal, and the second end of described second capacitance group exports second-phase output signal;
The first end of described 3rd capacitance group connects described positive radio frequency amplifying signal, and the second end of described 3rd capacitance group exports third phase output signal.
The first end of described 4th capacitance group connects described anti-phase radio frequency amplifying signal, and the second end of described 4th capacitance group exports the 4th phase output signal.
Described 5th capacitance group is connected between the second end of described first capacitance group and the second end of described second capacitance group.
Described 6th capacitance group is connected between the second end of described 3rd capacitance group and the second end of described 4th capacitance group.
Described second resistance is connected between the second end of described first capacitance group and the second end of described 3rd capacitance group.
Described 3rd resistance is connected between the second end of described second capacitance group and the second end of described 4th capacitance group.
Further improvement is, second bias voltage is connected to the grid of described first NMOS tube by the first resistor group, described second bias voltage is connected to the grid of described second NMOS tube by the second resistor group, and the link of described second bias voltage and described second resistor group is by the first capacity earth.
Further improvement is, described output loading network comprises the second inductance and the 4th resistance, the drain electrode of described 3rd NMOS tube and described 4th NMOS tube is connected to the two ends of described second inductance, and the inductance value mid point of described second inductance connects supply voltage by described 4th resistance.
Further improvement is, fully differential low noise amplifier also comprises:
The 5th NMOS tube be connected in parallel with described 3rd NMOS tube and the 6th NMOS tube, the 7th NMOS tube be connected in parallel with described 4th NMOS tube and the 8th NMOS tube.
Described 5th NMOS tube is all connected the source electrode of described 3rd NMOS tube with the source electrode of described 6th NMOS tube, and described 7th NMOS tube is all connected the source electrode of described 4th NMOS tube with the source electrode of described 8th NMOS tube;
The grid of described 5th NMOS tube, described 6th NMOS tube, described 7th NMOS tube and described 8th NMOS tube all connects the 3rd bias voltage.
The drain electrode of described 5th NMOS tube connects the drain electrode of described 3rd NMOS tube by the 5th resistance, the drain electrode of described 8th NMOS tube connects the drain electrode of described 4th NMOS tube by the 6th resistance.
The drain electrode of described 6th NMOS tube and described 7th NMOS tube is connected to described supply voltage by the 7th resistance.
The present invention can realize fully differential four phase orthogonal signalling and export, and noise factor can be reduced to below 1dB, can be widely used in mirror image and suppress in receiver.
Accompanying drawing explanation
Below in conjunction with the drawings and specific embodiments, the present invention is further detailed explanation:
Fig. 1 is existing band source electrode degeneracy inductance fully differential low noise amplifier structure chart;
Fig. 2 is embodiment of the present invention fully differential low noise amplifier structure chart;
Fig. 3 is scattering (S) parameters simulation of embodiment of the present invention circuit;
Fig. 4 is the noise factor emulation of embodiment of the present invention circuit.
Embodiment
As shown in Figure 2, be embodiment of the present invention fully differential low noise amplifier structure chart; Embodiment of the present invention fully differential low noise amplifier comprises:
Difference cascode cmos amplifier, comprises the first NMOS tube MN1, the second NMOS tube MN2, the 3rd NMOS tube MN3 and the 4th NMOS tube MN4.
Described first NMOS tube MN1 and described second NMOS tube MN2 is a pair difference common source input pipe, and described first NMOS tube MN1 is connected a pair differential radio frequency input signal RFinp and RFinn with the grid of described second NMOS tube MN2; Described first NMOS tube MN1 is connected the two ends of the first inductance L 1 respectively with the source electrode of described second NMOS tube MN2, and the inductance value mid point of described first inductance L 1 is by the first resistance R1 ground connection VSS, and described in Fig. 2, the first resistance R1 is formed by two resistor coupled in parallel.
Described 3rd NMOS tube MN3 and described 4th NMOS tube MN4 is a pair bank tube altogether, the grid of described 3rd NMOS tube MN3 and described 4th NMOS tube MN4 all meets the first identical bias voltage gatepass, and the grid of described 3rd NMOS tube MN3 and described 4th NMOS tube MN4 is also by electric capacity C2 ground connection VSS.
The source electrode of described 3rd NMOS tube MN3 connects the drain electrode of described first NMOS tube MN1, and the source electrode of described 4th NMOS tube MN4 connects the drain electrode of described second NMOS tube MN2; Described 3rd NMOS tube MN3 is connected output loading network with the drain electrode of described 4th NMOS tube MN4; The drain electrode of described 3rd NMOS tube MN3 exports positive radio frequency amplifying signal, the drain electrode of described 4th NMOS tube MN4 exports anti-phase radio frequency amplifying signal, described positive radio frequency amplifying signal and described anti-phase radio frequency amplifying signal partner differential radio frequency amplifying signal, the drain electrode of described 3rd NMOS tube MN3 and described 4th NMOS tube MN4 is also connected to four phase fully differential RC orthogonal signalling and produces circuit, and described four phase fully differential RC orthogonal signalling produce circuit and differential radio frequency amplifying signal described in a pair is converted to four phase positive blending output signal Ioutp, Ioutn, Qoutp and Qoutn.
Described four phase fully differential RC orthogonal signalling produce circuit and comprise the first capacitance group 1, second capacitance group 2, the 3rd capacitance group 3, the 4th capacitance group 4, the 5th capacitance group 5, the 6th capacitance group 6, second resistance R2 and the 3rd resistance R3.First capacitance group 1 described in the embodiment of the present invention, described second capacitance group 2, described 3rd capacitance group 3, described 4th capacitance group 4, described 5th capacitance group 5 and described 6th capacitance group 6 are formed by 5 Capacitance parallel connections all respectively.
The first end of described first capacitance group 1 connects described positive radio frequency amplifying signal, and the second end of described first capacitance group 1 exports first-phase output signal Ioutp.
The first end of described second capacitance group 2 connects described anti-phase radio frequency amplifying signal, and the second end of described second capacitance group 2 exports second-phase output signal Ioutn.
The first end of described 3rd capacitance group 3 connects described positive radio frequency amplifying signal, and the second end of described 3rd capacitance group 3 exports third phase output signal Qoutp.
The first end of described 4th capacitance group 4 connects described anti-phase radio frequency amplifying signal, and the second end of described 4th capacitance group 4 exports the 4th phase output signal Qoutn.
Described 5th capacitance group 5 is connected between the second end of described first capacitance group 1 and the second end of described second capacitance group 2.
Described 6th capacitance group 6 is connected between the second end of described 3rd capacitance group 3 and the second end of described 4th capacitance group 4.
Described second resistance R2 is connected between the second end of described first capacitance group 1 and the second end of described 3rd capacitance group 3.
Described 3rd resistance R3 is connected between the second end of described second capacitance group 2 and the second end of described 4th capacitance group 4.
Second bias voltage is connected to the grid of described first NMOS tube MN1 by the first resistor group 8, described second bias voltage is connected to the grid of described second NMOS tube MN2 by the second resistor group 7, and the link of described second bias voltage and described second resistor group 7 is by the first electric capacity C1 ground connection VSS.In the embodiment of the present invention, described first resistor group 8 and described second resistor group 7 are all formed by 3 resistant series.
Described output loading network comprises the second inductance L 2 and the 4th resistance R4, the drain electrode of described 3rd NMOS tube MN3 and described 4th NMOS tube MN4 is connected to the two ends of described second inductance L 2, and the inductance value mid point of described second inductance L 2 meets supply voltage VDD by described 4th resistance R4.
The 5th NMOS tube MN5 be connected in parallel with described 3rd NMOS tube MN3 and the 6th NMOS tube MN6, the 7th NMOS tube MN7 be connected in parallel with described 4th NMOS tube MN4 and the 8th NMOS tube MN8.
Described 5th NMOS tube MN5 is connected the source electrode of described 3rd NMOS tube MN3 with the source electrode of described 6th NMOS tube MN6, and described 7th NMOS tube MN7 is connected the source electrode of described 4th NMOS tube MN4 with the source electrode of described 8th NMOS tube MN8.
The grid of described 5th NMOS tube MN5, described 6th NMOS tube MN6, described 7th NMOS tube MN7 and described 8th NMOS tube MN8 all meets the 3rd bias voltage gateatten.The grid of described 5th NMOS tube MN5 and described 6th NMOS tube MN6 is by electric capacity C4 ground connection VSS, and the grid of described 7th NMOS tube MN7 and described 8th NMOS tube MN8 is by electric capacity C5 ground connection VSS.
The drain electrode of described 5th NMOS tube MN5 connects the drain electrode of described 3rd NMOS tube MN3 by the 5th resistance R5, the drain electrode of described 8th NMOS tube MN8 connects the drain electrode of described 4th NMOS tube MN4 by the 6th resistance R6.
The drain electrode of described 6th NMOS tube MN6 and described 7th NMOS tube MN7 is connected to described supply voltage VDD by the 7th resistance R7.
The frequency mixer that mirror image suppresses receiver to use one to have mirror image and suppress, by the relation between the signal needed and unwanted image signal, image signal is eliminated in optical mixing process, therefore the pre-filter that special image signal is eliminated no longer is needed, without the need to considering that mirror image suppresses problem in system structure design process.But mirror image suppresses the image-reject mixer in receiver to require to produce the low noise amplifier of quadrature phase signal, embodiment of the present invention circuit can realize fully differential four phase orthogonal signalling and export, can by noise factor (Noise figure, NF) be reduced to below 1dB, mirror image can be widely used in and suppress in receiver.
In the embodiment of the present invention, the grid of difference common source input pipe MN1 and MN2 provides precision offset to optimize noise factor by resistance capacitance filtering, the source electrode of difference common source input pipe MN1 and MN2 by inductance again terminating resistor to realize source degeneracy inductive resistance negative feedback and realize input resistant matching and improve gain.
Bank tube MN3 and MN4 realizes export resonance coupling by differential inductance and resistance to Vdd altogether.Two altogether bank tube MN3 and MN4 each two transistors through the design of precision offset voltage optimization in parallel and NMOS tube MN5 and MN6 and MN7 and MN8 are less than 1dB to realize noise factor while improving gain and 1dB compression point respectively.Wherein pair of transistor MN6 and MN7 drains, and short circuit meets power vd D by resistance R7 again, other pair of transistor MN5 and MN8 meets power vd D through inductance L 2 and resistance R4 again respectively by resistance R5 and R6, and this structural design adds the adjustable dimension of gain and 1dB compression point.
Last differential radio frequency amplifying signal exports and produces the output of circuit generation orthogonal signalling by four phase fully differential RC orthogonal signalling, and the NF achieving a kind of four phase orthogonal signalling outputs with fully differential is less than the high performance low noise amplifier of 1dB.
Fig. 3 gives S parameter simulation result, includes the curve of S11, S12, S21 and S22 tetra-parameters of S parameter, the known 17.33dB of achieving high-gain basis obtains the reverse isolation of-39.67dB.The known NF=0.542dB of Fig. 4 Noisefigure simulation result achieves the NF being less than 1dB.
Above by specific embodiment to invention has been detailed description, but these are not construed as limiting the invention.Without departing from the principles of the present invention, those skilled in the art also can make many distortion and improvement, and these also should be considered as protection scope of the present invention.
Claims (4)
1. a fully differential low noise amplifier, is characterized in that, comprising:
Difference cascode cmos amplifier, comprises the first NMOS tube, the second NMOS tube, the 3rd NMOS tube and the 4th NMOS tube;
Described first NMOS tube and described second NMOS tube are a pair difference common source input pipe, and described first NMOS tube is connected a pair differential radio frequency input signal with the grid of described second NMOS tube; Described first NMOS tube is connected the two ends of the first inductance respectively with the source electrode of described second NMOS tube, and the inductance value mid point of described first inductance is by the first grounding through resistance;
Described 3rd NMOS tube and described 4th NMOS tube are a pair bank tube altogether, the grid of described 3rd NMOS tube and described 4th NMOS tube all connects the first identical bias voltage, the source electrode of described 3rd NMOS tube connects the drain electrode of described first NMOS tube, and the source electrode of described 4th NMOS tube connects the drain electrode of described second NMOS tube; Described 3rd NMOS tube is connected output loading network with the drain electrode of described 4th NMOS tube; The drain electrode of described 3rd NMOS tube exports positive radio frequency amplifying signal, the drain electrode of described 4th NMOS tube exports anti-phase radio frequency amplifying signal, described positive radio frequency amplifying signal and described anti-phase radio frequency amplifying signal partner differential radio frequency amplifying signal, the drain electrode of described 3rd NMOS tube and described 4th NMOS tube is also connected to four phase fully differential RC orthogonal signalling and produces circuit, and described four phase fully differential RC orthogonal signalling produce circuit and differential radio frequency amplifying signal described in a pair is converted to four phase positive blending output signals;
Described four phase fully differential RC orthogonal signalling produce circuit and comprise the first capacitance group, the second capacitance group, the 3rd capacitance group, the 4th capacitance group, the 5th capacitance group, the 6th capacitance group, the second resistance and the 3rd resistance;
The first end of described first capacitance group connects described positive radio frequency amplifying signal, and the second end of described first capacitance group exports first-phase output signal;
The first end of described second capacitance group connects described anti-phase radio frequency amplifying signal, and the second end of described second capacitance group exports second-phase output signal;
The first end of described 3rd capacitance group connects described positive radio frequency amplifying signal, and the second end of described 3rd capacitance group exports third phase output signal;
The first end of described 4th capacitance group connects described anti-phase radio frequency amplifying signal, and the second end of described 4th capacitance group exports the 4th phase output signal;
Described 5th capacitance group is connected between the second end of described first capacitance group and the second end of described second capacitance group;
Described 6th capacitance group is connected between the second end of described 3rd capacitance group and the second end of described 4th capacitance group;
Described second resistance is connected between the second end of described first capacitance group and the second end of described 3rd capacitance group;
Described 3rd resistance is connected between the second end of described second capacitance group and the second end of described 4th capacitance group.
2. fully differential low noise amplifier as claimed in claim 1, it is characterized in that: the second bias voltage is connected to the grid of described first NMOS tube by the first resistor group, described second bias voltage is connected to the grid of described second NMOS tube by the second resistor group, and the link of described second bias voltage and described second resistor group is by the first capacity earth.
3. fully differential low noise amplifier as claimed in claim 1, it is characterized in that: described output loading network comprises the second inductance and the 4th resistance, the drain electrode of described 3rd NMOS tube and described 4th NMOS tube is connected to the two ends of described second inductance, and the inductance value mid point of described second inductance connects supply voltage by described 4th resistance.
4. fully differential low noise amplifier as claimed in claim 1, is characterized in that: fully differential low noise amplifier also comprises:
The 5th NMOS tube be connected in parallel with described 3rd NMOS tube and the 6th NMOS tube, the 7th NMOS tube be connected in parallel with described 4th NMOS tube and the 8th NMOS tube;
Described 5th NMOS tube is all connected the source electrode of described 3rd NMOS tube with the source electrode of described 6th NMOS tube, and described 7th NMOS tube is all connected the source electrode of described 4th NMOS tube with the source electrode of described 8th NMOS tube;
The grid of described 5th NMOS tube, described 6th NMOS tube, described 7th NMOS tube and described 8th NMOS tube all connects the 3rd bias voltage;
The drain electrode of described 5th NMOS tube connects the drain electrode of described 3rd NMOS tube by the 5th resistance, the drain electrode of described 8th NMOS tube connects the drain electrode of described 4th NMOS tube by the 6th resistance;
The drain electrode of described 6th NMOS tube and described 7th NMOS tube is connected to described supply voltage by the 7th resistance.
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| CN201310610709.9A CN104682879B (en) | 2013-11-26 | 2013-11-26 | Fully differential low-noise amplifier |
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| CN201310610709.9A CN104682879B (en) | 2013-11-26 | 2013-11-26 | Fully differential low-noise amplifier |
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| CN104682879A true CN104682879A (en) | 2015-06-03 |
| CN104682879B CN104682879B (en) | 2017-10-24 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108574463A (en) * | 2017-03-07 | 2018-09-25 | 中芯国际集成电路制造(上海)有限公司 | Low-noise amplifier and RF front-end circuit |
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| CN1433592A (en) * | 1999-12-09 | 2003-07-30 | 艾利森电话股份有限公司 | Demodulating method and equipment in high-speed time-division multiplex packet data transmission |
| CN101656516A (en) * | 2009-07-23 | 2010-02-24 | 复旦大学 | Full-difference CMOS ultra wide band low-noise amplifier |
| CN101771388A (en) * | 2010-03-05 | 2010-07-07 | 上海集成电路研发中心有限公司 | Multi-mode full-difference amplifier |
| US20110092169A1 (en) * | 2009-10-19 | 2011-04-21 | Qualcomm Incorporated | Lr polyphase filter |
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2013
- 2013-11-26 CN CN201310610709.9A patent/CN104682879B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1433592A (en) * | 1999-12-09 | 2003-07-30 | 艾利森电话股份有限公司 | Demodulating method and equipment in high-speed time-division multiplex packet data transmission |
| CN101656516A (en) * | 2009-07-23 | 2010-02-24 | 复旦大学 | Full-difference CMOS ultra wide band low-noise amplifier |
| US20110092169A1 (en) * | 2009-10-19 | 2011-04-21 | Qualcomm Incorporated | Lr polyphase filter |
| CN101771388A (en) * | 2010-03-05 | 2010-07-07 | 上海集成电路研发中心有限公司 | Multi-mode full-difference amplifier |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN108574463A (en) * | 2017-03-07 | 2018-09-25 | 中芯国际集成电路制造(上海)有限公司 | Low-noise amplifier and RF front-end circuit |
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