CN104681480B - The semiconductor power component that there is electrostatic discharge circuit to protect of mask number can be reduced - Google Patents
The semiconductor power component that there is electrostatic discharge circuit to protect of mask number can be reduced Download PDFInfo
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- CN104681480B CN104681480B CN201510103758.2A CN201510103758A CN104681480B CN 104681480 B CN104681480 B CN 104681480B CN 201510103758 A CN201510103758 A CN 201510103758A CN 104681480 B CN104681480 B CN 104681480B
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 75
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 83
- 229920005591 polysilicon Polymers 0.000 claims abstract description 83
- 230000004224 protection Effects 0.000 claims abstract description 52
- 239000000758 substrate Substances 0.000 claims abstract description 40
- 238000002161 passivation Methods 0.000 claims abstract description 15
- 238000000034 method Methods 0.000 claims description 28
- 239000002184 metal Substances 0.000 claims description 27
- 229910052751 metal Inorganic materials 0.000 claims description 27
- 239000012634 fragment Substances 0.000 claims description 19
- 230000008021 deposition Effects 0.000 claims description 14
- 238000004519 manufacturing process Methods 0.000 claims description 14
- 230000015572 biosynthetic process Effects 0.000 claims description 10
- 210000000746 body region Anatomy 0.000 claims description 8
- 238000000059 patterning Methods 0.000 claims description 8
- 239000004020 conductor Substances 0.000 claims 1
- 230000004888 barrier function Effects 0.000 abstract description 11
- 230000003068 static effect Effects 0.000 abstract description 10
- 238000005520 cutting process Methods 0.000 abstract description 5
- 239000010410 layer Substances 0.000 description 73
- 150000002500 ions Chemical class 0.000 description 14
- 238000002513 implantation Methods 0.000 description 13
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical group [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 8
- 239000013078 crystal Substances 0.000 description 6
- 229910052710 silicon Inorganic materials 0.000 description 6
- 239000010703 silicon Substances 0.000 description 6
- 239000002019 doping agent Substances 0.000 description 5
- 230000015556 catabolic process Effects 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 3
- 238000012797 qualification Methods 0.000 description 3
- 238000009792 diffusion process Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000011229 interlayer Substances 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 241000150100 Margo Species 0.000 description 1
- KZNMRPQBBZBTSW-UHFFFAOYSA-N [Au]=O Chemical compound [Au]=O KZNMRPQBBZBTSW-UHFFFAOYSA-N 0.000 description 1
- 230000002159 abnormal effect Effects 0.000 description 1
- 229910001423 beryllium ion Inorganic materials 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 239000005380 borophosphosilicate glass Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 238000001556 precipitation Methods 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 238000009738 saturating Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 238000005496 tempering Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/66734—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the gate electrode, e.g. to form a trench gate electrode
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0255—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using diodes as protective elements
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7803—Vertical DMOS transistors, i.e. VDMOS transistors structurally associated with at least one other device
- H01L29/7808—Vertical DMOS transistors, i.e. VDMOS transistors structurally associated with at least one other device the other device being a breakdown diode, e.g. Zener diode
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7811—Vertical DMOS transistors, i.e. VDMOS transistors with an edge termination structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
- H01L29/0692—Surface layout
- H01L29/0696—Surface layout of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/402—Field plates
- H01L29/404—Multiple field plate structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Abstract
The present invention provides a kind of semiconductor power component being arranged in semi-conductive substrate, and it includes the static discharge of a first part of a patterned polysilicon layer being arranged on the Semiconductor substrate top surface（ESD）Protection circuit.This semiconductor power component further includes a Part II for having patterned ESD polysilicon layers that barrier layer is ion implanted as body, is entered with the body ion for hindering doping and is located at the Semiconductor substrate that the body is ion implanted below barrier layer.In another specific embodiment, the static discharge on the edge of semiconductor subassembly（ESD）Polysilicon layer more covers the Cutting Road on semiconductor subassembly edge, thus a passivation layer is no longer needed when semiconductor subassembly is made, to reduce the mask needed for patterned passivation layer.
Description
This case is divisional application
Original bill title：The semiconductor power component that there is electrostatic discharge circuit to protect of mask number can be reduced
Original bill application number：200880124096.5
Original bill international application no：PCT/US2008/013638
Original bill enters the National Phase in China date：On 06 30th, 2010
Original bill international filing date：On December 12nd, 2008.
Technical field
The present invention is the structure and manufacture method about a kind of semiconductor power component, and particularly relating to one kind can to manufacture
The structure-improved of the semiconductor power component that there is electrostatic discharge circuit to protect of mask number is reduced, to utilize simple step
With relatively low into original making, yield and production reliability are improved.
Background technology
At present to make with static discharge（ESD）The layout of the semiconductor power component of circuit protection has one always
Limitation is exactly the MOS field efficiency transistor with electrostatic discharge circuit protection of prior art（MOSFET）The layout of component
Need to make using seven road masks with layer structure.This seven roads mask includes a groove（trench）Mask, an ESD are covered
Film, a body（body）Mask, a source mask, a contact zone（contact）Mask, a metal mask and a passivation layer
（passivation）Mask.Because needing to use the road masks of Dao Zhe seven in manufacturing process, thus be made step be it is quite cumbersome and
Time-consuming.During with using a mask on processing procedure, the abnormal possibility with product defects of processing procedure will be improved more, and reduction is produced
Achievement.When making the semiconductor power component of layout and layer structure at present, the significant increase of cost of manufacture is not only due to again
Miscellaneous step and processing time demand, also because more mask causes relatively low qualification rate.
As shown in Figure 1A and Figure 1B, it is the sectional view and top view of prior art semiconductor power component, this semiconductor
(PCC) power is, for example, the MOSFET protected with electrostatic discharge circuit.Particularly, this prior art stratiform knot shown in figure
The fabrication steps of structure are to need a body mask to come in borderline region one protection ring of formation with layout.In addition it is also required to a passivation
Layer mask come formed one pass through passivation layer contact hole, for encapsulation connection, wherein passivation layer be covering crystal edge with cutting
Road.
Therefore, there is provided another alternative semiconductor work(for the techno-absence of the invention that above-mentioned prior art is directed to then
The electrostatic protection loop configuration of rate component, under the premise of electrostatic protection efficiency is not influenceed, to exempt by existing layout and stratiform
The limitation of structure.In addition, this new layout can reduce the use demand of mask, therefore simplify fabrication steps, reaching reduces into
This, improves the service life reliability of qualification rate, excellent performance and semiconductor power component.
The content of the invention
The main object of the present invention is providing a kind of partly leading with electrostatic discharge circuit protection for reducing mask number
Body (PCC) power, it in borderline region formation esd protection circuit due to, with having the protection ring around ESD structure peripheries, coming
Improve semiconductor power component to puncture.Another object of the present invention is to provide semiconductor work(that is a kind of brand-new and changing layout
Esd protection circuit on rate component, it is due to forming esd protection circuit in borderline region and being formed not using ESD polysilicon layers
With layout and layer structure, to hinder mask as body, to reach due to removing the demand of a body mask, and simplify processing procedure
Step.The demand of mask is hindered using a body due to removing, fabrication steps, which are simplified, and processing procedure cost is relative is lowered, and produces
The qualification rate of product is also enhanced.Thus the technical problem for the prior art being previously discussed as can also be solved.
In one embodiment, it is another object of the present invention to ESD polysilicon layers covering line of cut and crystal edge, because
This is not needing a passivation layer mask.Outer boundary polysilicon is the epitaxial layer for being connected to substrate in the corner of component, using as
One electric board（field plate）, it is to avoid the border that may be produced ahead of time when polysilicon layer is operated under floating voltage punctures,
Therefore component is made to be operated under higher voltage range.Because borderline region is provided with Floating polysilicon silicon fragment component, so only
It can be solved in the voltage limitation operated under low-voltage therefore also.
In one embodiment, it is pattern it is another object of the present invention to the outer boundary polysilicon hindered as body
Turn between several epitaxial layers and device source metal between substrate and sequence connection diode, thus polycrystalline silicon body hinder
Hinder and also serve as the electric board with through the grade bias close to diode, further to prevent early stage border from puncturing.
Briefly include a semiconductor power group in semi-conductive substrate in specific embodiment of the invention
Part.This semiconductor power component includes a static discharge（ESD）Protection circuit, it is arranged at one and is located at semiconductor substrate surface
On patterning ESD polysilicon layers first part.Semiconductor power component further includes the of patterning ESD polysilicon layers
Two parts, it, to hinder the body ion of implantation to enter Semiconductor substrate, is thus reduced as a body implanting ions barrier layer
Body is implanted into mask.In one embodiment, the static discharge on semiconductor substrate surface（ESD）The of polysilicon layer
The Cutting Road at semiconductor subassembly edge is more covered in two parts, and thus semiconductor subassembly no longer needs a passivation layer, therefore reduces
The demand of patterned passivation layer mask.In another specific embodiment, semiconductor power component, which has further included one and is arranged at, partly leads
The metal contact zone in body component corner, the ESD polysilicon layers Part II hindered using connecting as body implanting ions to drain electrode
Voltage, thus the body ion obstruction in semiconductor power component is operated under non-floating voltage.In another specific implementation
In example, the static discharge on semiconductor substrate surface（ESD）If the Part II of polysilicon layer is further patterned
The dry diode between extension interlayer and the sequence connection of source electrode and substrate, to improve border breakdown voltage.Another specific
In embodiment, semiconductor power component has further included an active cell area and a borderline region, is provided with borderline region
And the esd protection circuit on the first part of ESD polysilicon layers is the active cell area relative to semiconductor power component.
In another specific embodiment, the esd protection circuit on ESD polysilicon layer first parts has further included diode, and it has
The first part of the ESD polysilicon layers of doped p-type and N-type.Semiconductor power component has further included a MOSFET components, and it is included
There are a source region being enclosed in using the formed body regions of blanket body implantation and one in body regions, wherein source
Polar region domain is while being formed using a source mask with ESD protection circuit.In another specific embodiment, semiconductor power component
Further include a MOSFET components and the esd protection circuit is more electrically connected to the grid and source electrode of MOSFET components.Another
In specific embodiment, semiconductor power component further includes a protection ring for surrounding esd protection circuit.In another specific embodiment
In, esd protection circuit has further included a resistor fragment on the first part of ESD polysilicon layers.
The present invention also discloses a kind of method for making semiconductor (PCC) power on a semiconductor substrate.This method is included
There is one static discharge of deposition（ESD）Polysilicon layer turns on the surface of Semiconductor substrate, being subsequently patterned this ESD polysilicon layer
One first part and a Part II.This method is further included forms ESD protections on the first part of ESD polysilicon layers
Circuit and obstruction is ion implanted by the use of the Part II of ESD polysilicon layers as body, thus in the system of this semiconductor subassembly
Make to will no longer be required to body implantation mask in method.In another specific embodiment, in precipitation static discharge（ESD）Polysilicon layer
Cutting Road on deposition ESD polysilicon layer covering semiconductor subassemblies edge has been further included in the step on semiconductor substrate surface, by
This will no longer be required to passivation layer in the preparation method of this semiconductor subassembly, with the use for the mask for omitting patterned passivation layer.
In another specific embodiment, the method is further included forms a metal contact zone in the corner of semiconductor subassembly, electrically to connect
Connect and the ESD polysilicon layers Part II of obstruction is ion implanted to drain voltage as body, thus in semiconductor power component,
Obstruction, which is ion implanted, in body is operated under non-floating voltage.In another specific embodiment, formation is used as body ion
If the method for being implanted into the ESD polysilicon layer Part II hindered has further included patterning, the ESD polysilicon layers Part II turns into
Dry p-type and N-type region domain, with the extension interlayer of the source electrode of semiconductor power component and substrate formation sequential close to two
Pole pipe.In another specific embodiment, the step of esd protection circuit is formed on the first part of ESD polysilicon layers further includes
Have on the borderline region relative to the active cell area of semiconductor power component.In another specific embodiment, in ESD polycrystalline
The step of silicon first part formation esd protection circuit, which further includes, applies the bulk doped implantation that a code-pattern body is ion implanted
The step of, then obstruction is ion implanted with body in some of the first part of one source mask of application covering ESD polysilicon layers,
And the first part for the ESD polysilicons that adulterate, to form p-type and the alternate polysilicon of N-type in the Part I of ESD polysilicon layers
Region is used as ESD diode.In another specific embodiment, the step of semiconductor power component formation esd protection circuit more
Include the esd protection circuit of the MOSFET components with esd protection circuit is electrically connected to the source electrodes of MOSFET components with
The step of grid.This method has been further included in another specific embodiment protects to semiconductor power component formation one around ESD
The step of protection ring of protection circuit.In another specific embodiment, the step of forming esd protection circuit has further included many in ESD
The first part one resistor fragment of formation of crystal silicon layer.In another specific embodiment, this method further included deposition with
Static discharge on patterned semiconductor substrate surface（ESD）Several ditches are formed before polysilicon layer using a trench mask
Groove.Deposition with after patterning ESD polysilicon layers, this method further includes the using a covering ESD partial polysilicons layer
The step of source mask of obstruction is ion implanted in a part of and body, it is many in ESD with the first part for the ESD polysilicon layers that adulterate
If forming p-type in the Part I of crystal silicon layer with the alternate polysilicon region of N-type as ESD diode and to body regions
A dry source region is implanted into.This method has been further included to be covered during this semiconductor power component is made using a contact
The step of film, a metal mask and passivation layer mask, therefore completed altogether using six masks.In another specific embodiment
In, this method further includes the static discharge in deposition and patterned semiconductor substrate surface（ESD）Polysilicon layer step
It is preceding that several grooves are formed using a trench mask.It is heavy to have been further included before the step of this deposition is with patterning ESD polysilicon layers
The step of product is with patterning ESD polysilicon layer covering semiconductor power component edge cuts roads.In deposition and patterning ESD polycrystalline
After the step of silicon layer, this method has further included using a source mask, contact mask and a metal mask to make semiconductor
(PCC) power, thus may achieve using only five masks to complete manufacturing process.
It is beneath due to specific embodiment elaborate, when be easier to understand the purpose of the present invention, technology contents, feature and its
The effect reached.
Brief description of the drawings
Figure 1A to Figure 1B is the sectional view that the MOSFET components of esd protection circuit are provided with borderline region of prior art
With top view.
Fig. 2 is walked to use ESD polysilicons fragment to be implanted into barrier layer as body in manufacturing process with reducing mask demand
Rapid has the MOSFET assemble cross-sections that esd protection circuit is protected.
Fig. 3 A, 3B and 3C it show in making of the invention due to using ESD polysilicon layers as body ion for three
Implantation hinders mask to reduce whole top views of the MOSFET components of mask number and the perspective view of two corner regions.
Its three another specific embodiments for the display present invention of Fig. 4 A, 4B and 4C are in making due to using ESD polycrystalline
Silicon layer as body be ion implanted hinder mask with reduce the MOSFET components of mask number whole top views and two corners
The perspective view in region.
Fig. 5 A, 5B and 5C it are three top views to show another tool for further reducing mask quantity of the present invention
There is the specific embodiment of the MOSFET components of esd protection circuit, this right embodiment can improve the operating voltage range of higher range.
It is a series of side sectional view of fabrication steps of MOSFET components to Fig. 6 A to 6J, and mask is reduced to be formed to have
The esd protection circuit of number.
Embodiment
To put it more simply, only proposing groove type gold oxygen half-court effect transistor（MOSFET）It is used as explanation.The present invention can also be answered
For other groove-type power components, such as plane formula (PCC) power.As shown in Fig. 2 it is the MOSFET groups for showing the present invention
The sectional view of part 100, as illustrated, which show borderline region and the active region of part MOSFET components 100, it is to be located at
It is formed with semi-conductive substrate 105, and in Semiconductor substrate 105 by the circumjacent channel grid 120 of body regions 130,
With the source region 135 being enclosed in body regions 130.An oxidation insulating layer 145 is covered with MOSFET components 100, its
With gate contact opening, so that gate metal 140-G passes through gate lead（gate finger）120-F is connected to plough groove type
Grid 120.MOSFET components 100 are protected using ESD diode 125, and ESD diode 125 is generally formed in the top surface of substrate 100
The polysilicon layer of upper deposition.When carrying out body implantation, mask is hindered to body in order to eliminate（body block mask）Need
Ask, in being formed with polysilicon fragment on the top surface of substrate 100（polysilicon segments）125-B, to be hindered as body
Hinder.When through bulk doped is carried out between the intersegmental gap in multi-crystal silicon area, at least one guarantor adulterated with body kenel is formed
Retaining ring 138.As described below, body hinder polysilicon fragment 125-B be commonly referred to as ESD bodies obstruction because they be usually with
ESD polysilicon layers 125 are formed and are made using a special pattern ESD mask etchs together.Body hinders polysilicon fragment
125-B can be floating or be connected directly to drain electrode.As shown in Fig. 2 body hinders multi-chip fragment 125-B to can pass through one
The bulk doped region 139 of source dopant regions 137 and one is connected to drain voltage, and wherein high dose source dopant regions are not exist
Center, with the doping in the bulk doped region for offseting edge, and set up to the connection of drain electrode.
As shown in Fig. 3 A to Fig. 3 C, it is three top views, includes the saturating of the top view of a whole and two corners
Depending on top view, with the layout of display module.As shown in Figure 3A, one is formed around component and connection gate trench pin 120-F
Gate metal, gate trench pin 120-F extends to borderline region by the channel grid of active cell area.Anti-, ditch
Trench-gate runner（trenched gate runner）It is formed at around component and is connected to channel grid pin（In figure not
Show）.The details in corner above the left side as shown in Figure 3 B, esd protection circuit 125 is to pass through the 125-CG connections of ESD- gate contacts
To gate metal 140, with being connected to source metal 140-S through ESD source contacts 125-CS.ESD bodies hinder 125-B can quilt
Extend to the edge of component.Fig. 3 C are identical with Fig. 3 B, with gate metal 140-G and source metal 140-S removal, to show
Beneath layer structure.As illustrated, ESD bodies obstruction can be with patterned one or more long and narrow banding, to be formed such as
Protection ring 138 shown in Fig. 2.
As shown in Fig. 4 A to Fig. 4 C, it is three top views, and Fig. 4 A are whole top views, and Fig. 4 B and Fig. 4 C are two angles
The perspective plan view fallen, with the layout of display module.As shown in Fig. 4 A, gate metal is set around component, grid ditch
Groove pin 120-F extends to borderline region by the channel grid positioned at active cell area.The corner above the left side, ESD is protected
Protection circuit 125 is to be connected to gate metal 140-G through ESD- gate contacts 125-CG, and through ESD- source contacts 125-CS
It is connected to source metal 140-S.ESD bodies hinder 125-B to be extended to the edge of component.Form a polysilicon ring 125-R
Around ESD125, to improve breakdown voltage.Fig. 4 C are identical with Fig. 4 B, with the removal of metal 140, to show the stratiform knot of lower section
Structure.
As shown in Figure 5 A to FIG. 5 C, it is the 3rd alternative specific embodiment of the invention.In fig. 5,
The upper left hand corner of MOSFET components 100 such as Fig. 3 to Fig. 4 layout, plants with ESD polysilicon layers 125-B extensions as body
Enter mask, thus under no longer need body mask in the processing procedure.The grid for being deposited on peripheral border region are not shown in figure
Pole metal 140-G is around component and source metal 140-S covered active cell area.Several more shapes of protection ring 138
Into between polysilicon fragment 125-B.In previous Fig. 3 to Fig. 4 specific embodiment, because being implanted into the polycrystalline hindered as body
Silicon fragment 125-B is float zone, therefore component is restricted to operate under more than a certain voltage.It is such in order to solve
Limitation, therefore the ESD polysilicon layer 125-B that barrier layer is implanted into as body are formed, to cover the edge of component.Further, exist
Corner forms metal contact zone 140-D, to connect body implantation barrier layer 125-B to draining, thus body implantation barrier layer
125-B is being not to be operated under floating state, hence in so that component can be higher than the component voltage limitation described in Fig. 3 to Fig. 4
Operated under voltage range.Protection ring 125-R is around ESD125, to protect esd protection circuit 125 to prevent low pressure from puncturing.Further,
It is covered with the edge of component with Cutting Road by body implantation barrier layer 125, will no longer be required to passivation layer, therefore compared to existing
Seven masks of demand for having technology are even more the quantity required for reducing mask to five masks.Effectively cost savings and product are qualified
Rate is reached.Fig. 5 B are the specific embodiments similar to Fig. 5 A.The different structure of the present embodiment is to be that body obstruction is more with characteristic
Crystal silicon is to be patterned and adulterate to be formed as several bulk doped polysilicon strips（stripes）125-P and source dopant polycrystalline
Silicon strip 125-N, using formed several it is continuous close to polysilicon diode protected as margo, improve edge breakdown.This
It is continuous close to one end of polysilicon diode be to be connected to drain electrode through contact zone 140-D, the other end is to pass through contact zone
125-CS ' is connected to source metal 140-S.Fig. 5 C are another similar specific embodiments for showing the present invention.The difference of this structure
Different is to be to provide an ESD resistors 125-RS to esd protection circuit 125 with function characteristicses, and ESD resistors 1125-RS
It is to be protect by protection ring 160, to improve breakdown voltage.
As shown in Fig. 6 A to Fig. 6 J, it is cutd open for the Making programme step of the MOSFET components with ring-type esd protection circuit
Face schematic diagram.Step starts from providing semi-conductive substrate, and such as one attached epitaxial layer 400 being placed on substrate is formed with thereon
One oxide layer 405.Use a groove photoresistance formula mask（Do not show in figure）It is etched, to form several grooves 410.Then move
Except photoresistance formula mask（Do not show in figure）.In fig. 6b, polysilicon is inserted in deposition in groove 410, then due to blanket
（blanket）Polysilicon back etches the polycrystal layer removed beyond groove 410 to formula.In figure 6 c, using further aoxidizing
Step increases the thickness of oxide layer 405, and then one ESD polysilicon layers 415 of deposition are in the surface of oxide layer 405.In figure 6d, use
ESD masks 418 are etched to polysilicon layer 415, and fragment 415-B is hindered with body implantation to form ESD fragments 415-E.
In Fig. 6 E, ESD masks 418 are removed, and carry out an oxide etch, are hindered with removing to be implanted between ESD fragments 415-E and body
Residual fraction in oxide layer 405 between fragment 415-B, and the surface of substrate 400（reminder portions）.Then, enter
Row tempering.In Fig. 6 F, code-pattern body implantation is carried out to body regions 420.Different from the manufacturing method thereof of prior art, this hair
It is bright no longer to need body mask.Polysilicon fragment 451-B and 415-E is prevented below ion doping to substrate area and substrate table
It with the dopant profile of body is identical that the polysilicon fragment in face, which is, is the doping of p-type state in this example.In Fig. 6 G, enter
Row bulk diffusion step, to spread extension body region 420 to the larger depth of substrate 400.In Fig. 6 H, a source electrode is utilized
ESD masks 425 are implanted into source ion to source region 430 and the n-type doping region 435-N in ESD fragments 415-E.Cause
Higher trial of strength is implanted into using compared to body for source electrode implantation is general, therefore region 435-N is the counting of doped N-type state doping
Device, to form ESD protection diode with the P row types domain 435-P in ESD polysilicon fragments 451-E.Polysilicon fragment 415-
B can at the same time in patterned P and n-quadrant, as shown in Fig. 5 B.Source dopant regions 430-B is adjacent to 415-B regions
Edge, to reduce PN junctions as far as possible, to establish connections to drain region.In Fig. 6 I, source electrode ESD masks 425 are removed, then
A diffusion process is carried out, to spread source region 430.In Fig. 6 J, deposition one includes low-temperature oxidation insulating barrier（LTO）/ boron
Phosphorosilicate glass（BPSG）The insulating barrier 440 of layer, then contacts mask using one（Do not show in figure）It is etched, to form several
Contact zone opening.Contact zone implantation is carried out, to form the contact doping region being located at below contact zone opening.With through contact
When window connects source/body with grid, resistance when being contacted with the metal level 450 on insulating barrier 440 is reduced.Connect body
Polysilicon fragment 415-B is hindered also to be completed to draining within the same time.These steps are patterned using metal mask
Metal level 450 is source/body contacting metal 450-S, ESD contacting metal 450-E and gate liner（Do not show in figure）.
Although present disclosure is discussed in detail by above preferred embodiment, but it should be appreciated that above-mentioned
Description is not considered as limitation of the present invention.After those skilled in the art have read the above, for the present invention's
A variety of modifications and substitutions all will be apparent.Therefore, protection scope of the present invention should be limited to the appended claims.
Claims (8)
1. it is a kind of in the method that semiconductor (PCC) power is made in semi-conductive substrate, it is characterised in that it includes：
In an ESD polysilicon layers are deposited in the Semiconductor substrate and pattern the ESD polysilicon layers as a Part I with
One Part II；And
Formed in the Part I of the ESD polysilicon layers esd protection circuit and by the ESD polysilicon layers this second
Obstruction is ion implanted as a body in part, and a body is thus omitted in the manufacturing method thereof for making the semiconductor power component and is planted
Enter mask；Wherein,
Described has further included in the method that semiconductor (PCC) power is made in semi-conductive substrate：
In deposition with patterning the ESD polysilicon layers in using a trench mask before the step in the Semiconductor substrate, to be formed
Several grooves, then remove the trench mask；
Deposition with pattern the ESD polysilicon layers after, come the first of the covering part ESD polysilicon layers using a source mask
Obstruction is ion implanted with the body in part, with the Part I for the ESD polysilicon layers that adulterate, and the ESD polysilicons this
Formed in a part of by p-type and the alternate ESD diode in N-type polycrystalline silicon region, with several source electrodes in the body regions
Region；And,
Using a contact mask, a metal mask mask, to make the semiconductor power component, thus whole processing procedure are protected with one
Step is completed using six masks.
2. it is as claimed in claim 1 in the method that semiconductor (PCC) power is made in semi-conductive substrate, it is characterised in that
Wherein：
Deposition ESD polysilicon layers covering has been further included the step of the ESD polysilicon layers are deposited in the Semiconductor substrate should be partly
A Cutting Road on conductor assembly edge, is not thus needing one to be passivated in the manufacturing method thereof for making the semiconductor power component
Layer, to omit the mask for forming the passivation layer.
3. it is as claimed in claim 1 in the method that semiconductor (PCC) power is made in semi-conductive substrate, it is characterised in that
Further include：
A metal contact zone is formed in a corner of the semiconductor subassembly, is hindered using being electrically connected with as the body ion doping
The ESD polysilicon layers to the Semiconductor substrate doped region, thus the body ion in the semiconductor power component plant
Entering obstruction is operated under a non-floating voltage.
4. it is as claimed in claim 1 in the method that semiconductor (PCC) power is made in semi-conductive substrate, it is characterised in that
Wherein：
The step of esd protection circuit is formed in the Part I of the ESD polysilicon layers has further included partly is leading relative to this
The esd protection circuit is formed in the borderline region of the active region of body (PCC) power.
5. it is as claimed in claim 1 in the method that semiconductor (PCC) power is made in semi-conductive substrate, it is characterised in that
Wherein：
The step of forming the esd protection circuit in the Part I of the ESD polysilicon layers has further included one code-pattern of implementation
The step of bulk doped that body is ion implanted is implanted into, then applies being somebody's turn to do for the source mask covering part ESD polysilicon layers
Part I is ion implanted with the body, with the Part I for the ESD polysilicon layers that adulterate, makes being somebody's turn to do for the ESD polysilicon layers
Being formed in Part I has p-type and the alternate polysilicon region of N-type.
6. it is as claimed in claim 1 in the method that semiconductor (PCC) power is made in semi-conductive substrate, it is characterised in that
Wherein：
Promising MOSFET components formation is further included before the step of forming the esd protection circuit for the semiconductor power component should
Esd protection circuit, it is the source electrode and a grid for being electrically connected to the MOSFET components.
7. it is as claimed in claim 1 in the method that semiconductor (PCC) power is made in semi-conductive substrate, it is characterised in that
Further include：
The protection ring of the esd protection circuit is surrounded to semiconductor power component formation one.
8. it is as claimed in claim 1 in the method that semiconductor (PCC) power is made in semi-conductive substrate, it is characterised in that
Wherein：
The step of forming the esd protection circuit further includes forms a resistor in the Part I of the ESD polysilicon layers
The step of fragment.
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US12/006,398 US7825431B2 (en) | 2007-12-31 | 2007-12-31 | Reduced mask configuration for power MOSFETs with electrostatic discharge (ESD) circuit protection |
| US12/006,398 | 2007-12-31 | ||
| CN200880124096.5A CN101919042B (en) | 2007-12-31 | 2008-12-12 | Power semiconductor deviceswith reduced mask configuration with electrostatic discharge (ESD) circuit protection |
Related Parent Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN200880124096.5A Division CN101919042B (en) | 2007-12-31 | 2008-12-12 | Power semiconductor deviceswith reduced mask configuration with electrostatic discharge (ESD) circuit protection |
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| Publication Number | Publication Date |
|---|---|
| CN104681480A CN104681480A (en) | 2015-06-03 |
| CN104681480B true CN104681480B (en) | 2017-09-08 |
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| CN200880124096.5A Active CN101919042B (en) | 2007-12-31 | 2008-12-12 | Power semiconductor deviceswith reduced mask configuration with electrostatic discharge (ESD) circuit protection |
| CN201510103697.XA Active CN104617134B (en) | 2007-12-31 | 2008-12-12 | The semiconductor power component that there is electrostatic discharge circuit to protect of mask number can be reduced |
| CN201510103758.2A Active CN104681480B (en) | 2007-12-31 | 2008-12-12 | The semiconductor power component that there is electrostatic discharge circuit to protect of mask number can be reduced |
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| CN200880124096.5A Active CN101919042B (en) | 2007-12-31 | 2008-12-12 | Power semiconductor deviceswith reduced mask configuration with electrostatic discharge (ESD) circuit protection |
| CN201510103697.XA Active CN104617134B (en) | 2007-12-31 | 2008-12-12 | The semiconductor power component that there is electrostatic discharge circuit to protect of mask number can be reduced |
Country Status (4)
| Country | Link |
|---|---|
| US (2) | US7825431B2 (en) |
| CN (3) | CN101919042B (en) |
| TW (1) | TWI427741B (en) |
| WO (1) | WO2009088422A2 (en) |
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Also Published As
| Publication number | Publication date |
|---|---|
| CN104617134B (en) | 2017-11-07 |
| TW200929443A (en) | 2009-07-01 |
| US20090166740A1 (en) | 2009-07-02 |
| CN101919042B (en) | 2015-04-15 |
| CN104681480A (en) | 2015-06-03 |
| TWI427741B (en) | 2014-02-21 |
| US20110076815A1 (en) | 2011-03-31 |
| US7825431B2 (en) | 2010-11-02 |
| CN104617134A (en) | 2015-05-13 |
| US8354316B2 (en) | 2013-01-15 |
| WO2009088422A3 (en) | 2009-12-23 |
| WO2009088422A2 (en) | 2009-07-16 |
| CN101919042A (en) | 2010-12-15 |
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