CN101399267A - Power transistor structure and method for producing the same - Google Patents
Power transistor structure and method for producing the same Download PDFInfo
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- CN101399267A CN101399267A CN 200710153214 CN200710153214A CN101399267A CN 101399267 A CN101399267 A CN 101399267A CN 200710153214 CN200710153214 CN 200710153214 CN 200710153214 A CN200710153214 A CN 200710153214A CN 101399267 A CN101399267 A CN 101399267A
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- power transistor
- transistor structure
- semiconductor layer
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- ditches
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
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- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
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- Electrodes Of Semiconductors (AREA)
Abstract
A power transistor structure of the invention forms a first gate which is positioned in the unit cell area of a grain and a second gate which is positioned in the edge area of the grain in a semiconductor substrate. The first gate and the second gate are electrically connected, and the second gate is connected with a contact wire to be connected to a pad for transmitting a gate control signal. The semiconductor substrate sequentially comprises a first semiconductor layer, a second semiconductor layer and a third semiconductor layer from the surface to the lower part, the first and the third semiconductor layers are a first conductive type (such as n type), the second semiconductor layer is a second conductive type (such as p type), and the first and the third semiconductor layers are respectively taken as a source and a drain of the power transistor.
Description
Technical field
The present invention is about a kind of MOSFET structure and manufacture method, particularly about a kind of power metal oxide semiconductor field-effect transistor (Power Metal OxideSemiconductor Field Effect Transistor; Power MOSFET) structure and manufacture method.
Background technology
Power metal oxide semiconductor field-effect transistor (Power MOSFET) has become the main flow of high-power components, occupy leading position on market.With the development of the electronic installation headed by the computer to the requirement drive Power MOSFET of compactization and high mechanization, this trend is in the ascendant, and technology just constantly progresses greatly.That supports in huge computer market is following, and it is the breakthrough of high-power components that IC development technique personnel adopt single stone (Monolithic) technical elements to facilitate MOS at high-power components.Especially low withstand voltage high-power MOSFET, performance heightens with the raising of the integrated level of its MOS of person.The action of high-power MOSFET is suitable for the application of IC such as drive circuit and protective circuit.
Fig. 1 shows a known Power MOSFET structure 10, and substrate 11 comprises by extension (epi) technology in n
+The n that N-type semiconductor N substrate 12 is grown up
- Type semiconductor layer 13, and utilize the ion injection or be doped in n
-Form p in the type semiconductor layer 13
- Type semiconductor layer 14 and n
+Type semiconductor layer 15.Insert polysilicon in the irrigation canals and ditches of left side and form grid 16 and 17, this n
+ Type semiconductor layer 15 and n
- Type semiconductor layer 13 is respectively as source electrode and drain electrode.Substrate 11 surfaces at the crystal grain on right side (die) edge (peripheral) form a grid 18 in addition, and are connected to a weld pad (bonding pad) by contact wire (contact) 19 and associated metal line, control this grid 16,17 and 18 with transmission signals.
Because of grid 18 is made on substrate 11 surfaces, except grid 18 own needs with the photomask definition, the zone that forms preceding these grid 18 places of this grid 18 (isolates (isolation) zone, no element part) also needs to be defined with photomask, thereby make complex process, and the photomask cost of manufacture can't effectively reduce.
Summary of the invention
The invention provides a kind of Power MOSFET structure and manufacture method,,, and then simplify technology, reduce cost of manufacture with minimizing photomask number by structural change.
Power transistor structure of the present invention will be arranged in the first grid of cell region of a crystal grain and the second grid that is positioned at the marginal zone of this crystal grain all is formed at semiconductor substrate.This first grid and second grid are electrical connected, and this second grid connects a contact wire, to be connected to a weld pad with the transmission grid control signal.This semiconductor substrate comprises one first semiconductor layer, one second semiconductor layer and one the 3rd semiconductor layer downwards from the surface, this the first and the 3rd semiconductor layer is first conductivity type (a for example n type), this second semiconductor layer is second conductivity type (a for example p type), and this first and the 3rd semiconductor layer is respectively as the source electrode and the drain electrode of this power transistor.
In an embodiment who makes above-mentioned power transistor structure, at first in the semiconductor substrate, form these first irrigation canals and ditches and second irrigation canals and ditches, and in these first and second irrigation canals and ditches, insert conductive layer (for example doped polycrystalline silicon) and form first and second grid, wherein this first and second grid electrically connects.Afterwards, form dielectric layer, and form a contact wire and run through this dielectric layer to this second grid in the surface of this first and second grid and this semiconductor substrate.This contact wire can be electrically connected to one first weld pad, with the transmission grid control signal.
Compared to traditional power transistor the grid at crystal grain edge is made in structure on the substrate, the present invention then is formed at grid in the semiconductor substrate simultaneously, therefore need not make the photomask that the definition edge connects the grid of contact wire in addition, and the photomask of definition isolated area (being used to keep the formation to the grid that connects contact wire) also can be omitted.Moreover, at n
+P in edge
-The non-n of matrix
+The zone is to utilize the photomask of contact hole with n
+The zone etching is removed, and utilizes the p of contact hole
+Ion injects and produces a p
+Shading ring (guard ring) is to stablize p
-The voltage of matrix.Therefore, can save 3 road photomasks altogether.
Description of drawings
Fig. 1 is known power transistor structure; And
Fig. 2～12nd, the making schematic flow sheet of power transistor of the present invention.
The main element symbol description
10 Power MOSFET structures, 11 substrates
12 n
+N-type semiconductor N substrate 13 n
-Type semiconductor layer
14 p
-Type semiconductor layer 15 n
+Type semiconductor layer
16 grids, 17 grids
18 grids, 19 contacts wire
20 power transistor structures, 21 n
+The N-type semiconductor N substrate
22 n
- Type semiconductor layer 23 oxide layers
24 irrigation canals and ditches, 25 irrigation canals and ditches
26 sacrificial oxide layers, 27 grid oxic horizons
28 doped polysilicon layers, 29 p
-Type semiconductor layer
30 n
+ Type semiconductor layer 31 is rich in silicon oxide layer
32 oxide layers, 33 openings
34 doped regions, 35 doped regions
36 titanium substrates, 37 tungsten plugs
38 Solder for Al-Cu Joint Welding metal levels, 39 oxide layers
40 nitration cases, 41 grids
42 grids, 43 grids
44 tungsten plugs, 50 semiconductor substrates
51 doped regions, 33 ＇ base stage strip openings
44 ＇ tungsten metal connecting lines
Embodiment
Below will be by the graphic technological innovation place that clearly demonstrates power transistor structure of the present invention and preparation method thereof.
Fig. 2 to Figure 12 shows the manufacture method of the power transistor of one embodiment of the invention.
With reference to Fig. 2, at first in a n
+N-type semiconductor N substrate 21 surfaces utilize extension to form a n
-Type semiconductor layer 22.This n
-The thickness of type semiconductor layer 22 is approximately between 4～4.5 μ m.Afterwards, carry out oxidation technology in 1000 ℃, form the oxide layer 23 of about 6000 dusts.
With reference to Fig. 3, define the irrigation canals and ditches position with photoetching process, carry out etching subsequently and form irrigation canals and ditches 24,25.About 1.2～1.4 μ m of the degree of depth of these irrigation canals and ditches 24,25.The irrigation canals and ditches 24 in left side will form the transistor gate of structure cell, and the irrigation canals and ditches 25 on right side are positioned at the edge of crystal grain.The grid that forms in the future because of irrigation canals and ditches 25 need connect a contact wire, so its width is big than irrigation canals and ditches 24.
With reference to Fig. 4, carry out oxidation technology and remove the oxide layer 23 of part in 1150 ℃, and carry out the sacrificial oxide layer 26 that oxidation forms about 3500 dusts subsequently with buffered hydrofluoric acid (BHF).
With reference to Fig. 5, carry out oxidation in 1000 ℃, and form grid oxic horizons 27, and insert irrigation canals and ditches 24 and 25 with doped polysilicon layer 28 in irrigation canals and ditches 24,25 surfaces.Doped polysilicon layer 28 thickness of present embodiment deposition are 8000 dusts.
With reference to Fig. 6 (a), with cmp or (etching back) mode of eat-backing carry out planarization for doped polysilicon layer 28, and stop at this sacrificial oxide layer 26, and form grid 41,42 and 43.Afterwards sacrificial oxide layer 26 is carried out wet etching to thickness and remain 200 dusts.Fig. 6 (b) is the top view of Fig. 6 (a), the grid 42 and 43 that the grid 41 on right side electrically connects in this cell region.
With reference to Fig. 7, the boron ion is injected this n
-Semiconductor layer 22 forms p
- Type semiconductor layer 29, and under the environment that is mainly nitrogen with 1150 ℃ anneal (Annealing).Then, arsenic ion is injected this p
-(dosage is 8E15atom/cm to type semiconductor layer 29
2), form n
+ Type semiconductor layer 30, as shown in Figure 8.This semiconductor layer 21,22,29 and 30 forms semiconductor substrate 50, and this grid 41,42 and 43 is formed in this semiconductor substrate 50, this n
+ Type semiconductor layer 30 and n
- Type semiconductor layer 22 is respectively as source electrode and drain electrode, this p
-29 of type semiconductor layer are as raceway groove (Channel).
With reference to Fig. 9, remove sacrificial oxide layer 26, strengthen the oxide layer 31 that is rich in silicon (Si-rich) that (Plasma Enhanced) chemical deposition mode forms about 2000 dusts of a thickness with plasma, and form the oxide layer 32 of about 5300 dusts of a thickness in addition, as interlayer dielectric layer (Interlayer dielectric; ILD).This oxide layer 32 is boron-phosphorosilicate glass (Boro-phospho-silicate Glass in the present embodiment; BPSG).
With reference to Figure 10, utilize photolithography techniques etching n
+District 30 forms source electrode opening 33 and base stage strip opening 33 ＇, and with boron fluoride (BF
2) carry out ion injection and annealing, form p
+Doped region 34,35 and 51.This doped region 51 forms a shading ring (guard ring) to stablize p
-The voltage of matrix 29.
With reference to Figure 11 (a) and Figure 11 (b), wherein Figure 11 (b) is the top view of Figure 11 (a).Utilize sputter to form a titanium substrate 36 and anneal in opening 33 and base stage strip opening 33 ＇ surface.In opening 33 and 33 ＇, make conductive connecting line afterwards, insert tungsten plug (W-plug) 37,44 and tungsten metal connecting line 44 ＇ in the present embodiment.Then in the mode of dry ecthing with tungsten plug 37,41 with tungsten metal connecting line 44 ＇ eat-back and determine this no tungsten metal residuals in oxide layer 32 surfaces.This tungsten plug 37 is electrically connected to the weld pad of grid with the transmission grid control signal.This tungsten plug 44 and tungsten metal connecting line 44 ＇ that are connected p zone 51 then are electrically connected to the weld pad of source electrode, with the transmission source control signal.
With reference to Figure 12, the Solder for Al-Cu Joint Welding metal level 38 that forms the about 30～40K dust of a thickness is in this tungsten plug 37 and oxide layer 32 surfaces, and by the in addition etching of required pattern.Afterwards, deposit an oxide layer 39 and a nitration case 40 between adjacent Solder for Al-Cu Joint Welding metal level 38,, and form power transistor structure 20 of the present invention as isolation.
Compared to power transistor shown in Figure 1 the grid at crystal grain edge is made in structure on the substrate, because the present invention is formed at grid 41,42 and 43 in the semiconductor substrate simultaneously, so need not make the photomask of this grid 41 of definition in addition, and the photomask of definition isolated area (being used to keep the formation to grid 41) also can be omitted.Moreover traditional crystal grain (die) edge is the n that asks good
-Matrix contact electrically is required to be the p type around and can not carries out n
-The type ion injects, so need be covered protection is provided in addition, makes need add photomask one in the technology.With reference to Figure 10, the present invention utilizes source electrode contact hole photomask to remove n again
+ District 30 also defines contact hole, so n originally
+Photomask can be omitted.
The present invention can be reduced to 4 roads with 7 traditional road photo-marsk processes, also can reduce by 3 road photo-marsk processes, and is significantly simplified technology and reduce cost.
Technology contents of the present invention and technical characterstic disclose as above, yet the personage who is familiar with this technology still may be based on teaching of the present invention and announcement and done all replacement and modifications that does not deviate from spirit of the present invention.Therefore, protection scope of the present invention should be not limited to those disclosed embodiments, and should comprise various do not deviate from replacement of the present invention and modifications, and is contained by claim.
Claims (23)
1, a kind of power transistor structure comprises:
At least one first grid, it is positioned at the cell region of crystal grain, and is formed in the semiconductor substrate;
At least one second grid, it is positioned at the marginal zone of this crystal grain, and is formed in this semiconductor substrate;
Wherein this first grid and second grid are electrical connected, and this second grid connection contact wire, to be connected to first weld pad with the transmission grid control signal.
2, according to the power transistor structure of claim 1, wherein comprise grid oxic horizon between this first and second grid and this semiconductor substrate.
3, according to the power transistor structure of claim 1, wherein this contact wire is a tungsten plug.
4, according to the power transistor structure of claim 3, wherein comprise the titanium substrate between this tungsten plug and this second grid.
5, according to the power transistor structure of claim 3, wherein this tungsten plug is connected to the Solder for Al-Cu Joint Welding metal level.
6, according to the power transistor structure of claim 3, wherein this tungsten plug bottom connects ion implanted region.
7, according to the power transistor structure of claim 1, wherein this semiconductor substrate comprises first semiconductor layer, second semiconductor layer and the 3rd semiconductor layer downwards from the surface, this the first and the 3rd semiconductor layer is first conductivity type, this second semiconductor layer is second conductivity type, and this first and the 3rd semiconductor layer is respectively as the source electrode and the drain electrode of this power transistor.
8, according to the power transistor structure of claim 7, wherein this first semiconductor layer is electrically connected to second weld pad with conductive connecting line, with the transmission source control signal.
9, power transistor structure according to Claim 8, wherein this conductive connecting line is a tungsten plug.
10, according to the power transistor structure of claim 9, wherein this tungsten plug bottom connects ion implanted region.
11, according to the power transistor structure of claim 7, it comprises a shading ring in addition and is formed in this second semiconductor layer, and this shading ring is this second conductivity type, and opposite with the polarity of this second semiconductor layer.
12, according to the power transistor structure of claim 11, wherein this shading ring is electrically connected to second weld pad by metal connecting line, with the transmission source control signal.
13, a kind of manufacture method of power transistor structure comprises:
Form at least the first irrigation canals and ditches and at least one second irrigation canals and ditches in semiconductor substrate, wherein these first irrigation canals and ditches are positioned at cell region, and these second irrigation canals and ditches are positioned at the edge of crystal grain;
Insert conductive layer and form first and second grid in these first and second irrigation canals and ditches, wherein this first and second grid electrically connects;
Form dielectric layer in the surface of this first and second grid and this semiconductor substrate; And
Formation runs through the contact wire of this dielectric layer to this second grid, and this contact wire is electrically connected to first weld pad, with the transmission grid control signal.
14, according to the manufacture method of the power transistor structure of claim 13, wherein the width of these second irrigation canals and ditches is greater than the width of first irrigation canals and ditches.
15, according to the manufacture method of the power transistor structure of claim 13, wherein the degree of depth of these first and second irrigation canals and ditches is between 1.2～1.4 μ m.
16, according to the manufacture method of the power transistor structure of claim 13, wherein this first and second grid be by in these first and second irrigation canals and ditches, insert polysilicon and in addition planarization make.
17, according to the manufacture method of the power transistor structure of claim 16, wherein planarization is to utilize cmp.
18, according to the manufacture method of the power transistor structure of claim 13, wherein this semiconductor substrate comprises by surface downward first semiconductor layer, second semiconductor layer that utilize the ion injection to form, and the 3rd semiconductor layer that utilizes extension to form, this the first and the 3rd semiconductor layer is first conductivity type, this second semiconductor layer is second conductivity type, and this first and the 3rd semiconductor layer is respectively as the source electrode and the drain electrode of this power transistor.
19, according to the manufacture method of the power transistor structure of claim 18, wherein when forming this contact wire, form the conductive connecting line that connects this first semiconductor layer simultaneously, in order to be electrically connected to second weld pad, with the transmission source control signal.
20,, wherein form this dielectric layer and comprise to form in regular turn and be rich in silicon oxide layer and oxide layer according to the manufacture method of the power transistor structure of claim 13.
21, according to the manufacture method of the power transistor structure of claim 13, it comprises the step that forms the Solder for Al-Cu Joint Welding metal level in addition, and this Solder for Al-Cu Joint Welding metal level connects the top of this contact wire.
22, according to the manufacture method of the power transistor structure of claim 18, wherein when forming this contact wire, form the metal connecting line that connects the shading ring in this second semiconductor layer simultaneously, this shading ring is this second conductivity type, and opposite with the polarity of this second semiconductor layer.
23, according to the manufacture method of the power transistor structure of claim 22, wherein this shading ring is electrically connected to second weld pad, with the transmission source control signal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200710153214 CN101399267A (en) | 2007-09-29 | 2007-09-29 | Power transistor structure and method for producing the same |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200710153214 CN101399267A (en) | 2007-09-29 | 2007-09-29 | Power transistor structure and method for producing the same |
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| Publication Number | Publication Date |
|---|---|
| CN101399267A true CN101399267A (en) | 2009-04-01 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 200710153214 Pending CN101399267A (en) | 2007-09-29 | 2007-09-29 | Power transistor structure and method for producing the same |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102593156A (en) * | 2011-01-13 | 2012-07-18 | 茂达电子股份有限公司 | Trench Power Transistor with Low Gate/Drain Capacitance |
| CN107068638A (en) * | 2011-04-19 | 2017-08-18 | 索尼公司 | Semiconductor device and its manufacture method, solid camera head and electronic equipment |
-
2007
- 2007-09-29 CN CN 200710153214 patent/CN101399267A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102593156A (en) * | 2011-01-13 | 2012-07-18 | 茂达电子股份有限公司 | Trench Power Transistor with Low Gate/Drain Capacitance |
| CN107068638A (en) * | 2011-04-19 | 2017-08-18 | 索尼公司 | Semiconductor device and its manufacture method, solid camera head and electronic equipment |
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Open date: 20090401 |