CN104638001B - Radio frequency LDMOS device and process - Google Patents
Radio frequency LDMOS device and process Download PDFInfo
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- CN104638001B CN104638001B CN201310559718.XA CN201310559718A CN104638001B CN 104638001 B CN104638001 B CN 104638001B CN 201310559718 A CN201310559718 A CN 201310559718A CN 104638001 B CN104638001 B CN 104638001B
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- 238000005530 etching Methods 0.000 claims abstract description 6
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- 239000002019 doping agent Substances 0.000 claims description 11
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- 229910052721 tungsten Inorganic materials 0.000 claims description 10
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
- H01L29/7835—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/402—Field plates
- H01L29/404—Multiple field plate structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66659—Lateral single gate silicon transistors with asymmetry in the channel direction, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
- H01L29/7834—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with a non-planar structure, e.g. the gate or the source or the drain being non-planar
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Abstract
The invention discloses a kind of radio frequency LDMOS device, there is body area and N-type drift region is lightly doped for Yanzhong outside p-type in P type substrate, it is the groove-shaped faraday's ring of individual layer above its N-type drift region, the groove-shaped faraday's ring of the individual layer has the Electric Field Modulated effect equal with traditional double-deck faraday's ring structure, can reach very high breakdown voltage.The invention also discloses the process of described radio frequency LDMOS device, comprising steps such as polysilicon gate formation, etching groove, drift region injection, body area and source-drain area formation, oxide layer deposit and the formation of faraday's ring, individual layer faraday's ring reduces the deposit of a metal level.
Description
Technical field
The present invention relates to semiconductor applications, a kind of radio frequency LDMOS device is particularly related to, the invention further relates to the radio frequency
The process of LDMOS device.
Background technology
Radio frequency LDMOS（LDMOS：Laterally Diffused Metal Oxide Semiconductor）Device is half
Conductor integrated circuit technique and the microwave solid Power semiconductor products of the New Generation of Integrated of microwave electron technological incorporation,
With the linearity is good, high gain, high pressure, output power, good heat endurance, efficiency high, good broadband matching performance, be easy to and
The advantages of MOS techniques are integrated, and its price is far below GaAs device, is a kind of very competitive power device,
It is widely used in terms of the power amplifier of GSM, PCS, W-CDMA base station, and radio broadcasting and nuclear magnetic resonance.
In radio frequency LDMOS design process, it is desirable to big breakdown voltage BV and small conducting resistance Rdson, meanwhile, it is
Good radio-frequency performance is obtained, it is desirable to which its input capacitance Cgs and output capacitance Cds are also as small as possible, so as to reduce parasitic electricity
Hold the influence to device gain and efficiency.Higher breakdown voltage helps to ensure that stability of the device in real work, such as
Operating voltage is 50V radio frequency LDMOS device, and its breakdown voltage needs to reach more than 110V.And conducting resistance Rdson then can be straight
Connect and have influence on device radiofrequency characteristicses, such as gain and efficiency characteristic.In order to realize higher breakdown voltage (more than 110V), typically
Radio frequency LDMOS tubular constructions are as shown in figure 1, wherein 1 is P type substrate, and 10 be p-type extension, and 11 be PXing Ti areas, and 12 be N-type drift
Area, 23 be source region, and 21 be drain region.Most it is characterized in significantly with two layers of faraday's ring in figure（G-Shield）17, this two
Faraday's ring structure of layer is conducive to electric field to be more uniformly distributed, but in manufacturing process, two layers of faraday's ring structure is also right
Metal deposition twice is answered, technical process is complex.
The content of the invention
The technical problems to be solved by the invention are to provide a kind of radio frequency LDMOS device, and it has groove-shaped individual layer method
Draw ring.
Another technical problem to be solved by this invention is to provide the process of the radio frequency LDMOS device.
To solve the above problems, radio frequency LDMOS device of the present invention, has p-type extension, the P in P type substrate
The outer Yanzhong of type has PXing Ti areas, and the heavily doped P-type area in PXing Ti areas and the source region of the radio frequency LDMOS device；
The outer Yanzhong of the p-type, which also has, is lightly doped drift region, and the leakage in drift region with the LDMOS device is lightly doped
Area；
The PXing Ti areas and the silicon face being lightly doped between drift region have grid oxygen and the polysilicon being covered on grid oxygen
Grid；
There is break-through epitaxial layer away from the side that drift region is lightly doped in PXing Ti areas and its bottom is located at the tungsten of P type substrate
Plug, tungsten holds the connection heavily doped P-type area beyond the Great Wall；
Described be lightly doped in drift region is etched with two various sizes of grooves, and drift region and polysilicon gate is lightly doped
Upper covering silica, silica fills up the groove away from polysilicon gate farther out, does not fill up away from the nearer groove of polysilicon gate, gently
Metal formation faraday's ring is covered on silica above doped drift region and partial polysilicon grid.
Further, be lightly doped in drift region two described various sizes of grooves, one of them is away from polysilicon gate
The nearer groove in pole, it is apart from polysilicon gate side along 0.4~1 μm, 0.4~1.2 μm of groove opening width；Another groove
0.2~0.8 μm away from former trenches edge, 0.4~1.2 μm of groove opening width；Two described gash depths are
A kind of process of radio frequency LDMOS device, includes following processing step：
1st step, is formed in P type substrate after p-type extension, growth grid oxygen and depositing polysilicon, and photoetching and etching form many
Polysilicon gate；
2nd step, performs etching to form two various sizes of grooves using lithographic definition in the region that drift region is lightly doped；
3rd step, is defined using photoresist and drift region is lightly doped, ion implanting is once lightly doped；
4th step, forms PXing Ti areas, and the heavily doped P-type area that PXing Ti areas are drawn in ion implanting formation, and radio frequency
The source region of LDMOS device and drain region；
5th step, whole device surface deposited oxide layer, the oxide layer is not filled up away from the nearer groove of polysilicon gate,
It is fully filled with from the groove of polysilicon gate farther out；
6th step, deposited metal is simultaneously etched, and forms faraday's ring structure；Make tungsten plug.
Further, in the 2nd step, away from the groove that polysilicon gate is nearer, it is apart from polysilicon gate side along 0.4
~1 μm, 0.4~1.2 μm of groove opening width；Another 0.2~0.8 μm of slot trough former trenches edge, groove opening width
0.4~1.2 μm；Two described gash depths are
Further, in the 3rd step, N-type drift region implanted dopant is phosphorus or arsenic, and Implantation Energy is 50~300KeV,
Implantation dosage is 5x1011~4x1012cm-2。
Further, in the 4th step, PXing Ti areas are formed as two ways：One kind is before polysilicon gate formation
Promote to be formed by ion implanting and high temperature, another is to promote to be formed by self-registered technology and high temperature；The injection in PXing Ti areas
Impurity is boron, and Implantation Energy is 30~80KeV, and implantation dosage is 1x1012~1x1014cm-2；Source region and drain region are heavy doping N
Type area, implanted dopant is phosphorus or arsenic, and Implantation Energy is below 200KeV, and implantation dosage is 1x1013~1x1016cm-2；PXing Ti areas
In heavily doped P-type area implanted dopant be boron or boron difluoride, Implantation Energy be below 100KeV, implantation dosage is 1x1013~
1x1016cm-2。
Further, in the 5th step, the silicon oxide layer thickness of deposit is
Radio frequency LDMOS device of the present invention, with groove-shaped individual layer faraday's ring structure, by faraday's ring
The silicon oxide layer of lower section and the adjustment of silicon layer pattern, have reached and conventional double faraday's ring identical N-type drift region electric field point
Cloth regulating effect, makes device have same high-breakdown-voltage characteristic.A Metal deposition is reduced, manufacture craft is simplified.
Brief description of the drawings
Fig. 1 is the structural representation of conventional radio frequency LDMOS device.
Fig. 2~7 are present invention process step schematic diagrams.
Fig. 8 is present invention process flow chart of steps.
Fig. 9~10 are the present invention and tradition LDMOS simulation comparison figure.
Description of reference numerals
1 is P type substrate, and 10 be p-type epitaxial layer, and 11 be PXing Ti areas, and 12 be that drift region is lightly doped, and 13 be tungsten plug, and 14 be grid
Oxygen, 15 be polysilicon gate, and 16 be oxide layer, and 17 be faraday's ring, and 21 be drain region, and 22 be heavily doped P-type area, and 23 be source region,
105 be photoresist.
Embodiment
Radio frequency LDMOS device of the present invention, as shown in fig. 7, having p-type extension 10, the p-type in P type substrate 1
There is PXing Ti areas 11 in extension 10, and heavily doped P-type area 22 in PXing Ti areas 11 and the radio frequency LDMOS device
Source region 23；
Also have in the p-type extension 10 and drift region 12 is lightly doped, be lightly doped in drift region with the LDMOS device
Drain region 21；
The PXing Ti areas 11 and the silicon face being lightly doped between drift region 12 have grid oxygen 14 and are covered on grid oxygen 14
Polysilicon gate 15；
There is break-through epitaxial layer 10 away from the side that drift region 12 is lightly doped in PXing Ti areas 11 and its bottom is served as a contrast positioned at p-type
The tungsten plug 13 at bottom 1, the upper end of tungsten plug 13 connects the heavily doped P-type area 22；
Described be lightly doped in drift region 12 is etched with two various sizes of grooves, and drift region 12 and polysilicon is lightly doped
Silica 16 is covered on grid 15, silica 16 fills up the groove away from polysilicon gate 15 farther out, do not filled up away from polysilicon gate
15 nearer grooves, are lightly doped covering metal formation farad on the silica 16 of drift region 12 and the top of partial polysilicon grid 15
Ring 17.
The process of radio frequency LDMOS device of the present invention, enumerates an embodiment and is described as follows：
Processing step：
1st step, as shown in Fig. 2 in P type substrate after 1 formation p-type extension 10, growth grid oxygen 14 and depositing polysilicon, light
The definition of photoresist 105 forms polysilicon gate 15.
2nd step, as shown in figure 3, performing etching to form two differences in the region that drift region is lightly doped using lithographic definition
The groove of size；Away from the groove that polysilicon gate 15 is nearer, it is apart from polysilicon gate side along d1=0.4~1 μm, and groove is opened
Mouth width d2=0.4~1.2 μm；Another slot trough former trenches edge d3=0.2~0.8 μm, groove opening width d4=0.4
~1.2 μm；It is required that the A/F close to the groove of polysilicon gate is more than the A/F of another groove, two described ditches
Groove depth isThe depth of two grooves can be with identical or different.
3rd step, drift region is lightly doped as shown in figure 4, being defined using photoresist 105, and ion note is once lightly doped
Enter；The implanted dopant of N-type drift region 12 is phosphorus or arsenic, and Implantation Energy is 50~300KeV, and implantation dosage is 5x1011~4x1012cm-2。
4th step, as shown in figure 5, forming PXing Ti areas 11, the formation in PXing Ti areas 11 has two ways：One kind is in polysilicon
Promote to be formed by ion implanting and high temperature before grid formation, another is to promote to be formed by self-registered technology and high temperature；P
The implanted dopant in Xing Ti areas is boron, and Implantation Energy is 30~80KeV, and implantation dosage is 1x1012~1x1014cm-2.Ion is noted again
Enter the heavily doped P-type area 22 to be formed and draw PXing Ti areas 11, implanted dopant is boron or boron difluoride, and Implantation Energy is 100KeV
Hereinafter, implantation dosage is 1x1013~1x1016cm-2.Source region 23 and drain region 21 are heavily doped N-type area, implanted dopant be phosphorus or
Arsenic, Implantation Energy is below 200KeV, and implantation dosage is 1x1013~1x1016cm-2。
5th step, as shown in fig. 6, whole device surface deposited oxide layer 16, the thickness of silicon oxide layer 16 of deposit is The oxide layer is not filled up away from the nearer groove of polysilicon gate, the i.e. bigger groove of A/F, from polysilicon gate
The groove of pole farther out is fully filled with.
6th step, deposited metal is simultaneously etched, and forms faraday's ring structure 17；Tungsten plug 13 is made, device is completed, such as Fig. 7 institutes
Show.
The Making programme of whole device is as shown in Figure 8.
Actual effect to illustrate the invention, is managed and traditional using TCAD simulation softwares to radio frequency LDMOS of the present invention
The effect of radio frequency LDMOS pipes has carried out simulation comparison, and Fig. 9 shows traditional structure and the horizontal stroke that drift region is lightly doped of the present invention
To distribution of the electric field with X-axis, the area that curve and X-axis are surrounded in figure is the breakdown voltage BV of radio frequency LDMOS pipes.Can from figure
To find out, in most of scope, both curve distributions are similar, correspondingly, and both breakdown voltage BV are almost identical.This master
If because first groove of the invention（Away from the groove that polysilicon gate is nearer）The metallic vertical direction of bottom is apart from drift region
It is relatively near, the effect with stronger lifting electric field, and second groove（From the groove of polysilicon gate farther out）The metal at top
Apart from drift region farther out, the same effect with lifting electric field so forms certain gradient to vertical direction, in conjunction with they with
The difference of drain terminal distance, so as to help to obtain more uniform Electric Field Distribution, makes the device of the groove-shaped faraday's ring structure of individual layer
Part has the same high-breakdown-voltage of double-deck faraday's ring structure.Figure 10 is of the invention imitative with traditional structure actual breakdown voltage
True curve, from the results of view, both curves are almost completely superposed, in figure, the breakdown potential of traditional double-deck faraday's ring structure
It is 118V to press BV, and the breakdown voltage BV of groove-shaped individual layer faraday ring of the invention is 117.2V.
The preferred embodiments of the present invention are these are only, are not intended to limit the present invention.Come for those skilled in the art
Say, the present invention there can be various modifications and variations.Within the spirit and principles of the invention, it is any modification for being made, equivalent
Replace, improve etc., it should be included in the scope of the protection.
Claims (7)
1. a kind of radio frequency LDMOS device, has p-type extension in P type substrate, the outer Yanzhong of the p-type has PXing Ti areas, and
The source region in heavily doped P-type area and the radio frequency LDMOS device in PXing Ti areas；
The outer Yanzhong of the p-type, which also has, is lightly doped drift region, and the drain region in drift region with the LDMOS device is lightly doped；
The PXing Ti areas and the silicon face being lightly doped between drift region have grid oxygen and the polysilicon gate being covered on grid oxygen
Pole；
There is break-through epitaxial layer away from the side that drift region is lightly doped in PXing Ti areas and its bottom is located at the tungsten plug of P type substrate, tungsten
The heavily doped P-type area of end connection beyond the Great Wall；
It is characterized in that：Described be lightly doped in drift region is etched with two various sizes of grooves, and drift region is lightly doped and many
Silica is covered in polysilicon gate, silica fills up the groove away from polysilicon gate farther out, does not fill up nearer away from polysilicon gate
Groove, be lightly doped on the silica above drift region and partial polysilicon grid cover metal formation faraday's ring.
2. radio frequency LDMOS device as claimed in claim 1, it is characterised in that：Described be lightly doped in drift region two are not
With the groove of A/F, one of them is away from the nearer groove of polysilicon gate, and it is apart from polysilicon gate side along 0.4~1 μ
M, 0.4~1.2 μm of groove opening width；Another 0.2~0.8 μm of slot trough former trenches edge, groove opening width 0.4~
1.2μm；Groove opening width close to polysilicon gate is more than the A/F of another groove；Two gash depths be 1000~
5000Å。
3. a kind of process of radio frequency LDMOS device as claimed in claim 1, it is characterised in that：Include following technique step
Suddenly：
1st step, is formed in P type substrate after p-type extension, growth grid oxygen and depositing polysilicon, and photoetching and etching form polysilicon
Grid；
2nd step, performs etching to form two various sizes of grooves using lithographic definition in the region that drift region is lightly doped；
3rd step, is defined using photoresist and drift region is lightly doped, ion implanting is once lightly doped；
4th step, forms PXing Ti areas, and the heavily doped P-type area that PXing Ti areas are drawn in ion implanting formation, and radio frequency LDMOS
The source region of device and drain region；
5th step, whole device surface deposited oxide layer, the oxide layer is not filled up away from the nearer groove of polysilicon gate, from many
The groove of polysilicon gate farther out is fully filled with；
6th step, deposited metal is simultaneously etched, and forms faraday's ring structure；Make tungsten plug.
4. a kind of process of radio frequency LDMOS device as claimed in claim 3, it is characterised in that：In 2nd step, away from
The nearer groove of polysilicon gate, it is apart from polysilicon gate side along 0.4~1 μm, 0.4~1.2 μm of groove opening width；Separately
One 0.2~0.8 μm of slot trough former trenches edge, 0.4~1.2 μm of groove opening width；Two gash depths be 1000~
5000Å。
5. a kind of process of radio frequency LDMOS device as claimed in claim 3, it is characterised in that：In 3rd step, N-type
Drift region implanted dopant is phosphorus or arsenic, and Implantation Energy is 50~300KeV, and implantation dosage is 5x1011~4x1012cm-2。
6. a kind of process of radio frequency LDMOS device as claimed in claim 3, it is characterised in that：In 4th step, p-type
Body area is formed as two ways：It is a kind of to promote to be formed by ion implanting and high temperature before polysilicon gate formation, it is another
It is to promote to be formed by self-registered technology and high temperature to plant；The implanted dopant in PXing Ti areas is boron, and Implantation Energy is 30~80KeV, note
Enter dosage for 1x1012~1x1014cm-2；Source region and drain region are heavily doped N-type area, and implanted dopant is phosphorus or arsenic, Implantation Energy
For below 200KeV, implantation dosage is 1x1013~1x1016cm-2；Heavily doped P-type area implanted dopant in PXing Ti areas for boron or
Boron difluoride, Implantation Energy is below 100KeV, and implantation dosage is 1x1013~1x1016cm-2。
7. a kind of process of radio frequency LDMOS device as claimed in claim 3, it is characterised in that：In 5th step, form sediment
Long-pending silicon oxide layer thickness is 1000~4000.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310559718.XA CN104638001B (en) | 2013-11-12 | 2013-11-12 | Radio frequency LDMOS device and process |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310559718.XA CN104638001B (en) | 2013-11-12 | 2013-11-12 | Radio frequency LDMOS device and process |
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| US5909039A (en) * | 1996-04-24 | 1999-06-01 | Abb Research Ltd. | Insulated gate bipolar transistor having a trench |
| CN101312211A (en) * | 2007-05-25 | 2008-11-26 | 东部高科股份有限公司 | Semiconductor device and its manufacture method |
| CN103050531A (en) * | 2012-08-13 | 2013-04-17 | 上海华虹Nec电子有限公司 | RF LDMOS (ratio frequency laterally diffused metal oxide semiconductor) device and manufacture method of RF LDMOS device |
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| KR20100079548A (en) * | 2008-12-31 | 2010-07-08 | 주식회사 동부하이텍 | Laterally double-diffused metal oxide semiconductor, and method for fabricating therof |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US5909039A (en) * | 1996-04-24 | 1999-06-01 | Abb Research Ltd. | Insulated gate bipolar transistor having a trench |
| CN101312211A (en) * | 2007-05-25 | 2008-11-26 | 东部高科股份有限公司 | Semiconductor device and its manufacture method |
| CN103050531A (en) * | 2012-08-13 | 2013-04-17 | 上海华虹Nec电子有限公司 | RF LDMOS (ratio frequency laterally diffused metal oxide semiconductor) device and manufacture method of RF LDMOS device |
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