CN103050531B - RF LDMOS device and manufacture method - Google Patents
RF LDMOS device and manufacture method Download PDFInfo
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- CN103050531B CN103050531B CN201210287203.4A CN201210287203A CN103050531B CN 103050531 B CN103050531 B CN 103050531B CN 201210287203 A CN201210287203 A CN 201210287203A CN 103050531 B CN103050531 B CN 103050531B
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Abstract
The invention discloses a kind of RF LDMOS device, its structure is faraday's shield is single metal layer, this single metal layer comprises polysilicon portion, drift portion, vertical portion, vertical portion is on the right side of polysilicon gate, upper end, vertical portion is communicated with polysilicon portion right-hand member, lower end, vertical portion is communicated with drift portion left end, the left end in polysilicon portion is above polysilicon gate, drift portion is above N-type drain terminal light dope drift region, dielectric layer immediately below polysilicon portion is silica, dielectric layer immediately below drift portion comprises silica, silicon nitride, the width of silicon nitride region is less than the width in described drift portion, the top of silicon nitride region meets the drift portion of this single metal layer, bottom and both sides are silica.The invention also discloses the manufacture method of this kind of RF LDMOS device.The present invention makes RF LDMOS device have high breakdown voltage, and manufacturing process is simple.
Description
Technical field
The present invention relates to semiconductor technology, particularly a kind of RF LDMOS device and manufacture method thereof.
Background technology
RF LDMOS(radio frequency Laterally Diffused Metal Oxide Semiconductor) device is the microwave solid Power semiconductor products of the New Generation of Integrated of semiconductor integrated circuit technology and microwave electron technological incorporation, there is the linearity good, gain is high, withstand voltage height, power output is large, Heat stability is good, efficiency is high, Broadband Matching performance is good, be easy to the advantage such as integrated with MOS technique, and its price is far below GaAs device, it is the very competitive power device of one, be widely used in GSM, PCS, the power amplifier of W-CDMA base station, and the aspect such as radio broadcasting and nulcear magnetic resonance (NMR).
In the design process of RF LDMOS, require little conducting resistance and large puncture voltage, simultaneously because its gate leakage capacitance determines the size of cut-off frequency, thus gate leakage capacitance also should be the smaller the better.Higher puncture voltage contributes to ensureing the stability of device when real work, as the RF LDMOS device that operating voltage is 50V, its puncture voltage needs to reach more than 110V, and conducting resistance Rdson then directly can have influence on the characteristic such as power output and gain of device.
The structure of common RF LDMOS device as shown in Figure 1.Substrate P 1 is formed P extension 10, is formed with a P trap 11 at the left part of P extension 10, right part is formed with a N-type drain terminal light dope drift region 12, and described P trap 11 does not contact with described N-type drain terminal light dope drift region 12;
Described P trap 11 top is formed with a N-type source heavily doped region 24;
Described N-type drain terminal light dope drift region 12 right-hand member is formed with a N-type drain terminal heavily doped region 21;
The N-type impurity concentration of the N-type impurity concentration ratio N-type drain terminal light dope drift region 12 of N-type source heavily doped region 24, N-type drain terminal heavily doped region 21 is high;
A P type polysilicon or Metal Contact post 13 is connect on the left of described P trap 11;
Described contact stud 13 is communicated to substrate P 1;
The p type impurity concentration that P trap 11 top on the left of described N-type source heavily doped region 24 is formed with the p type impurity concentration ratio P trap 11 of the type heavily doped region, P type heavily doped region 22, P 22 that is communicated with described P type polysilicon or Metal Contact post 13 is high;
Above P trap 11 on the right side of described N-type source heavily doped region 24, and above P extension 10 between described P trap 11 and described N-type drain terminal light dope drift region 12, be formed with grid oxygen 14;
Polysilicon gate 15 is formed above described grid oxygen 14;
Above described polysilicon gate 15, and above the left part of described N-type drain terminal light dope drift region 12, be formed with silica 16;
Faraday's shield (Faraday shield) 17 is formed above described silica 16 right part.
The structure of common RF LDMOS device, it has light dope drift region (LDD) 12 at drain terminal, thus make it have larger puncture voltage (BV), simultaneously because its drain terminal light dope drift region 12 doping content is lighter, make it have larger conducting resistance (Rdson).The effect of faraday's shield 17 is the gate leakage capacitances (Cgd) reducing feedback, be in zero potential in the application due to it simultaneously, the effect of field plate can be played, by changing its length or silicon oxide thickness below it, surface field can be reduced to a certain extent, thus the puncture voltage of increased device, and the effect suppressing hot carrier in jection can be played.
As shown in Figure 1, a kind of common faraday's shield 17 is single metal layer, and this single metal layer is
shape, comprise polysilicon portion 171, drift portion 172, vertical portion 173, vertical portion 173 is communicated with polysilicon portion 171 and drift portion 172, polysilicon portion 171 is positioned at upper left, vertical portion 173, drift portion 172 is positioned at bottom right, vertical portion 173, vertical portion 173 is on the right side of polysilicon gate 15, the left part in polysilicon portion 171 is above polysilicon gate 15, drift portion 172 is above drain terminal light dope drift region 12, this single metal layer is with being silica 16 between polysilicon gate 15, drain terminal light dope drift region 12, and drift portion 172 is tabular.This kind of faraday's shield is that the RF LDMOS puncture voltage of single metal layer 17 is difficult to reach very large puncture voltage.
RF LDMOS is (operating voltage is 50V) in high voltage applications, in order to make it have larger safety operation area, current industry adopts the structure of faraday's shield with two-layer or more metal layers usually, as shown in Figure 2 and Figure 3, first layer metal layer is identical with single metal layer shown in Fig. 1, other each metal levels are sequentially positioned at the upper right side of first layer metal layer, and between each layer metal level, silica 16 is isolated.Faraday's shield 17 is two-layer or more metal layers, be conducive to Electric Field Distribution evenly, so have the RF LDMOS of this faraday's shield structure, there is large puncture voltage, be generally about 120V.But faraday's shield be two-layer or the RF LDMOS of more metal layers in manufacture craft process, need the making carrying out two-layer (or multilayer) metal level, need at least twice metal level deposit and etching process, manufacturing process is complicated.
Summary of the invention
The technical problem to be solved in the present invention makes RF LDMOS device have high breakdown voltage, and manufacturing process is simple.
For solving the problems of the technologies described above, the invention provides a kind of RF LDMOS device, its structure is, a N-type drain terminal light dope drift region is formed at the right part of P extension, P extension on the left of N-type drain terminal light dope drift region is formed with grid oxygen, polysilicon gate is formed above described grid oxygen, above described polysilicon gate, dielectric layer is formed above side and described N-type drain terminal light dope drift region left part, faraday's shield is formed above described dielectric layer right part, described faraday's shield is single metal layer, this single metal layer comprises polysilicon portion, drift portion, vertical portion, vertical portion is on the right side of polysilicon gate, upper end, vertical portion is communicated with polysilicon portion right-hand member, lower end, vertical portion is communicated with drift portion left end, the left end in polysilicon portion is above polysilicon gate, drift portion is above N-type drain terminal light dope drift region, it is characterized in that,
Dielectric layer immediately below the polysilicon portion of this single metal layer is silica, dielectric layer immediately below the drift portion of this single metal layer comprises silica, silicon nitride, the width of silicon nitride region is less than the width in described drift portion, the top of silicon nitride region meets the drift portion of this single metal layer, and bottom and both sides are silica.
For solving the problems of the technologies described above, present invention also offers a kind of manufacture method of RF LDMOS device, it comprises the following steps:
One. form grid oxygen, polysilicon gate, N-type drain terminal light dope drift region, N-type drain terminal light dope drift region is formed in the right part of P extension, and grid oxygen is formed in the P extension on the left of N-type drain terminal light dope drift region, and polysilicon gate is formed on described grid oxygen;
Two. overall deposit one deck silica on silicon chip;
Three. by chemical wet etching, form a groove in the silica above the left part of N-type drain terminal light dope drift region, the degree of depth of described groove is less than the thickness of this layer of silica;
Four. overall deposit one deck silicon nitride on silicon chip, the thickness of this layer of silicon nitride equals the degree of depth of described groove;
Five. described groove is fallen with the silicon nitride etch of exterior domain;
Six. deposit layer of metal layer on silicon chip also etches accordingly, forms faraday's shield;
The metal level forming described faraday's shield comprises polysilicon portion, drift portion, vertical portion, vertical portion is on the right side of polysilicon gate, upper end, vertical portion is communicated with polysilicon portion right-hand member, lower end, vertical portion is communicated with drift portion left end, the left end in polysilicon portion is above polysilicon gate, drift portion is positioned at directly over described groove, and the width in the portion that drifts about is greater than the width of described groove;
Seven. carry out subsequent technique, form RF LDMOS device.
RF LDMOS device of the present invention, its faraday's shield is single-layer metal Rotating fields, single metal layer is the composite dielectric district be made up of silica and silicon nitride with the dielectric layer between N-type drain terminal light dope drift region, silicon nitride is near metal level, silica is near N-type drain terminal light dope drift region, single metal layer is simple silica with the dielectric layer between polysilicon gate, relative dielectric constant due to silicon nitride is about the twice of silicon dioxide, make the electric field below faraday's shield distribute more equably like this, thus improve the puncture voltage BV of device.
RF LDMOS device of the present invention, because its faraday's shield is single-layer metal Rotating fields, by regulating the dielectric layer in region immediately below single metal layer, the high-breakdown-voltage identical with two metal layers structure devices can be realized, and the Metal deposition, the etching process that decrease in device manufacturing processes, device fabrication is simple.
Accompanying drawing explanation
In order to be illustrated more clearly in technical scheme of the present invention, below the accompanying drawing that will use required for the present invention is briefly described, apparently, accompanying drawing in the following describes is only some embodiments of the present invention, for those of ordinary skill in the art, under the prerequisite not paying creative work, other accompanying drawing can also be obtained according to these accompanying drawings.
The structural representation of Fig. 1 to be a kind of faraday's shield be RF LDMOS device of common single metal layer;
The structural representation of Fig. 2 to be a kind of faraday's shield be RF LDMOS device of two metal layers;
The structural representation of Fig. 3 to be a kind of faraday's shield be RF LDMOS device of three-layer metal layer;
Fig. 4 is the structure one embodiment schematic diagram of RF LDMOS device of the present invention;
Fig. 5 is manufacture method one embodiment step one schematic diagram of RF LDMOS device of the present invention;
Fig. 6 is the manufacture method one embodiment step 2 schematic diagram of RF LDMOS device of the present invention;
Fig. 7 is the manufacture method one embodiment step 3 schematic diagram of RF LDMOS device of the present invention;
Fig. 8 is the manufacture method one embodiment step 4 schematic diagram of RF LDMOS device of the present invention;
Fig. 9 is the manufacture method one embodiment step 5 schematic diagram of RF LDMOS device of the present invention;
Figure 10 is the manufacture method one embodiment step 6 schematic diagram of RF LDMOS device of the present invention;
The distribution of Figure 11 to be RF LDMOS device of the present invention and faraday's shield be N-type drain terminal light dope drift region transverse electric field intensity distance of the RF LDMOS device of two metal layers.
Embodiment
Below in conjunction with accompanying drawing, carry out clear, complete description to the technical scheme in the present invention, obviously, described embodiment is a part of embodiment of the present invention, instead of whole embodiments.Based on the embodiment in the present invention, other embodiments all that those of ordinary skill in the art obtain under the prerequisite not making creative work, all belong to the scope of protection of the invention.
Embodiment one
The structure of RF LDMOS device as shown in Figure 4.A N-type drain terminal light dope drift region 12 is formed at the right part of P extension 10, P extension 10 on the left of N-type drain terminal light dope drift region 12 is formed with grid oxygen 14, polysilicon gate 15 is formed above described grid oxygen 14, above described polysilicon gate 15, dielectric layer 16 is formed above side and described N-type drain terminal light dope drift region 12 left part, faraday's shield (Faradayshield) 17 is formed above described dielectric layer 16 right part, described faraday's shield 17 is single metal layer, this single metal layer comprises polysilicon portion 171, drift portion 172, vertical portion 173, vertical portion 173 is on the right side of polysilicon gate 15, upper end, vertical portion 173 is communicated with polysilicon portion 171 right-hand member, lower end, vertical portion 173 is communicated with drift portion 172 left end, the left end in polysilicon portion 171 is above polysilicon gate 15, drift portion 172 is above N-type drain terminal light dope drift region 12, dielectric layer 16 immediately below the polysilicon portion 171 of this single metal layer is silica, dielectric layer 16 immediately below the drift portion 172 of this single metal layer comprises silica, silicon nitride, the width of silicon nitride region 19 is less than the width in drift portion 172, the top of silicon nitride region 19 meets the drift portion 172 of this single metal layer, bottom and both sides are silica.
Preferably, the thickness of described silicon nitride region 19 is 1000 ~ 3000 dusts;
Preferably, the width of described silicon nitride region 19 is 0 ~ 1.3um.
Embodiment two
Based on embodiment one, RF LDMOS device structure as shown in Figure 4.Be formed with a P trap 11 at the left part of P extension 10, be formed with a N-type drain terminal light dope drift region 12 at the right part of P extension 10, described P trap 11 does not contact with described N-type drain terminal light dope drift region 12;
The top of described P trap 11 is formed with a N-type source heavily doped region 24;
The right part of described N-type drain terminal light dope drift region 12 is formed with a N-type drain terminal heavily doped region 21;
The N-type impurity concentration of described N-type source heavily doped region 24, N-type drain terminal heavily doped region 21, is greater than the N-type impurity concentration of N-type drain terminal light dope drift region 12;
Above P trap 11 on the right side of described N-type source heavily doped region 24, and above P extension 10 between described P trap 11 and described N-type drain terminal light dope drift region 12, be formed with described grid oxygen 14.
Embodiment three
The manufacture method of the RF LDMOS device described in embodiment one, comprises the following steps:
One. form grid oxygen 14, polysilicon gate 15, N-type drain terminal light dope drift region 12, N-type drain terminal light dope drift region 12 is formed in the right part of P extension 10, grid oxygen 14 is formed in the P extension 10 on the left of N-type drain terminal light dope drift region 12, and polysilicon gate 15 is formed on described grid oxygen 14, as shown in Figure 5;
Two. overall deposit one deck silica 16 on silicon chip, as shown in Figure 6; Preferably, the thickness of this layer of silica is 1000 ~ 4000 dusts;
Three. by chemical wet etching, form a groove in the silica above the left part of N-type drain terminal light dope drift region, the degree of depth of this groove is less than the thickness of this layer of silica 16, as shown in Figure 7; Preferably, the width of this groove is less than or equal to 1.3um, and the degree of depth is 1000 ~ 3000 dusts;
Four. overall deposit one deck silicon nitride 19 on silicon chip, the thickness of this layer of silicon nitride 19 equals the degree of depth of described groove, as shown in Figure 8; Preferably, the thickness of this layer of silicon nitride 19 is 1000 ~ 3000 dusts;
Five. described groove is etched away with the silicon nitride 19 of exterior domain, as shown in Figure 9;
Six. deposit layer of metal layer on silicon chip also etches accordingly, forms faraday's shield 17, as shown in Figure 10;
The metal level forming described faraday's shield 17 comprises polysilicon portion 171, drift portion 172, vertical portion 173, vertical portion 173 is on the right side of polysilicon gate 15, upper end, vertical portion 173 is communicated with polysilicon portion 171 right-hand member, lower end, vertical portion 173 is communicated with drift portion 172 left end, the left end in polysilicon portion 171 is above polysilicon gate 15, drift portion 172 is positioned at directly over described groove, and the width in the portion 172 that drifts about is greater than the width of described groove;
Seven. carry out subsequent technique, form RF LDMOS device, as shown in Figure 4.
Embodiment four
Based on the manufacture method of the RF LDMOS device of embodiment three, step one comprises the following steps:
(1) in substrate P, P extension 10 is grown;
(2) in P extension 10, push away trap (ion activation) by P ion implantation and high temperature and form P trap 11;
(3) in P extension 10, gate oxide is grown;
(4) depositing polysilicon on gate oxide;
(5) by position and the area of photoresist definition polysilicon gate 15, the gate oxide outside polysilicon gate 15 region and etching polysilicon, above the right part of described P trap 11, are removed, are formed grid oxygen 14 and polysilicon gate 15 by the left end of polysilicon gate 15;
(6) retain the photoresist at polysilicon gate 15 top, carry out N-type light dope ion implantation, form a N-type drain terminal light dope drift region 12 in the P extension 10 on the right side of polysilicon gate 15, in the P trap 11 on the left of polysilicon gate 15, form N-type source light doping section; Preferably, the N-type impurity of N-type light dope ion implantation is phosphorus or arsenic, and Implantation Energy scope is 50keV ~ 300keV, and implantation dosage scope is 5E
11~ 4E
12individual atom per square centimeter;
(7) go out the position of a N-type source heavily doped region 24 and area, the position of a N-type drain terminal heavily doped region 21 and area by lithographic definition, carry out N ion implantation, form this N-type source heavily doped region 24 and this N-type drain terminal heavily doped region 21; This N-type source heavily doped region 24 is positioned at the right part of described N-type source light doping section, and this N-type drain terminal heavily doped region 21 is positioned at the right part of this N-type drain terminal light doping section 12.
RF LDMOS device of the present invention, its faraday's shield is single-layer metal Rotating fields, single metal layer is the composite dielectric district be made up of silica and silicon nitride with the dielectric layer between N-type drain terminal light dope drift region, silicon nitride is near metal level, silica is near N-type drain terminal light dope drift region, single metal layer is simple silica with the dielectric layer between polysilicon gate, relative dielectric constant due to silicon nitride is about the twice of silicon dioxide, make the electric field below faraday's shield distribute more equably like this, thus improve the puncture voltage BV of device.
RF LDMOS device of the present invention, because its faraday's shield is single-layer metal Rotating fields, by regulating the dielectric layer in region immediately below single metal layer, the high-breakdown-voltage identical with two metal layers structure devices can be realized, and the Metal deposition, the etching process that decrease in device manufacturing processes, device fabrication is simple.
The distribution of Figure 11 to be RF LDMOS device of the present invention and faraday's shield be N-type drain terminal light dope drift region transverse electric field intensity distance of the RF LDMOS device of two metal layers.Wherein, solid line represents that double-deck faraday's shield is the RF LDMOS device of two metal layers, and dotted line represents RF LDMOS device of the present invention, and the area that Curves is corresponding is puncture voltage BV.Peak electric field 30 is formed by the composite dielectric district under the single metal layer of RF LDMOS device of the present invention.This is because silicon nitride has higher relative dielectric constant than silicon dioxide, be about its 2 times, thus the electric field of filling below silicon nitride region can form a peak value, and the peak electric field that the first layer metal layer of the RF LDMOS device being two metal layers with double-deck faraday's shield obtains is similar.The existence of this peak value can make the distribution of electric field more even, contributes to improving puncture voltage BV.
The foregoing is only preferred embodiment of the present invention, not in order to limit the present invention, within the spirit and principles in the present invention all, any amendment made, equivalent replacement, improvement etc., all should be included within the scope of protection of the invention.
Claims (7)
1. a RF LDMOS device, a N-type drain terminal light dope drift region is formed at the right part of P extension, P extension on the left of N-type drain terminal light dope drift region is formed with grid oxygen, polysilicon gate is formed above described grid oxygen, above described polysilicon gate, dielectric layer is formed above side and described N-type drain terminal light dope drift region left part, faraday's shield is formed above described dielectric layer right part, described faraday's shield is single metal layer, this single metal layer comprises polysilicon portion, drift portion, vertical portion, vertical portion is on the right side of polysilicon gate, upper end, vertical portion is communicated with polysilicon portion right-hand member, lower end, vertical portion is communicated with drift portion left end, the left end in polysilicon portion is above polysilicon gate, drift portion is above N-type drain terminal light dope drift region, it is characterized in that,
Dielectric layer immediately below the polysilicon portion of this single metal layer is silica, dielectric layer immediately below the drift portion of this single metal layer comprises silica, silicon nitride, the width of silicon nitride region is less than the width in described drift portion, the top of silicon nitride region meets the drift portion of this single metal layer, and bottom and both sides are silica.
2. RF LDMOS device according to claim 1, is characterized in that,
The thickness of silicon nitride region is 1000 ~ 3000 dusts.
3. RF LDMOS device according to claim 1, is characterized in that,
The width of silicon nitride region is 0 ~ 1.3um.
4. RF LDMOS device according to claim 1, is characterized in that,
Be formed with a P trap at the left part of P extension, described P trap does not contact with described N-type drain terminal light dope drift region;
The top of described P trap is formed with a N-type source heavily doped region;
The right part of described N-type drain terminal light dope drift region is formed with a N-type drain terminal heavily doped region;
The N-type impurity concentration of described N-type drain terminal heavily doped region, N-type source heavily doped region, is greater than the N-type impurity concentration of N-type drain terminal light dope drift region;
Above P trap on the right side of described N-type source heavily doped region, and above P extension between described P trap and described N-type drain terminal light dope drift region, be formed with described grid oxygen.
5. a manufacture method for RF LDMOS device according to claim 1, is characterized in that, comprise the following steps:
One. form grid oxygen, polysilicon gate, N-type drain terminal light dope drift region, N-type drain terminal light dope drift region is formed in the right part of P extension, and grid oxygen is formed in the P extension on the left of N-type drain terminal light dope drift region, and polysilicon gate is formed on described grid oxygen;
Two. overall deposit one deck silica on silicon chip;
Three. by chemical wet etching, form a groove in the silica above the left part of N-type drain terminal light dope drift region, the degree of depth of described groove is less than the thickness of this layer of silica;
Four. overall deposit one deck silicon nitride on silicon chip, the thickness of this layer of silicon nitride equals the degree of depth of described groove;
Five. described groove is fallen with the silicon nitride etch of exterior domain;
Six. deposit layer of metal layer on silicon chip also etches accordingly, forms faraday's shield;
The metal level forming described faraday's shield comprises polysilicon portion, drift portion, vertical portion, vertical portion is on the right side of polysilicon gate, upper end, vertical portion is communicated with polysilicon portion right-hand member, lower end, vertical portion is communicated with drift portion left end, the left end in polysilicon portion is above polysilicon gate, drift portion is positioned at directly over described groove, and the width in the portion that drifts about is greater than the width of described groove;
Seven. carry out subsequent technique, form RF LDMOS device.
6. the manufacture method of RF LDMOS device according to claim 5, is characterized in that,
The width of described groove is less than or equal to 1.3um, and the degree of depth is 1000 ~ 3000 dusts;
The thickness of this layer of silicon nitride is 1000 ~ 3000 dusts.
7. the manufacture method of RF LDMOS device according to claim 5, is characterized in that,
Step one comprises the following steps:
(1) in substrate P, P extension is grown;
(2) push away trap in the outer Yanzhong of P by P ion implantation and high temperature and form P trap;
(3) in P extension, gate oxide is grown;
(4) depositing polysilicon on gate oxide;
(5) by position and the area of photoresist definition polysilicon gate, the gate oxide outside polysilicon gate region and etching polysilicon, above the right part of described P trap, are removed, are formed grid oxygen and polysilicon gate by the left end of polysilicon gate;
(6) retain the photoresist at polysilicon gate top, carry out N-type light dope ion implantation, the outer Yanzhong of the P on the right side of polysilicon gate forms a N-type drain terminal light dope drift region.
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0069429B1 (en) * | 1981-07-06 | 1989-09-20 | Koninklijke Philips Electronics N.V. | Insulated gate field effect transistor |
| CN1842918A (en) * | 2003-08-27 | 2006-10-04 | 皇家飞利浦电子股份有限公司 | Electronic device comprising an ldmos transistor |
| TWI325175B (en) * | 2003-09-30 | 2010-05-21 | Agere Systems Inc | Metal-oxide-semiconductor device including a buried lightly-doped drain region |
| CN102237410A (en) * | 2010-04-29 | 2011-11-09 | Nxp股份有限公司 | Semiconductor transistor comprising two electrically conductive shield elements |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2004516652A (en) * | 2000-12-11 | 2004-06-03 | コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ | Method for manufacturing semiconductor device having field effect transistor |
| US20090267145A1 (en) * | 2008-04-23 | 2009-10-29 | Ciclon Semiconductor Device Corp. | Mosfet device having dual interlevel dielectric thickness and method of making same |
-
2012
- 2012-08-13 CN CN201210287203.4A patent/CN103050531B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0069429B1 (en) * | 1981-07-06 | 1989-09-20 | Koninklijke Philips Electronics N.V. | Insulated gate field effect transistor |
| CN1842918A (en) * | 2003-08-27 | 2006-10-04 | 皇家飞利浦电子股份有限公司 | Electronic device comprising an ldmos transistor |
| TWI325175B (en) * | 2003-09-30 | 2010-05-21 | Agere Systems Inc | Metal-oxide-semiconductor device including a buried lightly-doped drain region |
| CN102237410A (en) * | 2010-04-29 | 2011-11-09 | Nxp股份有限公司 | Semiconductor transistor comprising two electrically conductive shield elements |
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