CN104636526B - The mismatch model method of silicon hole - Google Patents
The mismatch model method of silicon hole Download PDFInfo
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- CN104636526B CN104636526B CN201310571386.7A CN201310571386A CN104636526B CN 104636526 B CN104636526 B CN 104636526B CN 201310571386 A CN201310571386 A CN 201310571386A CN 104636526 B CN104636526 B CN 104636526B
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Abstract
The invention discloses a kind of mismatch model method of silicon hole, including step：The test structure being made of the silicon hole of two phases across a certain distance is respectively formed on multi-disc silicon substrate；The diameter of silicon hole and the normal distyribution function of spacing are obtained by the way that data are monitored online and derives the diameter mismatch model of silicon hole and pitch mismatch model and obtains the resistance value actual distribution of silicon hole and inductance value actual distribution；Resistivity mismatch model is established, and is combined by the diameter mismatch model of silicon hole, the pitch mismatch model of silicon hole and resistivity mismatch model and is formed silicon hole mismatch model；Monte Carlo simulation is carried out to silicon hole mismatch model and obtains the resistance of silicon hole and inductance value emulation distribution；By realizing the Coefficient Fitting to silicon hole mismatch model to the resistance value emulation distribution of silicon hole and resistance value actual distribution, the inductance value emulation distribution and comparison of inductance value actual distribution.The random error of silicon hole diameter, spacing and resistivity, can improve model accuracy caused by energy simulation process fluctuation of the invention.
Description
Technical field
The present invention relates to a kind of semiconductor integrated circuit method of manufacturing technology, more particularly to a kind of silicon hole（TSV）'s
Mismatch model method.
Background technology
Silicon hole technique is a kind of emerging ic manufacturing process, and the circuit for being produced on silicon chip upper surface is passed through silicon
The metal filled in through-hole is connected to silicon chip back side, with reference to three-dimension packaging technique so that IC layouts are arranged side by side from conventional two-dimensional
Develop to more advanced three-dimensional stacked, such component encapsulation is more compact, by shortening chip lead distance, can greatly improve
The frequency characteristic and power characteristic of circuit.Silicon hole technique is widely used, and is suitable as many-sided device performance and is promoted.
In actual process, due to technological fluctuation, the random of silicon hole diameter, pitch of holes and tungsten plug resistivity can be caused
Error, these differences influence whether the series resistance and inductance of TSV, but are available to the TSV models of designer, when given silicon leads to
The only fixation that model is obtained by emulation after bore dia is as a result, can not reflect that mismatch caused by technological fluctuation shows
As.In the fabrication process, obtained TSV inductance values and resistance value all can there are a random waves after through-hole diameter is fixed
Dynamic range.In existing TSV models, silicon hole diameter caused by not accounting for technological fluctuation, pitch of holes and tungsten plug resistance
The random error of rate has ignored influence of the technological fluctuation to model accuracy.
Invention content
The technical problems to be solved by the invention are to provide a kind of mismatch model method of silicon hole, can simulation process fluctuation
The random error of caused silicon hole diameter, spacing and resistivity, can improve model accuracy.
In order to solve the above technical problems, the mismatch model method of silicon hole provided by the invention includes the following steps：
Step 1: the test knot being made of the silicon hole of two phases across a certain distance is respectively formed on multi-disc silicon substrate
Structure, the design value of the diameter of all silicon holes is all identical, and the design value of the spacing between each adjacent silicon hole is all
It is identical, a silicon hole in each test structure as test signal input part, another is as the letter tested
Number output terminal.
Step 2: the test value for obtaining the diameter of each silicon hole on each silicon substrate by the way that data are monitored online
And the test value of the spacing between each silicon hole, so as to obtain +/- 3 mark of the diameter of all silicon holes and spacing
It is accurate poor（sigma）Statistical monitor value, and be worth to by the Statistical monitor normal distyribution function of the diameter of the silicon hole
And the spacing between each adjacent silicon hole normal distyribution function and the silicon is calculated by the Statistical monitor value
The normal distyribution function of the diameter of through-hole relative to Standard Normal Distribution the first correction factor and calculate each adjacent
The normal distyribution function of spacing between the silicon hole relative to Standard Normal Distribution the second correction factor, described
Two correction factors are twice of first correction factor.
The diameter mismatch model and spacing of silicon hole are established according to first correction factor and second correction factor
Mismatch model, the diameter mismatch model of the silicon hole are：
D1 '=D1+ Δ D1,
Δ D1=dm × agauss (0,1,1)；
Wherein, D1 is the design value of the diameter of the silicon hole before correcting and the diameter equal to the silicon hole；D1 ' is
By the diameter of the revised silicon hole；Δ D1 is the diameter correction term of the silicon hole；Dm is corrected for described first
Number.
The pitch mismatch model of the silicon hole is：
S1 '=S1+2dm × agauss (0,1,1)；
Wherein, S1 is spacing between the adjacent silicon hole before correcting and equal between the adjacent silicon hole
Away from design value；S1 ' is the spacing Jing Guo the revised silicon hole；2dm × agauss (0,1,1) is the silicon hole
Spacing correction term；2dm is second correction factor.
The resistance value actual distribution of the silicon hole and inductance value actual distribution are obtained by the on-line monitoring data.
Step 3: establishing resistivity mismatch model, the resistivity mismatch model formula is：
ρ '=ρ+Δ ρ
Wherein ρ ', be the silicon hole first resistor rate, the first resistor rate include by the silicon hole diameter and
Spacing and the mismatch part generated；ρ is the second resistance rate of the silicon hole, and the second resistance rate is a fixed value, by institute
The packing material for stating silicon hole determines；Δ ρ is the mismatch resistivity that is generated by the diameter and spacing of the silicon hole；D is institute
State the diameter of silicon hole, spacing of the S between the adjacent silicon hole, ρ1It is the mismatch resistivity with the straight of the silicon hole
The third correction factor of diameter variation, ρ2For the mismatch resistivity with the silicon hole spacing change the 4th correction factor,
Dx is the 5th correction factor positioned at the diameter index part of the silicon hole, and sx is the spacing index part positioned at the silicon hole
The 6th correction factor divided；Agauss (0,1,1) is Standard Normal Distribution.
By the diameter mismatch model of the silicon hole, the pitch mismatch model of the silicon hole and the resistivity mismatch mould
Type combines to form silicon hole mismatch model.
Step 4: fixed first frequency is selected to carry out Monte Carlo simulation to the silicon hole mismatch model, respectively
The resistance value emulation distribution of the silicon hole under to the first frequency and inductance value emulation distribution.
Step 5: by the resistance value of silicon hole emulation distribution and the resistance value actual distribution, described
Inductance value emulation distribution and the comparison of the inductance value actual distribution are realized to first correction factor, the third amendment
The fitting of coefficient, the 4th correction factor, the 5th correction factor and the 6th correction factor, after making Coefficient Fitting
The resistance value emulation distribution that the silicon hole mismatch model obtains is consistent with the resistance value actual distribution, the inductance value
Emulation distribution is consistent with the inductance value actual distribution.
A further improvement is that the resistivity is updated to by the D1 ' in the diameter mismatch model by the silicon hole
D in mismatch model, the S1 ' in the pitch mismatch model of the silicon hole is updated to the S in the resistivity mismatch model
Obtain the silicon hole mismatch model.
A further improvement is that between the normal distyribution function model of the diameter of the silicon hole, the adjacent silicon hole
Spacing normal distyribution function model and the silicon hole mismatch model all write using SPICE language；Agauss (0,1,1)
The Standard Normal Distribution built-in for SPIEC.
The present invention can obtain spacing between the normal distyribution function model of the diameter of silicon hole, adjacent silicon hole just
State distribution function model and silicon hole mismatch model, between the normal distyribution function model of the diameter of silicon hole, adjacent silicon hole
The normal distyribution function model of spacing simulate the influence that technological fluctuation generates the diameter and spacing of silicon hole respectively, so as to
It can realize the diameter of silicon hole and the accurate simulation of spacing；The normal state of the diameter of silicon hole is reflected in silicon hole mismatch model
The diameter and spacing of silicon hole obtained by the normal distyribution function model of spacing between distribution function model and adjacent silicon hole
Fluctuation, so as to simulation process fluctuate caused by silicon hole diameter, spacing and resistivity random error, can accurate simulation by
Technological fluctuation and the mismatch that generates and improve model accuracy.
Description of the drawings
The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments：
Fig. 1 is flow chart of the embodiment of the present invention；
Fig. 2 is the structure diagram of the silicon hole in the embodiment of the present invention.
Specific embodiment
As shown in Figure 1, it is flow chart of the embodiment of the present invention；As shown in Fig. 2, it is the silicon hole in the embodiment of the present invention
3 structure diagram.The mismatch model method of silicon hole of the embodiment of the present invention 3 includes the following steps：
Step 1: the test knot being made of the silicon hole 3 of two phases across a certain distance is respectively formed on multi-disc silicon substrate 1
Structure, the design value of the diameter of all silicon holes 3 is all identical, the design value of the spacing between each adjacent silicon hole 3
It is all identical, a silicon hole 3 in each test structure as test signal input part, another is as testing
Signal output end.
It in order to which the diameter to first silicon hole 3 and spacing illustrate, please refers to shown in Fig. 2, is implementation of the present invention
The structure diagram of silicon hole 3 in example, device architecture is formed on silicon substrate 1（It is not shown）, interlayer film 2 covering be formed with
1 surface of silicon substrate of device architecture, silicon hole 3 passes through the connection of the realization front metal 4 of silicon substrate 1 and back metal 5, in front
Protective dielectric layer such as silicon nitride layer is formed on metal 4.Tungsten is filled in silicon hole 3.Silicon hole 3 is by photoetching work
It is formed after being performed etching again to silicon substrate 1 after skill definition, so while technological fluctuation, the diameter actual value and design of silicon hole 3
Value is differentiated.The width of silicon of the spacing between two adjacent silicon holes 3 between silicon hole 3, the spacing of silicon hole 3
It also can be with technological fluctuation.
Step 2: the test for obtaining the diameter of each silicon hole 3 on each silicon substrate 1 by the way that data are monitored online
The test value of spacing between value and each silicon hole 3, so as to obtain the diameter of all silicon holes 3 and spacing
The Statistical monitor value of +/- 3 standard deviation, and it is worth to by the Statistical monitor normal distyribution function of the diameter of the silicon hole 3
And the spacing between each adjacent silicon hole 3 normal distyribution function and calculated by the Statistical monitor value described
The normal distyribution function of the diameter of silicon hole 3 relative to Standard Normal Distribution the first correction factor and calculate each phase
The normal distyribution function of spacing between the adjacent silicon hole 3 is relative to the second correction factor of Standard Normal Distribution, institute
State twice that the second correction factor is first correction factor.
The diameter mismatch model and spacing of silicon hole are established according to first correction factor and second correction factor
Mismatch model, the diameter mismatch model of the silicon hole are：
D1 '=D1+ Δ D1,
Δ D1=dm × agauss (0,1,1)；
Wherein, D1 is the design value of the diameter of the silicon hole 3 before correcting and the diameter equal to the silicon hole 3；D1’
For the diameter Jing Guo the revised silicon hole 3；Δ D1 is the diameter correction term of the silicon hole 3；Dm is repaiied for described first
Positive coefficient.
The pitch mismatch model of the silicon hole is：
S1 '=S1+2dm × agauss (0,1,1)；
Wherein, S1 is the spacing of the silicon hole 3 before correcting and setting equal to the spacing between the adjacent silicon hole 3
Evaluation；S1 ' is the spacing Jing Guo the revised silicon hole 3；2dm × agauss (0,1,1) is the spacing of the silicon hole
Correction term；2dm is second correction factor.
The resistance value actual distribution of the silicon hole and inductance value actual distribution are obtained by the on-line monitoring data.
The normal state of spacing between the normal distyribution function model of the diameter of the silicon hole 3 and the adjacent silicon hole 3
Distribution function model is all write using SPICE language.
The resistance value actual distribution of the silicon hole 3 and inductance value actual distribution are obtained by the on-line monitoring data.
Step 3: establishing resistivity mismatch model, the resistivity mismatch model formula is：
ρ '=ρ+Δ ρ
Wherein, ρ ' is the first resistor rate of the silicon hole 3, which includes the diameter by the silicon hole 3
The mismatch part generated with spacing；ρ is the second resistance rate of the silicon hole 3, and the second resistance rate is a fixed value, by
The packing material of the silicon hole 3 determines；Δ ρ is the mismatch resistivity that is generated by the diameter and spacing of the silicon hole 3；D
For the diameter of the silicon hole 3, spacing of the S between the adjacent silicon hole 3, ρ1Lead to for the mismatch resistivity with the silicon
The third correction factor of the diameter change in hole 3, ρ2It is repaiied for the mismatch resistivity with the 4th that the spacing of the silicon hole 3 changes
Positive coefficient, dx are the 5th correction factor positioned at the diameter index part of the silicon hole 3, and sx is positioned at the silicon hole 3
6th correction factor of spacing exponential part；Agauss (0,1,1) is Standard Normal Distribution.
The silicon hole mismatch model is all write using SPICE language；Agauss (0,1,1) is the built-in standards of SPIEC
Normal distyribution function, 0 of first item in the bracket of agauss (0,1,1) represents the central value of distribution function 0, Section 2
1 represent distribution function curve from 0 to the right and left maximum sigma amplitudes be 1, Section 31 represent distribution function sigma numbers
Value, wherein sigma numerical value represent uniformly poor.
Due to the fluctuation of resistivity, when resulting in high frequency the fluctuation of Kelvin effect influenced by resistivity：
Wherein, δ is skin depth, μoFor magnetic conductivity, f is frequency.
By the diameter mismatch model of the silicon hole, the pitch mismatch model of the silicon hole and the resistivity mismatch mould
Type combines to form silicon hole mismatch model.The resistance is updated to by the D1 ' in the diameter mismatch model by the silicon hole
D in rate mismatch model, the S1 ' in the pitch mismatch model of the silicon hole is updated in the resistivity mismatch model
S obtains the silicon hole mismatch model.
Step 4: fixed first frequency is selected to carry out Monte Carlo simulation to the silicon hole mismatch model, respectively
The resistance value emulation distribution of the silicon hole 3 under to the first frequency and inductance value emulation distribution.
Step 5: by the resistance value of the silicon hole 3 emulation distribution and the resistance value actual distribution, described
Inductance value emulation distribution and the comparison of the inductance value actual distribution are realized to first correction factor, the third amendment
The fitting of coefficient, the 4th correction factor, the 5th correction factor and the 6th correction factor, after making Coefficient Fitting
The resistance value emulation distribution that the silicon hole mismatch model obtains is consistent with the resistance value actual distribution, the inductance value
Emulation distribution is consistent with the inductance value actual distribution.
The present invention has been described in detail through specific embodiments, but these not form the limit to the present invention
System.Without departing from the principles of the present invention, those skilled in the art can also make many modification and improvement, these also should
It is considered as protection scope of the present invention.
Claims (3)
1. a kind of mismatch model method of silicon hole, which is characterized in that include the following steps：
Step 1: the test structure being made of the silicon hole of two phases across a certain distance, institute are respectively formed on multi-disc silicon substrate
The design value for having the diameter of the silicon hole is all identical, and the design value of the spacing between each adjacent silicon hole is all identical,
A silicon hole in each test structure as test signal input part, another exports as the signal of test
End；
Step 2: by be monitored online data obtain each silicon hole on each silicon substrate diameter test value and
The test value of spacing between each silicon hole, so as to obtain +/- 3 standard deviation of the diameter of all silicon holes and spacing
Statistical monitor value, and be worth to by the Statistical monitor normal distyribution function of the diameter of the silicon hole and each adjacent institute
It states the normal distyribution function of the spacing between silicon hole and the diameter of the silicon hole is calculated by the Statistical monitor value
Normal distyribution function relative to Standard Normal Distribution the first correction factor and calculate each adjacent silicon hole it
Between spacing normal distyribution function relative to the second correction factor of Standard Normal Distribution, second correction factor is
Twice of first correction factor；
The diameter mismatch model and pitch mismatch of silicon hole are established according to first correction factor and second correction factor
Model, the diameter mismatch model of the silicon hole are：
D1 '=D1+ Δ D1,
Δ D1=dm × agauss (0,1,1)；
Wherein, D1 is the design value of the diameter of the silicon hole before correcting and the diameter equal to the silicon hole；D1 ' is passes through
The diameter of the revised silicon hole；Δ D1 is the diameter correction term of the silicon hole；Dm is first correction factor；
The pitch mismatch model of the silicon hole is：
S1 '=S1+2dm × agauss (0,1,1)；
Wherein, S1 is spacing between the adjacent silicon hole before correcting and equal to the spacing between the adjacent silicon hole
Design value；S1 ' is the spacing Jing Guo the revised silicon hole；2dm × agauss (0,1,1) is the spacing of the silicon hole
Correction term；2dm is second correction factor；
The resistance value actual distribution of the silicon hole and inductance value actual distribution are obtained by the on-line monitoring data；
Step 3: establishing resistivity mismatch model, the resistivity mismatch model formula is：
ρ '=ρ+Δ ρ
Wherein, ρ ' is the first resistor rate of the silicon hole, which includes the diameter and spacing by the silicon hole
And the mismatch part generated；ρ is the second resistance rate of the silicon hole, and the second resistance rate is a fixed value, by the silicon
The packing material of through-hole determines；Δ ρ is the mismatch resistivity that is generated by the diameter and spacing of the silicon hole；D is the silicon
The diameter of through-hole, spacing of the S between the adjacent silicon hole, ρ1Become for the mismatch resistivity with the diameter of the silicon hole
The third correction factor of change, ρ2For the 4th correction factor that the mismatch resistivity changes with the spacing of the silicon hole, dx is
The 5th correction factor positioned at the diameter index part of the silicon hole, sx are the spacing exponential part positioned at the silicon hole
6th correction factor；Agauss (0,1,1) is the built-in Standard Normal Distributions of SPIEC, in the bracket of agauss (0,1,1)
First item 0 represent the central value of distribution function 0, the 1 of Section 2 represents distribution function curve from 0 to the right and left maximum
Sigma amplitudes are 1, and the sigma numerical value of 1 expression distribution function of Section 3, wherein sigma numerical tabulars show standard variance；
By the diameter mismatch model of the silicon hole, the pitch mismatch model of the silicon hole and the resistivity mismatch model group
Conjunction forms silicon hole mismatch model；
Step 4: fixed first frequency is selected to carry out Monte Carlo simulation to the silicon hole mismatch model, institute is respectively obtained
State the resistance value emulation distribution of the silicon hole under first frequency and inductance value emulation distribution；
Step 5: by the resistance value emulation distribution of the silicon hole and the resistance value actual distribution, the inductance
Value emulation distribution and the inductance value actual distribution comparison realize to first correction factor, the third correction factor,
The fitting of 4th correction factor, the 5th correction factor and the 6th correction factor makes described after Coefficient Fitting
The resistance value emulation distribution that silicon hole mismatch model obtains is consistent with the resistance value actual distribution, inductance value emulation
Distribution is consistent with the inductance value actual distribution.
2. the method as described in claim 1, it is characterised in that：
The D that is updated in the resistivity mismatch model by the D1 ' in the diameter mismatch model by the silicon hole, will described in
The S that S1 ' in the pitch mismatch model of silicon hole is updated in the resistivity mismatch model obtains the silicon hole mismatch mould
Type.
3. method as claimed in claim 1 or 2, it is characterised in that：The normal distyribution function model of the diameter of the silicon hole,
The normal distyribution function model of spacing between the adjacent silicon hole and the silicon hole mismatch model all use SPICE language
It writes.
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| US8103996B2 (en) * | 2008-06-24 | 2012-01-24 | Cadence Design Systems, Inc. | Method and apparatus for thermal analysis of through-silicon via (TSV) |
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