CN105097435A - Method for adjusting resistance of high resistance polysilicon (HRP) - Google Patents
Method for adjusting resistance of high resistance polysilicon (HRP) Download PDFInfo
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Abstract
The invention provides a method for adjusting resistance of an HRP. The HRP at least comprises a polysilicon layer. The method at least comprises the following steps of a step S1, monitoring the polysilicon layer and acquiring monitoring data; a step S2, pre-estimating the resistance of the HRP according to the monitoring data; and a step S3, when a difference between the pre-estimated resistance of the HRP and a target value, forming a masking layer on the polysilicon layer in online production process of a semiconductor chip, and adjusting the transparency of the masking layer according to the pre-estimated resistance of the HRP for making the resistance of the HRP achieve a target value. According to the method of the invention, through collection of online monitored polysilicon layer key dimension data and offline monitored polysilicon layer resistance data, the resistance of the HRP is pre-estimated. When the difference between the pre-estimated resistance of the HRP and the target value exists, the resistance of the HRP can be adjusted in time in online production process of a semiconductor chip, thereby improving stability of the semiconductor chip.
Description
Technical field
The present invention relates to technical field of semiconductors, particularly relate to a kind of method regulating HRP resistance value.
Background technology
In semiconductor chip, high value fixed resistor is as conventional device, often be designed to SOI (Silicononisolator, silicon on insulated substrate), HRP (HighResistancePolysilicon, high value polyresistor) be the one of high value fixed resistor, silicon structure in HRP adopts polysilicon to realize, and the grid of the polysilicon layer of HRP and MOS device or PIP (Poly-SiIsolatorPoly-Si, polycrystalline silicon-on-insulator-polysilicon) wherein one deck polysilicon generate simultaneously, without the need to making in addition in semiconductor chip.Along with the continuous upgrading of integrated circuit, require that the size of semiconductor chip is more and more less, precision is more and more higher, and response speed is more and more faster, also requires that in circuit, the resistance accuracy of resistance device is more and more higher simultaneously.
But because HRP resistance value affects by multifactorial, as the thickness, CD (CriticalDimension, critical size), ion implantation concentration etc. of polysilicon, so to realize that resistance value is stable certain difficulty.Especially in the semiconductor device production process of a large amount of volume production, at thickness, the size of polysilicon, when the processing procedure formulas such as ion implantation concentration should not change, by the minor variations produced in each fabrication steps on the impact of resistance value but unavoidably (such as, polysilicon layer carries out the manufacturing process of subsequent deposition masking layer after injecting ion, and the resistance value of polysilicon layer may be made to become large or diminish due to the minor variations of the film of masking layer), cause between the HRP resistance value in semiconductor chip finished product and required desired value and have larger fluctuation.
At present, the adjustment of HRP resistance value is generally realized by the concentration of change ion implanted polysilicon layer or the size of control polysilicon layer, but these actions often can only carry out larger adjustment (such as according to the electrical test results that semiconductor chip finished product is in the past final, processing procedure is adjusted, but this adjustment often may occur adjusting mistake, cause between HRP resistance value and required desired value and still there is deviation, the accuracy of HRP resistance value cannot be ensured), and for online product because the impact of fluctuation on resistance value of each fabrication steps is unpredictable and at a loss what to do.Therefore, effective adjustment, adjusts to HRP resistance value the vital task that desired value is the volume production stage.
Summary of the invention
The shortcoming of prior art in view of the above, the object of the present invention is to provide a kind of method regulating HRP resistance value, by carrying out effective fine setting to HRP resistance value, HRP resistance value is adjusted to desired value, for solving in prior art because each step produces the minor variations of board, HRP resistance value is caused to have the problem of relatively large deviation relative to desired value, and HRP resistance value cannot regulate online in time in prior art, can only go to carry out larger adjustment according to the result of the final testing electrical property of semiconductor chip finished product, the problem of the accuracy of HRP resistance value cannot be ensured.
For achieving the above object and other relevant objects, the invention provides a kind of method regulating HRP resistance value, described HRP at least comprises polysilicon layer, and wherein, the method for described adjustment HRP resistance value at least comprises the steps:
Step S1, monitors described polysilicon layer, collects Monitoring Data;
Step S2, according to described Monitoring Data, estimates the resistance value of HRP;
Step S3, when the resistance value of the described HRP estimated and desired value there are differences, in the online production process of semiconductor chip, described polysilicon layer forms masking layer, and according to the described HRP resistance value estimated, regulate and control the light transmission of described masking layer, reach desired value to make the resistance value of described HRP.
Preferably, in step S1, online and off-line monitoring are carried out to described polysilicon layer, collect online monitoring data and off-line monitoring data; Wherein, described online monitoring data at least comprises on-line monitoring polysilicon layer CD data, and described off-line monitoring data at least comprise off-line monitoring polysilicon layer resistance data;
In described step S2, the method estimating the resistance value of described HRP is: statistics resistance relation factor-resistance associated diagram, wherein, described resistance relation factor at least comprises online polysilicon layer critical size and off-line polysilicon layer resistance, and described resistance relation factor-resistance associated diagram at least comprises online polysilicon layer critical size-resistance associated diagram and off-line polysilicon layer resistance-resistance associated diagram; According to the corresponding relation of described online monitoring data and described online polysilicon layer critical size-resistance associated diagram, obtain the first valuation of described HRP resistance value, according to the corresponding relation of described off-line monitoring data and described off-line polysilicon layer resistance-resistance associated diagram, obtain the second valuation of described HRP resistance value, get the first valuation of described HRP resistance value and the mean value of the second valuation as the described HRP resistance value estimated.
Preferably, in step S1, on-line monitoring is carried out to described polysilicon layer, collect online monitoring data; Wherein, described online monitoring data at least comprises on-line monitoring polysilicon layer CD data;
In described step S2, the method estimating the resistance value of described HRP is: statistics resistance relation factor-resistance associated diagram, wherein, described resistance relation factor at least comprises online polysilicon layer critical size, and described resistance relation factor-resistance associated diagram at least comprises online polysilicon layer critical size-resistance associated diagram; According to the corresponding relation of described online monitoring data and described online polysilicon layer critical size-resistance associated diagram, the HRP resistance value estimated described in obtaining.
Preferably, in step S1, off-line monitoring is carried out to described polysilicon layer, collect off-line monitoring data; Wherein, described off-line monitoring data at least comprise off-line monitoring polysilicon layer resistance data;
In described step S2, the method estimating the resistance value of described HRP is: statistics resistance relation factor-resistance associated diagram, wherein, described resistance relation factor at least comprises off-line polysilicon layer resistance, and described resistance relation factor-resistance associated diagram at least comprises off-line polysilicon layer resistance-resistance associated diagram; According to the corresponding relation of described off-line monitoring data and described off-line polysilicon layer resistance-resistance associated diagram, the HRP resistance value estimated described in obtaining.
Preferably, the method for statistics resistance relation factor-resistance associated diagram is: test multiple semiconductor chip in the past adopting same process processing procedure to produce, obtain multiple HRP and have resistance; Add up each described HRP and have resistance and the resistance relation factor corresponding with it, form resistance relation factor-resistance associated diagram with the form of coordinate diagram.
Preferably, the method for described polysilicon layer being carried out to on-line monitoring for: to described in board online production during HRP the polysilicon layer of deposit monitor and measure, to obtain online monitoring data;
The method of described polysilicon layer being carried out to off-line monitoring is: provide a blank wafer; When board off-line suspends the described HRP of production, depositing polysilicon layer on described blank wafer, carries out ion implantation to described polysilicon layer, monitors the polysilicon layer after ion implantation and measures, to obtain off-line monitoring data;
Wherein, same process processing procedure depositing polysilicon layer is adopted when online and off-line monitoring being carried out to described polysilicon layer; Same process processing procedure is adopted to carry out ion implantation to described polysilicon layer during HRP during the board off-line time-out described HRP of production and described in board online production.
Preferably, the method for described polysilicon layer being carried out to on-line monitoring for: to described in board online production during HRP the polysilicon layer of deposit monitor and measure, to obtain online monitoring data.
Preferably, to the method that described polysilicon layer carries out on-line monitoring be: a blank wafer is provided; When board off-line suspends the described HRP of production, depositing polysilicon layer on described blank wafer, carries out ion implantation to described polysilicon layer, monitors the polysilicon layer after ion implantation and measures, to obtain off-line monitoring data; Wherein, polysilicon layer described in deposit and when carrying out ion implantation to described polysilicon layer on described blank wafer, adopts and manufacturing process identical during HRP described in board online production.
Preferably, in described step S3, the method that regulation and control are covered in the light transmittance of the masking layer on described HRP is: add up the light transmittance that described HRP has resistance and the described masking layer corresponding with it, form light transmittance-resistance associated diagram, add up the light transmittance of described masking layer and the gas flow of the described masking layer of the generation corresponding with it simultaneously, form light transmittance-gas flow contingency table; According to the difference that the described HRP resistance value estimated and described desired value exist, the difference of the light transmittance that the HRP resistance value estimated described in obtaining is corresponding in described light transmittance-resistance associated diagram with described desired value; According to the transmissivity difference of the described masking layer existed between the described HRP resistance value estimated and described desired value, in conjunction with described light transmittance-gas flow contingency table, by the light transmittance regulating the gas flow generating described masking layer to regulate and control described masking layer, to change the density of described masking layer, described HRP resistance value is made to reach described desired value.
Preferably, adopt masking layer described in CVD or PVD Process Production, the gas generating described masking layer at least comprises SiH
4, the light transmittance of described masking layer is suitable for by regulating SiH
4flow regulate and control.
Preferably, described masking layer is self-aligned metal silicate layer or silicon rich oxide layer.
Preferably, described HRP at least comprises soi structure, described soi structure comprises: substrate, is positioned at the local oxidation of silicon layer on described substrate or shallow groove isolation layer, is positioned at the polysilicon layer after the ion implantation on described local oxidation of silicon layer or shallow groove isolation layer.
As mentioned above, the method for adjustment HRP resistance value of the present invention, has following beneficial effect:
1, by the collection to on-line monitoring polysilicon layer CD data and off-line monitoring polysilicon layer resistance data, estimate out the resistance value of HRP, but not current just see HRP resistance value result when can only arrive the final testing electrical property of semiconductor chip, thus can when the HRP resistance value estimated and desired value have deviation, in the online production process of semiconductor chip, adjust HRP resistance value in time, thus improve the stability of semiconductor chip.
2, the next timely on-line fine HRP resistance value of performance of the masking layer on HRP is covered in by regulation and control, fully consider the critical size of polysilicon layer and the expection of ion implantation, utilize the control of gas flow when generating masking layer online, regulate and control masking layer light transmittance this affect the correlative factor of HRP resistance value, thus fine setting HRP resistance value, reach desired value to make HRP resistance value.
Accompanying drawing explanation
Fig. 1 is shown as the method flow schematic diagram of the adjustment HRP resistance value of the embodiment of the present invention.
Fig. 2 is shown as HRP generalized section in the method for the adjustment HRP resistance value of the embodiment of the present invention.
Fig. 3 is shown as the some processes schematic flow sheet covering masking layer in the method for the adjustment HRP resistance value of the embodiment of the present invention on HRP.
Fig. 4 is shown as the schematic diagram of online polysilicon layer critical size-resistance associated diagram in the method for the adjustment HRP resistance value of the embodiment of the present invention.
Fig. 5 is shown as the schematic diagram of off-line polysilicon layer resistance-resistance associated diagram in the method for the adjustment HRP resistance value of the embodiment of the present invention.
Fig. 6 is shown as the schematic diagram of light transmittance-resistance associated diagram and light transmittance-gas flow contingency table in the method for the adjustment HRP resistance value of the embodiment of the present invention.
Fig. 7 is shown as the contrast schematic diagram of the HRP resistance value adopted before and after embodiment of the present invention regulation and control.
Element numbers explanation
S1 ~ S3 step
1 substrate
2 local oxidation of silicon layer or shallow groove isolation layers
Polysilicon layer after 3 ion implantations
4 masking layers
Embodiment
Below by way of specific instantiation, embodiments of the present invention are described, those skilled in the art the content disclosed by this specification can understand other advantages of the present invention and effect easily.The present invention can also be implemented or be applied by embodiments different in addition, and the every details in this specification also can based on different viewpoints and application, carries out various modification or change not deviating under spirit of the present invention.
Refer to Fig. 1, the embodiment of the present invention relates to a kind of method regulating HRP resistance value.It should be noted that, the diagram provided in the present embodiment only illustrates basic conception of the present invention in a schematic way, then only the assembly relevant with the present invention is shown in graphic but not component count, shape and size when implementing according to reality is drawn, it is actual when implementing, and the kenel of each assembly, quantity and ratio can be a kind of change arbitrarily, and its assembly layout kenel also may be more complicated.
The method of the adjustment HRP resistance value of the present embodiment, HRP at least comprises polysilicon layer; The present embodiment at least comprises the steps:
Step S1, monitors polysilicon layer, collects Monitoring Data;
Step S2, according to Monitoring Data, estimates the resistance value of HRP;
Step S3, when the HRP resistance value estimated and desired value there are differences, in the online production process of semiconductor chip, form masking layer on the polysilicon layer, and according to the HRP resistance value estimated, the light transmission of regulation and control masking layer, reaches desired value to make the resistance value of HRP.
Wherein, for HRP, as shown in Figure 2, at least comprise soi structure, this soi structure comprises: substrate 1, is positioned at the local oxidation of silicon layer on substrate 1 or shallow groove isolation layer 2, is positioned at the polysilicon layer 3 after the ion implantation on local oxidation of silicon layer or shallow groove isolation layer 2.Substrate 1 adopts monocrystalline silicon or monocrystalline substrate usually.In common technique, wherein one deck polysilicon layer of the polysilicon layer of HRP and the grid of MOS device or PIP generates simultaneously.The technological process referred to as shown in Figure 3 (is omitted in figure and is provided substrate 1, make local oxidation of silicon layer or shallow groove isolation layer 2 on substrate 1, the step such as depositing polysilicon layer on local oxidation of silicon layer or shallow groove isolation layer 2), its technique comprises: according to semiconductor chip need polysilicon layer is etched, then ion implantation (IMP is carried out to the polysilicon layer after etching, IonImplant), then deposit masking layer on polysilicon layer 3 after ion implantation, wherein, masking layer can pass through photoetching as mask in subsequent technique, use after etching.And in the present embodiment, polysilicon layer is carried out to the process of on-line monitoring from etches polycrystalline silicon layer, and be continued until that masking layer deposit completes; The process of polysilicon layer being carried out to off-line monitoring is then when board off-line suspends production HRP (or claiming idle, neutral gear), from ion implanted polysilicon layer, lasts till that masking layer deposit completes.
For the present embodiment, when estimating out the resistance value of HRP, in order to obtain the HRP resistance value estimated more accurately, need to consider on-line monitoring polysilicon layer CD data and off-line monitoring polysilicon layer resistance data simultaneously.Specifically, in step sl, online and off-line monitoring are carried out to polysilicon layer, collect online monitoring data and off-line monitoring data; Wherein, online monitoring data at least comprises on-line monitoring polysilicon layer CD data, and off-line monitoring data at least comprise off-line monitoring polysilicon layer resistance data; In step s 2, the method estimating the resistance value of HRP is: statistics resistance relation factor-resistance associated diagram, wherein, resistance relation factor at least comprises online polysilicon layer critical size and off-line polysilicon layer resistance, and resistance relation factor-resistance associated diagram at least comprises online polysilicon layer critical size-resistance associated diagram and off-line polysilicon layer resistance-resistance associated diagram; According to the corresponding relation of online monitoring data and online polysilicon layer critical size-resistance associated diagram, obtain the first valuation of HRP resistance value, according to the corresponding relation of off-line monitoring data and off-line polysilicon layer resistance-resistance associated diagram, obtain the second valuation of HRP resistance value, get the first valuation of HRP resistance value and the mean value of the second valuation as the HRP resistance value estimated.
For other embodiment, when estimating out the resistance value of HRP, if lower to the precise requirements of the HRP resistance value estimated, then only need to consider on-line monitoring polysilicon layer CD data or off-line monitoring polysilicon layer resistance data.If only consider on-line monitoring polysilicon layer CD data, in step sl, on-line monitoring is carried out to polysilicon layer, collect online monitoring data; Wherein, online monitoring data at least comprises on-line monitoring polysilicon layer CD data; In step s 2, the method estimating the resistance value of HRP is: statistics resistance relation factor-resistance associated diagram, wherein, resistance relation factor at least comprises online polysilicon layer critical size, and resistance relation factor-resistance associated diagram at least comprises online polysilicon layer critical size-resistance associated diagram; According to the corresponding relation of online monitoring data and online polysilicon layer critical size-resistance associated diagram, obtain the HRP resistance value estimated.If only consider off-line monitoring polysilicon layer resistance data, in step sl, off-line monitoring is carried out to polysilicon layer, collect off-line monitoring data; Wherein, off-line monitoring data at least comprise off-line monitoring polysilicon layer resistance data; In step s 2, the method estimating the resistance value of HRP is: statistics resistance relation factor-resistance associated diagram, wherein, resistance relation factor at least comprises off-line polysilicon layer resistance, and resistance relation factor-resistance associated diagram at least comprises off-line polysilicon layer resistance-resistance associated diagram; According to the corresponding relation of off-line monitoring data and off-line polysilicon layer resistance-resistance associated diagram, obtain the HRP resistance value estimated.
In the present embodiment and other embodiment, the method for statistics resistance relation factor-resistance associated diagram is: test multiple semiconductor chip in the past adopting same process processing procedure to produce, obtain multiple HRP and have resistance; Add up each HRP and have resistance and the resistance relation factor corresponding with it, form resistance relation factor-resistance associated diagram with the form of coordinate diagram.Such as, statistics HRP has resistance RS and the online polysilicon layer critical size CD corresponding with it, forms online polysilicon layer critical size-resistance associated diagram, as shown in Figure 4; Statistics HRP has resistance RS and the off-line polysilicon layer resistance RS_Offline corresponding with it, forms off-line polysilicon layer resistance-resistance associated diagram, as shown in Figure 5.
Due in the usual technique of semiconductor chip, the polysilicon layer of each HRP needs throughput measurement equipment to measure its critical size when generating online, and retained data, then after semiconductor chip completes, carry out final testing electrical property, obtain HRP and have resistance RS data; Therefore for the semiconductor chip produced in a large number in the past, resistance RS data are had except test obtains a large amount of HRP, also exist and have a large amount of online polysilicon layer critical size CD data corresponding to resistance RS with these HRP, these two kinds of data are associated by the mode of coordinate diagram, form online polysilicon layer critical size-resistance associated diagram, thus the relevance between them is embodied.
In addition, because ion implantation concentration is the key factor affecting HRP resistance value, the HRP resistance value that different ion implantation concentrations obtains is different, and multiple HRP that the semiconductor chip that test was produced in the past obtains have resistance, wherein, the ion implantation concentration of the polysilicon layer of HRP can have a variety of.Now we adopt a kind of mode of off-line to measure off-line polysilicon layer resistance (this mode is with to carry out the method for off-line monitoring to polysilicon layer in step S1 identical, be introduced to the method for off-line monitoring afterwards): get multiple blank wafer, when board off-line, on each blank wafer, depositing polysilicon layer (certainly, here the processing procedure of depositing polysilicon layer is identical with the processing procedure of the HRP of existing resistance), polysilicon layer on each blank wafer is carried out to the ion implantation of variable concentrations, measure the resistance of the polysilicon layer after ion implantation, thus obtain multiple off-line polysilicon layer resistance RS_Offline data.Each semiconductor chip in the past produced, the polysilicon layer of its HRP is in ion implantation process, a corresponding ion implantation concentration, but due to the minor variations produced in each front procedure step during board online production HRP, adopt the ion implantation process of this concentration may obtain multiple off-line polysilicon layer resistance RS_Offline data; Therefore for multiple semiconductor chip produced in the past, resistance RS data are had except test obtains multiple HRP, also to exist and these HRP have more off-line polysilicon layer resistance RS_Offline data corresponding to the ion implantation concentration of resistance RS, these two kinds of data are associated by the mode of coordinate diagram, form off-line polysilicon layer resistance-resistance associated diagram, thus the relevance between them is embodied.
Certainly, ion implantation type is also the key factor affecting HRP resistance value, as other embodiment of the present invention, type (such as B, P plasma) can also be injected according to different ions and form different off-line polysilicon layer resistance-resistance associated diagrams, its method is similar to the present embodiment, does not repeat at this.
The present embodiment to the method that polysilicon layer carries out on-line monitoring is: monitor and measure the polysilicon layer of deposit during board online production HRP, to obtain online monitoring data; The method of polysilicon layer being carried out to off-line monitoring is: provide a blank wafer; When board off-line suspends production HRP, depositing polysilicon layer on blank wafer, carries out ion implantation to polysilicon layer, monitors the polysilicon layer after ion implantation and measures, to obtain off-line monitoring data; Wherein, same process processing procedure depositing polysilicon layer is adopted when online and off-line monitoring being carried out to polysilicon layer; Board off-line suspend when producing HRP and board online production HRP time adopt same process processing procedure to carry out ion implantation to polysilicon layer.
For other embodiment, if only consider on-line monitoring polysilicon layer CD data, the method for polysilicon layer being carried out to on-line monitoring is: monitor and measure the polysilicon layer of deposit during board online production HRP, to obtain online monitoring data.If only consider off-line monitoring polysilicon layer resistance data, the method for polysilicon layer being carried out to on-line monitoring is: provide a blank wafer; When board off-line suspends production HRP, depositing polysilicon layer on blank wafer, carries out ion implantation to polysilicon layer, monitors the polysilicon layer after ion implantation and measures, to obtain off-line monitoring data; Wherein, depositing polysilicon layer and when carrying out ion implantation to polysilicon layer on blank wafer, adopts the manufacturing process identical with during board online production HRP.
In the present embodiment, after obtaining Monitoring Data, respectively by online monitoring data, the corresponding online polysilicon layer critical size-resistance associated diagram of off-line monitoring data, off-line polysilicon layer resistance-resistance associated diagram, then the first valuation RS1 and the second valuation RS2 of HRP resistance value is obtained respectively, first valuation RS1 and the second valuation RS2 is exactly the possible range value of HRP resistance value, get the first valuation RS1 and the second valuation RS2 median as the HRP resistance value estimated, two factors affecting HRP resistance value have been considered: online polysilicon layer critical size and off-line polysilicon layer resistance simultaneously, make the HRP resistance value estimated more accurate.
In the present embodiment step S3, the method that regulation and control are covered in the light transmittance of the masking layer on HRP is: statistics HRP has the light transmittance of resistance and the masking layer corresponding with it, form light transmittance-resistance associated diagram, the light transmittance of statistical masking layer and the gas flow of the generation masking layer corresponding with it simultaneously, form light transmittance-gas flow contingency table, as shown in Figure 6; According to the difference that the HRP resistance value estimated and desired value exist, the difference of the light transmittance that the HRP resistance value obtaining estimating is corresponding in light transmittance-resistance associated diagram with desired value; According to the transmissivity difference of the masking layer existed between the HRP resistance value estimated and desired value, in conjunction with light transmittance-gas flow contingency table, by the light transmittance regulating the gas flow generating masking layer to regulate masking layer, to change the density of masking layer, HRP resistance value is made to reach desired value.
Wherein, adopt CVD or PVD Process Production masking layer, the gas generating masking layer at least comprises SiH
4, the light transmittance of masking layer is suitable for by regulating SiH
4flow regulate and control.Masking layer is self-aligned metal silicate layer or silicon rich oxide layer.
Light transmittance is the one of the film of masking layer, in other embodiment of the present invention, except regulation and control are covered in the light transmittance of the masking layer on HRP, other that can also regulate and control to be covered in the masking layer on HRP can affect the film of HRP resistance value, such as stress etc., and the present embodiment is for light transmittance.
After semiconductor chip completes, carry out final testing electrical property, having resistance RS data except obtaining HRP, also obtaining the light transmittance RI being covered in the masking layer on HRP; Therefore for multiple semiconductor chip produced in the past, resistance RS data are had except test obtains multiple HRP, also there is the transmittance data having multiple masking layers corresponding to resistance RS with these HRP, these two kinds of data are associated by the mode of coordinate diagram, form light transmittance-resistance associated diagram, thus the relevance between them is embodied.
Respectively the HRP in the HRP resistance value estimated and the corresponding light transmittance-resistance associated diagram of desired value is had resistance ordinate, when the HRP resistance value estimated and desired value there are differences, the first light transmittance RI1 that the HRP resistance value that can obtain respectively estimating is corresponding and the second light transmittance RI2 corresponding to desired value, first light transmittance RI1 corresponding to the HRP resistance value estimated the obviously second light transmittance RI2 corresponding with desired value also exists difference, only have and by regulation and control, the difference between them is eliminated, HRP resistance value just can be made to reach desired value.
Please continue to refer to the light transmittance shown in Fig. 6-resistance associated diagram, this figure shows, the light transmittance of masking layer is the key factor affecting HRP resistance value.Specifically, resistivity due to HRP is one of decision condition of HRP resistance value, it is subject to the masking layer impact covered thereon, when the density of masking layer is lower, the tightness degree of the atomic arrangement in masking layer is lower, and the light transmittance of masking layer is higher, and the resistivity of HRP is lower, thus make HRP resistance value lower, vice versa.Therefore, in the online production process of semiconductor chip, the light transmittance of masking layer reflects the density of masking layer; And the density of masking layer is the gas flow control being subject to generation masking layer, gas flow is larger, and the tightness degree of the atomic arrangement in masking layer is higher, and the density of masking layer is higher, and vice versa.For Fig. 6, the gas flow of light transmittance RI 1.50 time is 80sccm, and thereafter, light transmittance RI often increases by 0.01, and gas flow recruitment N is 10sccm.
We also can data draw by experiment: the light transmittance of masking layer is associated with the uniformity of the gas flow size and masking layer that generate masking layer, to generate a kind of gas silane SiH of masking layer
4for example, draw SiH by experiment
4, relation between light transmittance RI and uniformity U three, as shown in table 1 below:
Table 1
Because the precision of the uniformity of masking layer is high, do not affect the enforcement of the present embodiment, therefore the present embodiment will not be considered.The present embodiment only need in the online production process of semiconductor chip, the light transmittance of masking layer just can be regulated and controled by the gas flow of on-line fine generation masking layer, difference between the second light transmittance RI2 that the first light transmittance RI1 making the HRP resistance value estimated corresponding is corresponding with desired value is eliminated, thus change the density of masking layer, HRP resistance value can be adjusted in time, reach desired value.
Fig. 7 is shown as the HRP resistance value contrast schematic diagram adopted before and after the present embodiment regulation and control, abscissa is testDate, ordinate is the actual HRP resistance value R recorded, and in figure, leading portion does not adopt the method for the present embodiment, tests the HRP resistance value fluctuation obtained obvious, big rise and fall, HRP resistance value is unstable, and after adopting the method for the present embodiment to be controlled, the HRP resistance value fluctuation convergence of figure posterior segment, HRP resistance value stability significantly improves, and makes the stability of semiconductor chip have also been obtained raising.
To sum up, the method of adjustment HRP resistance value of the present invention, by the collection to on-line monitoring polysilicon layer CD data and off-line monitoring polysilicon layer resistance data, estimate out the resistance value of HRP, but not current just see HRP resistance value result when can only arrive the final testing electrical property of semiconductor chip, thus when the HRP resistance value estimated and desired value have deviation, in the online production process of semiconductor chip, HRP resistance value can be adjusted in time, thus improve the stability of semiconductor chip.And, the performance that the present invention is covered in the masking layer on HRP by regulation and control carrys out timely on-line fine HRP resistance value, fully consider the critical size of polysilicon layer and the expection of ion implantation, utilize the control of gas flow when generating masking layer online, regulate and control masking layer light transmittance this affect the correlative factor of HRP resistance value, thus fine setting HRP resistance value, reach desired value to make HRP resistance value.So the present invention effectively overcomes various shortcoming of the prior art and tool high industrial utilization.
Above-described embodiment is illustrative principle of the present invention and effect thereof only, but not for limiting the present invention.Any person skilled in the art scholar all without prejudice under spirit of the present invention and category, can modify above-described embodiment or changes.Therefore, such as have in art usually know the knowledgeable do not depart from complete under disclosed spirit and technological thought all equivalence modify or change, must be contained by claim of the present invention.
Claims (12)
1. regulate a method for HRP resistance value, described HRP at least comprises polysilicon layer, it is characterized in that, the method for described adjustment HRP resistance value at least comprises the steps:
Step S1, monitors described polysilicon layer, collects Monitoring Data;
Step S2, according to described Monitoring Data, estimates the resistance value of HRP;
Step S3, when the resistance value of the described HRP estimated and desired value there are differences, in the online production process of semiconductor chip, described polysilicon layer forms masking layer, and according to the described HRP resistance value estimated, regulate and control the light transmission of described masking layer, reach desired value to make the resistance value of described HRP.
2. the method for adjustment HRP resistance value according to claim 1, is characterized in that, in step S1, carry out online and off-line monitoring to described polysilicon layer, collect online monitoring data and off-line monitoring data; Wherein, described online monitoring data at least comprises on-line monitoring polysilicon layer CD data, and described off-line monitoring data at least comprise off-line monitoring polysilicon layer resistance data;
In described step S2, the method estimating the resistance value of described HRP is: statistics resistance relation factor-resistance associated diagram, wherein, described resistance relation factor at least comprises online polysilicon layer critical size and off-line polysilicon layer resistance, and described resistance relation factor-resistance associated diagram at least comprises online polysilicon layer critical size-resistance associated diagram and off-line polysilicon layer resistance-resistance associated diagram; According to the corresponding relation of described online monitoring data and described online polysilicon layer critical size-resistance associated diagram, obtain the first valuation of described HRP resistance value, according to the corresponding relation of described off-line monitoring data and described off-line polysilicon layer resistance-resistance associated diagram, obtain the second valuation of described HRP resistance value, get the first valuation of described HRP resistance value and the mean value of the second valuation as the described HRP resistance value estimated.
3. the method for adjustment HRP resistance value according to claim 1, is characterized in that, in step S1, carry out on-line monitoring to described polysilicon layer, collect online monitoring data; Wherein, described online monitoring data at least comprises on-line monitoring polysilicon layer CD data;
In described step S2, the method estimating the resistance value of described HRP is: statistics resistance relation factor-resistance associated diagram, wherein, described resistance relation factor at least comprises online polysilicon layer critical size, and described resistance relation factor-resistance associated diagram at least comprises online polysilicon layer critical size-resistance associated diagram; According to the corresponding relation of described online monitoring data and described online polysilicon layer critical size-resistance associated diagram, the HRP resistance value estimated described in obtaining.
4. the method for adjustment HRP resistance value according to claim 1, is characterized in that, in step S1, carry out off-line monitoring to described polysilicon layer, collect off-line monitoring data; Wherein, described off-line monitoring data at least comprise off-line monitoring polysilicon layer resistance data;
In described step S2, the method estimating the resistance value of described HRP is: statistics resistance relation factor-resistance associated diagram, wherein, described resistance relation factor at least comprises off-line polysilicon layer resistance, and described resistance relation factor-resistance associated diagram at least comprises off-line polysilicon layer resistance-resistance associated diagram; According to the corresponding relation of described off-line monitoring data and described off-line polysilicon layer resistance-resistance associated diagram, the HRP resistance value estimated described in obtaining.
5. the method for the adjustment HRP resistance value according to any one of claim 2-4, it is characterized in that, the method of statistics resistance relation factor-resistance associated diagram is: test multiple semiconductor chip in the past adopting same process processing procedure to produce, obtain multiple HRP and have resistance; Add up each described HRP and have resistance and the resistance relation factor corresponding with it, form resistance relation factor-resistance associated diagram with the form of coordinate diagram.
6. the method for adjustment HRP resistance value according to claim 2, it is characterized in that, the method of described polysilicon layer being carried out to on-line monitoring for: to described in board online production during HRP the polysilicon layer of deposit monitor and measure, to obtain online monitoring data;
The method of described polysilicon layer being carried out to off-line monitoring is: provide a blank wafer; When board off-line suspends the described HRP of production, depositing polysilicon layer on described blank wafer, carries out ion implantation to described polysilicon layer, monitors the polysilicon layer after ion implantation and measures, to obtain off-line monitoring data;
Wherein, same process processing procedure depositing polysilicon layer is adopted when online and off-line monitoring being carried out to described polysilicon layer; Same process processing procedure is adopted to carry out ion implantation to described polysilicon layer during HRP during the board off-line time-out described HRP of production and described in board online production.
7. the method for adjustment HRP resistance value according to claim 3, it is characterized in that, the method of described polysilicon layer being carried out to on-line monitoring for: to described in board online production during HRP the polysilicon layer of deposit monitor and measure, to obtain online monitoring data.
8. the method for adjustment HRP resistance value according to claim 4, it is characterized in that, the method for described polysilicon layer being carried out to on-line monitoring is: provide a blank wafer; When board off-line suspends the described HRP of production, depositing polysilicon layer on described blank wafer, carries out ion implantation to described polysilicon layer, monitors the polysilicon layer after ion implantation and measures, to obtain off-line monitoring data; Wherein, polysilicon layer described in deposit and when carrying out ion implantation to described polysilicon layer on described blank wafer, adopts and manufacturing process identical during HRP described in board online production.
9. the method for the adjustment HRP resistance value according to any one of claim 1-4, it is characterized in that, in described step S3, the method that regulation and control are covered in the light transmittance of the masking layer on described HRP is: add up the light transmittance that described HRP has resistance and the described masking layer corresponding with it, form light transmittance-resistance associated diagram, add up the light transmittance of described masking layer and the gas flow of the described masking layer of the generation corresponding with it simultaneously, form light transmittance-gas flow contingency table; According to the difference that the described HRP resistance value estimated and described desired value exist, the difference of the light transmittance that the HRP resistance value estimated described in obtaining is corresponding in described light transmittance-resistance associated diagram with described desired value; According to the transmissivity difference of the described masking layer existed between the described HRP resistance value estimated and described desired value, in conjunction with described light transmittance-gas flow contingency table, by the light transmittance regulating the gas flow generating described masking layer to regulate and control described masking layer, to change the density of described masking layer, described HRP resistance value is made to reach described desired value.
10. the method for adjustment HRP resistance value according to claim 9, it is characterized in that, adopt masking layer described in CVD or PVD Process Production, the gas generating described masking layer at least comprises SiH
4, the light transmittance of described masking layer is suitable for by regulating SiH
4flow regulate and control.
The method of 11. adjustment HRP resistance values according to any one of claim 1-4, it is characterized in that, described masking layer is self-aligned metal silicate layer or silicon rich oxide layer.
The method of 12. adjustment HRP resistance values according to any one of claim 1-4, it is characterized in that, described HRP at least comprises soi structure, described soi structure comprises: substrate, be positioned at the local oxidation of silicon layer on described substrate or shallow groove isolation layer, be positioned at the polysilicon layer after the ion implantation on described local oxidation of silicon layer or shallow groove isolation layer.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108345275A (en) * | 2017-01-25 | 2018-07-31 | 中芯国际集成电路制造(上海)有限公司 | Equipment monitoring system and apparatus monitoring method |
| CN111276415A (en) * | 2020-02-18 | 2020-06-12 | 京东方科技集团股份有限公司 | Display substrate, preparation method thereof and display device |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5065221A (en) * | 1988-09-30 | 1991-11-12 | Kabushiki Kaisha Toshiba | Trimming resistor element for microelectronic circuit |
| JP2008277638A (en) * | 2007-05-01 | 2008-11-13 | Rohm Co Ltd | Chip resistor and manufacturing method therefor |
| CN102110593A (en) * | 2010-12-15 | 2011-06-29 | 无锡中微晶园电子有限公司 | Method for improving stability of polysilicon thin-film resistor |
| CN103346142A (en) * | 2013-06-04 | 2013-10-09 | 上海华力微电子有限公司 | Test key structure and method for monitoring etching capacity of contact holes in etching process |
-
2014
- 2014-05-21 CN CN201410217876.1A patent/CN105097435B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5065221A (en) * | 1988-09-30 | 1991-11-12 | Kabushiki Kaisha Toshiba | Trimming resistor element for microelectronic circuit |
| JP2008277638A (en) * | 2007-05-01 | 2008-11-13 | Rohm Co Ltd | Chip resistor and manufacturing method therefor |
| CN102110593A (en) * | 2010-12-15 | 2011-06-29 | 无锡中微晶园电子有限公司 | Method for improving stability of polysilicon thin-film resistor |
| CN103346142A (en) * | 2013-06-04 | 2013-10-09 | 上海华力微电子有限公司 | Test key structure and method for monitoring etching capacity of contact holes in etching process |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108345275A (en) * | 2017-01-25 | 2018-07-31 | 中芯国际集成电路制造(上海)有限公司 | Equipment monitoring system and apparatus monitoring method |
| CN111276415A (en) * | 2020-02-18 | 2020-06-12 | 京东方科技集团股份有限公司 | Display substrate, preparation method thereof and display device |
| CN111276415B (en) * | 2020-02-18 | 2023-11-07 | 京东方科技集团股份有限公司 | Display substrate, preparation method thereof and display device |
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