CN105097435B - A kind of method of regulation HRP resistance values - Google Patents
A kind of method of regulation HRP resistance values Download PDFInfo
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- CN105097435B CN105097435B CN201410217876.1A CN201410217876A CN105097435B CN 105097435 B CN105097435 B CN 105097435B CN 201410217876 A CN201410217876 A CN 201410217876A CN 105097435 B CN105097435 B CN 105097435B
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Abstract
The present invention provides a kind of method of regulation HRP resistance values, and the HRP comprises at least polysilicon layer, including at least following steps：Step S1, the polysilicon layer is monitored, collects Monitoring Data；Step S2, according to the Monitoring Data, estimate HRP resistance value；Step S3, when the HRP estimated resistance value has differences with desired value, during the online production of semiconductor chip, masking layer is formed on the polysilicon layer, and according to the HRP resistance values estimated, regulate and control the translucency of the masking layer, so that the resistance value of the HRP reaches desired value.The present invention passes through the collection to on-line monitoring polysilicon layer CD data and off-line monitoring polysilicon layer resistance data, estimate out HRP resistance value, can be when the HRP resistance values and desired value estimated have deviation, HRP resistance values are adjusted in time during the online production of semiconductor chip, so as to improve the stability of semiconductor chip.
Description
Technical field
The present invention relates to technical field of semiconductors, more particularly to a kind of method of regulation HRP resistance values.
Background technology
In semiconductor chip, high value fixed resister is frequently designed to SOI (Silicon as conventional device
On isolator, silicon on insulated substrate), HRP (High Resistance Polysilicon, high value polysilicon resistance
Device) be high value fixed resister one kind, the silicon structure in HRP realized using polysilicon, and HRP polysilicon layer with
Wherein more than one layer of grid or PIP (Poly-Si Isolator Poly-Si, polycrystalline silicon-on-insulator-polysilicon) of MOS device
Crystal silicon generates simultaneously, without being made in addition in semiconductor chip.With the continuous upgrading of integrated circuit, it is desirable to semiconductor chip
Size it is less and less, precision more and more higher, response speed is more and more faster, at the same also require resistance device in circuit resistance essence
Spend more and more higher.
But because HRP resistance values are influenceed by multifactor, thickness, CD such as polysilicon (Critical Dimension,
Critical size), ion implantation concentration etc., so to realize that resistance value stabilization has certain difficulty.Especially the half of a large amount of volume productions
In conductor device production process, feelings that the processing procedure such as thickness, size, the ion implantation concentration formula in polysilicon should not change
Under condition, by influence of the caused minor variations to resistance value in each fabrication steps it is inevitable (for example, polysilicon layer inject from
The manufacturing process of subsequent deposition masking layer is carried out after son, and because the minor variations of the film of masking layer may make polysilicon layer
Resistance value become big or diminish), cause to have between the HRP resistance values in semiconductor chip finished product and required desired value larger
Fluctuation.
At present, the regulation of HRP resistance values is generally by the concentration or control polycrystalline for changing ion implanted polysilicon layer
The size of silicon layer realizes, but these actions often can only electrical test results final according to conventional semiconductor chip finished product enter
The larger adjustment of row (for example, processing procedure is adjusted, but this adjustment is often possible to adjustment mistake occur, causes HRP resistance values
Between required desired value still deviation be present, the accuracy of HRP resistance values can not be ensured), and for online product by
It is unpredictable and at a loss what to do in influence of the fluctuation to resistance value of each fabrication steps.Therefore, effective regulation, by HRP
Resistance value is adjusted to the vital task that desired value is the volume production stage.
The content of the invention
In view of the above the shortcomings that prior art, it is an object of the invention to provide a kind of side of regulation HRP resistance values
Method, by carrying out effective fine setting to HRP resistance values, HRP resistance values are adjusted to desired value, for solving prior art
In due to each step production board minor variations, cause HRP resistance values to have the problem of relatively large deviation relative to desired value, and
HRP resistance values can not be adjusted in time online in the prior art, can only be according to the result of the final electrical testing of semiconductor chip finished product
Go to carry out larger adjustment, the problem of accuracy of HRP resistance values can not be ensured.
In order to achieve the above objects and other related objects, the present invention provides a kind of method of regulation HRP resistance values, described
HRP comprises at least polysilicon layer, wherein, the method for the regulation HRP resistance values comprises at least following steps：
Step S1, the polysilicon layer is monitored, collects Monitoring Data；
Step S2, according to the Monitoring Data, estimate HRP resistance value；
When step S3, the HRP estimated resistance value have differences with desired value, in the online production of semiconductor chip
During, masking layer is formed on the polysilicon layer, and according to the HRP resistance values estimated, regulate and control the masking layer
Translucency, so that the resistance value of the HRP reaches desired value.
Preferably, in step S1, online and offline monitoring is carried out to the polysilicon layer, collect online monitoring data and from
Line Monitoring Data；Wherein, the online monitoring data comprises at least on-line monitoring polysilicon layer CD data, described offline
Monitoring Data comprises at least off-line monitoring polysilicon layer resistance data；
In the step S2, the method for estimating the resistance value of the HRP is：Resistance relation factor-resistance associated diagram is counted,
Wherein, the resistance relation factor comprises at least online polysilicon layer critical size and offline polysilicon layer resistance, the resistance
Relation factor-resistance associated diagram comprise at least online polysilicon layer critical size-resistance associated diagram and offline polysilicon layer resistance-
Resistance associated diagram；Closed according to the online monitoring data and online the corresponding of polysilicon layer critical size-resistance associated diagram
System, obtains the first valuation of the HRP resistance values, according to the off-line monitoring data and the offline polysilicon layer resistance-resistance
It is worth the corresponding relation of associated diagram, obtains the second valuation of the HRP resistance values, takes the first valuation and the of the HRP resistance values
The HRP resistance values that the average value of two valuations is estimated as described in.
Preferably, in step S1, the polysilicon layer is monitored on-line, collects online monitoring data；Wherein, it is described
Online monitoring data comprises at least on-line monitoring polysilicon layer CD data；
In the step S2, the method for estimating the resistance value of the HRP is：Resistance relation factor-resistance associated diagram is counted,
Wherein, the resistance relation factor comprises at least online polysilicon layer critical size, the resistance relation factor-resistance associated diagram
Including at least online polysilicon layer critical size-resistance associated diagram；According to the online monitoring data and the online polysilicon
The corresponding relation of layer critical size-resistance associated diagram, obtain the HRP resistance values estimated.
Preferably, in step S1, off-line monitoring is carried out to the polysilicon layer, collects off-line monitoring data；Wherein, it is described
Off-line monitoring data comprise at least off-line monitoring polysilicon layer resistance data；
In the step S2, the method for estimating the resistance value of the HRP is：Resistance relation factor-resistance associated diagram is counted,
Wherein, the resistance relation factor comprises at least offline polysilicon layer resistance, and the resistance relation factor-resistance associated diagram is at least
Including offline polysilicon layer resistance-resistance associated diagram；According to the off-line monitoring data and the offline polysilicon layer resistance-resistance
It is worth the corresponding relation of associated diagram, obtains the HRP resistance values estimated.
Preferably, the method for statistics resistance relation factor-resistance associated diagram is：Test and multiple used same process system in the past
The semiconductor chip of journey production, obtain the existing resistances of multiple HRP；The each existing resistances of the HRP of statistics and corresponding resistance
It is worth relation factor, resistance relation factor-resistance associated diagram is formed in the form of coordinate diagram.
Preferably, the method monitored on-line to the polysilicon layer is：To being deposited described in board online production during HRP
Polysilicon layer be monitored and measure, to obtain online monitoring data；
To the polysilicon layer carry out off-line monitoring method be：One blank wafer is provided；When board suspends production offline
During the HRP, the depositing polysilicon layer on the blank wafer, ion implanting is carried out to the polysilicon layer, to ion implanting
Polysilicon layer afterwards is monitored and measured, to obtain off-line monitoring data；
Wherein, same process processing procedure depositing polysilicon layer is used when carrying out online and offline monitoring to the polysilicon layer；
Board suspends when producing the HRP and uses same process processing procedure to the polysilicon described in board online production during HRP offline
Layer carries out ion implanting.
Preferably, the method monitored on-line to the polysilicon layer is：To being deposited described in board online production during HRP
Polysilicon layer be monitored and measure, to obtain online monitoring data.
Preferably, the method monitored on-line to the polysilicon layer is：One blank wafer is provided；When board is temporary offline
When stopping producing the HRP, the depositing polysilicon layer on the blank wafer, to the polysilicon layer carry out ion implanting, to from
Polysilicon layer after son injection is monitored and measured, to obtain off-line monitoring data；Wherein, deposited on the blank wafer
The polysilicon layer and when carrying out ion implanting to the polysilicon layer, using with identical during HRP described in board online production
Manufacturing process.
Preferably, in the step S3, the method for regulating and controlling the light transmittance for the masking layer being covered on the HRP is：Statistics
The light transmittance of the existing resistances of the HRP and the corresponding masking layer, forms light transmittance-resistance associated diagram, counts simultaneously
The gas flow of the light transmittance of the masking layer and the corresponding generation masking layer, forms light transmittance-gas flow and closes
Join table；The difference according to existing for the HRP resistance values estimated and the desired value, obtain the HRP resistance values estimated with
The difference of the desired value corresponding light transmittance in the light transmittance-resistance associated diagram；According to the HRP resistance values estimated
The transmissivity difference of the existing masking layer between the desired value, with reference to the light transmittance-gas flow contingency table, lead to
Overregulate and generate the gas flow of the masking layer to regulate and control the light transmittance of the masking layer, to change the densification of the masking layer
Degree, makes the HRP resistance values reach the desired value.
Preferably, the masking layer is generated using CVD or PVD, the gas for generating the masking layer comprises at least
SiH4, the light transmittance of the masking layer is suitable for by adjusting SiH4Flow regulated and controled.
Preferably, the masking layer is self-aligned metal silicate layer or silicon rich oxide layer.
Preferably, the HRP comprises at least soi structure, and the soi structure includes：Substrate, the silicon on the substrate
Localized oxide or shallow groove isolation layer, on the local oxidation of silicon layer or shallow groove isolation layer ion note
Polysilicon layer after entering.
As described above, the method for the regulation HRP resistance values of the present invention, has the advantages that：
1st, by on-line monitoring polysilicon layer CD data and off-line monitoring polysilicon layer resistance data collection,
Estimate out HRP resistance value, rather than current just see HRP resistance value knots when can only arrive the final electrical testing of semiconductor chip
Fruit, during so as to have deviation in the HRP resistance values and desired value estimated, during the online production of semiconductor chip in time
HRP resistance values are adjusted, so as to improve the stability of semiconductor chip.
2nd, the performance of masking layer on HRP is covered in by regulation and control come timely on-line fine HRP resistance values, is fully considered more
The critical size of crystal silicon layer and the expection of ion implanting, using the control of gas flow during online generation masking layer, to regulate and control
The correlative factor of the light transmittance of masking layer this influence HRP resistance values, so as to finely tune HRP resistance values, so that HRP resistance values reach
Desired value.
Brief description of the drawings
Fig. 1 is shown as the method flow schematic diagram of the regulation HRP resistance values of the embodiment of the present invention.
Fig. 2 is shown as HRP diagrammatic cross-sections in the method for the regulation HRP resistance values of the embodiment of the present invention.
Fig. 3 is shown as covering the part work of masking layer on HRP in the method for the regulation HRP resistance values of the embodiment of the present invention
Skill schematic flow sheet.
Fig. 4 is shown as in the method for the regulation HRP resistance values of the embodiment of the present invention online polysilicon layer critical size-resistance
The schematic diagram of associated diagram.
Fig. 5 is shown as in the method for the regulation HRP resistance values of the embodiment of the present invention offline polysilicon layer resistance-resistance association
The schematic diagram of figure.
Fig. 6 is shown as light transmittance-resistance associated diagram and printing opacity in the method for the regulation HRP resistance values of the embodiment of the present invention
The schematic diagram of rate-gas flow contingency table.
Fig. 7 is shown with the contrast schematic diagram of the front and rear HRP resistance values of regulation and control of the embodiment of the present invention.
Component label instructions
S1~S3 steps
1 substrate
2 local oxidation of silicon layers or shallow groove isolation layer
Polysilicon layer after 3 ion implantings
4 masking layers
Embodiment
Illustrate embodiments of the present invention below by way of specific instantiation, those skilled in the art can be by this specification
Disclosed content understands other advantages and effect of the present invention easily.The present invention can also pass through specific realities different in addition
The mode of applying is embodied or practiced, the various details in this specification can also be based on different viewpoints with application, without departing from
Various modifications or alterations are carried out under the spirit of the present invention.
Referring to Fig. 1, the present embodiments relate to a kind of method of regulation HRP resistance values.It should be noted that this implementation
Diagram provided in example only illustrates the basic conception of the present invention in a schematic way, and only display is relevant with the present invention in schema then
Component rather than drawn according to component count, shape and the size during actual implement, the kenel of each component, number during its actual implementation
Amount and ratio can be a kind of random change, and its assembly layout kenel may also be increasingly complex.
The method of the regulation HRP resistance values of the present embodiment, HRP comprise at least polysilicon layer；The present embodiment comprises at least such as
Lower step：
Step S1, is monitored to polysilicon layer, collects Monitoring Data；
Step S2, according to Monitoring Data, estimate HRP resistance value；
Step S3, when the HRP resistance values estimated have differences with desired value, in the online production process of semiconductor chip
In, form masking layer on the polysilicon layer, and according to the HRP resistance values estimated, regulate and control the translucency of masking layer, so that HRP
Resistance value reaches desired value.
Wherein, for HRP, as shown in Fig. 2 comprising at least soi structure, the soi structure includes：Substrate 1, positioned at substrate 1
On local oxidation of silicon layer or shallow groove isolation layer 2, on local oxidation of silicon layer or shallow groove isolation layer 2 from
Polysilicon layer 3 after son injection.The generally use monocrystalline silicon of substrate 1 or monocrystalline substrate.In common technique, HRP's is more
Wherein one layer of polysilicon layer of the grid or PIP of crystal silicon layer and MOS device generates simultaneously.Refer to technique stream as shown in Figure 3
Journey (is omitted in figure and provides substrate 1, makes local oxidation of silicon layer or shallow groove isolation layer 2, the part in silicon on substrate 1
The step such as depositing polysilicon layer in oxide layer or shallow groove isolation layer 2), its technique includes：According to the needs of semiconductor chip
Polysilicon layer is performed etching, ion implanting (IMP, Ion Implant) then is carried out to the polysilicon layer after etching, then existed
Masking layer is deposited on polysilicon layer 3 after ion implanting, wherein, masking layer can pass through light as mask in subsequent technique
Carve, used after etching.And in the present embodiment, the process monitored on-line to polysilicon layer is since etches polycrystalline silicon layer
, and it is continued until that masking layer deposit is completed；And the process that off-line monitoring is carried out to polysilicon layer is then temporary offline in board
When stopping producing HRP (or idle, neutral gear), since ion implanted polysilicon layer, continue to that masking layer deposit is completed.
For the present embodiment, when estimating out HRP resistance value, in order to obtain the HRP resistance values more accurately estimated, need
On-line monitoring polysilicon layer CD data and off-line monitoring polysilicon layer resistance data are considered simultaneously.Specifically, exist
In step S1, online and offline monitoring is carried out to polysilicon layer, collects online monitoring data and off-line monitoring data；Wherein, exist
Line Monitoring Data comprises at least on-line monitoring polysilicon layer CD data, and it is more that off-line monitoring data comprise at least off-line monitoring
Crystal silicon layer resistance data；In step s 2, the method for estimating HRP resistance value is：Count resistance relation factor-resistance association
Figure, wherein, resistance relation factor comprises at least online polysilicon layer critical size and offline polysilicon layer resistance, resistance associate because
Element-resistance associated diagram comprises at least online polysilicon layer critical size-resistance associated diagram and offline polysilicon layer resistance-resistance is closed
Connection figure；According to online monitoring data and the corresponding relation of online polysilicon layer critical size-resistance associated diagram, HRP resistance is obtained
First valuation of value, according to off-line monitoring data and the corresponding relation of offline polysilicon layer resistance-resistance associated diagram, obtains HRP
Second valuation of resistance value, the average value of the first valuation and the second valuation of HRP resistance values is taken as the HRP resistance values estimated.
For further embodiment, when estimating out HRP resistance value, if to the accuracy for the HRP resistance values estimated
It is required that it is relatively low, then only need to consider on-line monitoring polysilicon layer CD data or off-line monitoring polysilicon layer resistance data
.If only considering on-line monitoring polysilicon layer CD data, in step sl, polysilicon layer is monitored on-line,
Collect online monitoring data；Wherein, online monitoring data comprises at least on-line monitoring polysilicon layer CD data；In step
In S2, the method for estimating HRP resistance value is：Resistance relation factor-resistance associated diagram is counted, wherein, resistance relation factor is extremely
Include online polysilicon layer critical size less, resistance relation factor-resistance associated diagram comprises at least online polysilicon layer key chi
Very little-resistance associated diagram；According to online monitoring data and the corresponding relation of online polysilicon layer critical size-resistance associated diagram, obtain
To the HRP resistance values estimated.If only considering off-line monitoring polysilicon layer resistance data, in step sl, polysilicon layer is carried out
Off-line monitoring, collect off-line monitoring data；Wherein, off-line monitoring data comprise at least off-line monitoring polysilicon layer resistance data；
In step s 2, the method for estimating HRP resistance value is：Resistance relation factor-resistance associated diagram is counted, wherein, resistance association
Factor comprises at least offline polysilicon layer resistance, resistance relation factor-resistance associated diagram comprise at least offline polysilicon layer resistance-
Resistance associated diagram；According to off-line monitoring data and the corresponding relation of offline polysilicon layer resistance-resistance associated diagram, estimated
HRP resistance values.
In the present embodiment and further embodiment, the method for statistics resistance relation factor-resistance associated diagram is：Test
Multiple semiconductor chips produced in the past using same process processing procedure, obtain the existing resistances of multiple HRP；Each HRP is counted to have
Resistance and corresponding resistance relation factor, resistance relation factor-resistance associated diagram is formed in the form of coordinate diagram.For example,
Count the existing resistance RS and corresponding online polysilicon layer critical size CD of HRP, formed online polysilicon layer critical size-
Resistance associated diagram, as shown in Figure 4；The existing resistance RS and corresponding offline polysilicon layer resistance RS_Offline of HRP are counted,
Offline polysilicon layer resistance-resistance associated diagram is formed, as shown in Figure 5.
Due to needing to pass through measurement in the usual technique of semiconductor chip, when each HRP polysilicon layer generates online
Equipment is measured to its critical size, and retained data, and final electrical testing is then carried out after the completion of semiconductor chip, is obtained
To the existing resistance RS data of HRP；Therefore for the semiconductor chip largely produced in the past, except test has obtained substantial amounts of HRP
There are resistance RS data, a large amount of online polysilicon layer critical size CD data corresponding with the existing resistance RS of these HRP also be present, will
Both data are associated by way of coordinate diagram, form online polysilicon layer critical size-resistance associated diagram, so that
Relevance between them emerges from.
Further, since ion implantation concentration is an important factor for influenceing HRP resistance values, different ion implantation concentrations obtains
HRP resistance values it is different, test the existing resistances of multiple HRP that the semiconductor chip produced in the past obtains, wherein, HRP polycrystalline
The ion implantation concentration of silicon layer can have many kinds.Now we using it is a kind of it is offline by the way of measure offline polysilicon layer resistance
(this mode is identical with the method for carrying out off-line monitoring in step S1 to polysilicon layer, and the method for off-line monitoring will be entered afterwards
Row is introduced)：Multiple blank wafers are taken, when board is offline, depositing polysilicon layer (certainly, forms sediment here on each blank wafer
The processing procedure of product polysilicon layer is identical with the HRP of existing resistance processing procedure), the polysilicon layer on each blank wafer is carried out different
The ion implanting of concentration, the resistance of the polysilicon layer after ion implanting is measured, so as to obtain multiple offline polysilicon layer resistance RS_
Offline data.Each semiconductor chip produced in the past, its HRP polysilicon layer are corresponding one in ion implantation process
Ion implantation concentration, but caused minor variations in each front procedure step during due to board online production HRP are dense using this
The ion implantation process of degree is likely to be obtained multiple offline polysilicon layer resistance RS_Offline data；Therefore for multiple in the past raw
The semiconductor chip of production, except test obtains the existing resistance RS data of multiple HRP, also exist with the existing resistance RS's of these HRP
Both data are passed through coordinate diagram by more offline polysilicon layer resistance RS_Offline data corresponding to ion implantation concentration
Mode associate, offline polysilicon layer resistance-resistance associated diagram is formed, so that the relevance between them is able to body
It is existing.
Certainly, ion implanting type is also an important factor for influenceing HRP resistance values, as the other embodiments of the present invention,
Type (such as B, P plasma) can also be injected according to different ions and forms different offline polysilicon layer resistances-resistance association
Figure, its method is similar to the present embodiment, will not be described here.
The method that the present embodiment is monitored on-line to polysilicon layer is：To the polycrystalline deposited during board online production HRP
Silicon layer is monitored and measured, to obtain online monitoring data；To polysilicon layer carry out off-line monitoring method be：There is provided
Bai Jingyuan；When board suspends production HRP offline, the depositing polysilicon layer on blank wafer, ion note is carried out to polysilicon layer
Enter, the polysilicon layer after ion implanting is monitored and measured, to obtain off-line monitoring data；Wherein, polysilicon layer is entered
Same process processing procedure depositing polysilicon layer is used during the online and offline monitoring of row；Exist when board suspends production HRP offline with board
Ion implanting is carried out to polysilicon layer using same process processing procedure when line produces HRP.
For further embodiment, if only considering on-line monitoring polysilicon layer CD data, polysilicon layer is carried out
The method of on-line monitoring is：The polysilicon layer deposited during board online production HRP is monitored and measured, to obtain online prison
Survey data.If only considering off-line monitoring polysilicon layer resistance data, the method monitored on-line to polysilicon layer is：There is provided one
Blank wafer；When board suspends production HRP offline, the depositing polysilicon layer on blank wafer, ion is carried out to polysilicon layer
Injection, is monitored and measures to the polysilicon layer after ion implanting, to obtain off-line monitoring data；Wherein, in blank wafer
Upper depositing polysilicon layer and to polysilicon layer carry out ion implanting when, using with identical technique system during board online production HRP
Journey.
In the present embodiment, it is respectively that online monitoring data, off-line monitoring data are corresponding online more after obtaining Monitoring Data
Crystal silicon layer critical size-resistance associated diagram, offline polysilicon layer resistance-resistance associated diagram, then respectively obtain HRP resistance values
First valuation RS1 and the second valuation RS2, the first valuation RS1 and the second valuation RS2 is exactly the possible range value of HRP resistance values, is taken
First valuation RS1 and the second valuation RS2 medians have considered the two of influence HRP resistance values as the HRP resistance values estimated
Individual factor：Online polysilicon layer critical size and offline polysilicon layer resistance so that the HRP resistance values estimated are more accurate.
In the present embodiment step S3, the method for regulating and controlling the light transmittance for the masking layer being covered on HRP is：Count HRP
There is the light transmittance of resistance and corresponding masking layer, form light transmittance-resistance associated diagram, while the light transmittance of statistical masking layer
With the gas flow of corresponding generation masking layer, light transmittance-gas flow contingency table is formed, as shown in Figure 6；According to estimating
HRP resistance values and desired value existing for difference, the HRP resistance values estimated are with desired value in light transmittance-resistance associated diagram
In corresponding light transmittance difference；According to the transmissivity difference of existing masking layer between the HRP resistance values and desired value estimated,
With reference to light transmittance-gas flow contingency table, the light transmittance of masking layer is adjusted by adjusting the gas flow of generation masking layer, with
Change the consistency of masking layer, HRP resistance values is reached desired value.
Wherein, masking layer is generated using CVD or PVD, the gas for generating masking layer comprises at least SiH4, masking layer
Light transmittance be suitable to by adjusting SiH4Flow regulated and controled.Masking layer is that self-aligned metal silicate layer or Silicon-rich aoxidize
Nitride layer.
Light transmittance is one kind of the film of masking layer, in the other embodiments of the present invention, except regulation and control are covered on HRP
Masking layer light transmittance, other films that can influence HRP resistance values of the masking layer being covered on HRP can also be regulated and controled,
Such as stress etc., and the present embodiment is to be directed to light transmittance.
Final electrical testing is carried out after the completion of semiconductor chip, except obtaining the existing resistance RS data of HRP, is also covered
The light transmittance RI for the masking layer being placed on HRP；Therefore for multiple semiconductor chips produced in the past, except test obtain it is multiple
The existing resistance RS data of HRP, the transmittance data of multiple masking layers corresponding with the existing resistance RS of these HRP also be present, will
Both data are associated by way of coordinate diagram, light transmittance-resistance associated diagram are formed, so that the association between them
Property emerges from.
The HRP resistance values and desired value estimated are corresponded to the vertical seat of the existing resistances of HRP in light transmittance-resistance associated diagram respectively
Mark, when the HRP resistance values estimated have differences with desired value, it can respectively obtain first corresponding to the HRP resistance values estimated
Second light transmittance RI2 corresponding to light transmittance RI1 and desired value, the first light transmittance RI1 corresponding to the HRP resistance values estimated obviously with
Difference between them is only eliminated, can just made there is difference by the second light transmittance RI2 corresponding to desired value by regulating and controlling
HRP resistance values reach desired value.
Please continue to refer to the light transmittance shown in Fig. 6-resistance associated diagram, the chart is bright, and the light transmittance of masking layer is to influence HRP
An important factor for resistance value.Specifically, because HRP resistivity is one of decision condition of HRP resistance values, it is covered
Masking layer thereon influences, and when the consistency of masking layer is relatively low, the tightness degree of the atomic arrangement in masking layer is relatively low, covers
Cover that the light transmittance of layer is higher, HRP resistivity is relatively low, so that HRP resistance values are relatively low, vice versa.Therefore, in semiconductor
During the online production of chip, the light transmittance of masking layer reflects the consistency of masking layer；And the consistency of masking layer be by
To the gas flow control for generating masking layer, gas flow is bigger, and the tightness degree of the atomic arrangement in masking layer is higher, covers
Cover that the consistency of layer is higher, and vice versa.By taking Fig. 6 as an example, gas flows of the light transmittance RI at 1.50 is 80sccm, thereafter,
Light transmittance RI often increases by 0.01, and gas flow incrementss N is 10sccm.
We can also be drawn by experimental data：The light transmittance of masking layer is and the gas flow size that generates masking layer
And the uniformity of masking layer is associated, to generate a kind of gas silane SiH of masking layer4Exemplified by, drawn by experiment
SiH4, relation between light transmittance RI and uniformity U three, it is as shown in table 1 below：
Table 1
Because the precision of the uniformity of masking layer is high, the implementation of the present embodiment is had no effect on, therefore the present embodiment is refused
Consider.The present embodiment during the online production of semiconductor chip, need to only generate the gas stream of masking layer by on-line fine
Amount can just regulate and control the light transmittance of masking layer, make the first light transmittance RI1 corresponding to the HRP resistance values estimated corresponding with desired value
Difference between second light transmittance RI2 eliminates, so as to change the consistency of masking layer so that HRP resistance values can obtain in time
Adjustment, reaches desired value.
Fig. 7 is shown with the front and rear HRP resistance value contrast schematic diagrams of the present embodiment regulation and control, and abscissa is testDate,
Ordinate is actually measured HRP resistance value R, the method that leading portion does not use the present embodiment in figure, tests obtained HRP resistance values
Fluctuation is obvious, and big rise and fall, HRP resistance values are unstable, and after using the method for the present embodiment to be controlled by, figure posterior segment
The fluctuation convergence of HRP resistance values, HRP resistance value stabilitys significantly improve, and the stability of semiconductor chip is also improved.
To sum up, the method for regulation HRP resistance values of the invention, by on-line monitoring polysilicon layer CD data and
The collection of off-line monitoring polysilicon layer resistance data, estimates out HRP resistance value, rather than current can only arrive semiconductor chip most
HRP resistance value results are just seen during whole electrical testing, during so as to have deviation in the HRP resistance values and desired value estimated,
HRP resistance values are adjusted during the online production of semiconductor chip in time, so as to improve the stability of semiconductor chip.Also,
The present invention is covered in the performance of masking layer on HRP come timely on-line fine HRP resistance values by regulation and control, fully considers polysilicon
The critical size of layer and the expection of ion implanting, using the control of gas flow during online generation masking layer, to regulate and control masking
The correlative factor of light transmittance this influence HRP resistance values of layer, so as to finely tune HRP resistance values, so that HRP resistance values reach target
Value.So the present invention effectively overcomes various shortcoming of the prior art and has high industrial utilization.
The above-described embodiments merely illustrate the principles and effects of the present invention, not for the limitation present invention.It is any ripe
Know the personage of this technology all can carry out modifications and changes under the spirit and scope without prejudice to the present invention to above-described embodiment.Cause
This, those of ordinary skill in the art is complete without departing from disclosed spirit and institute under technological thought such as
Into all equivalent modifications or change, should by the present invention claim be covered.
Claims (12)
1. a kind of method for adjusting high value polyresistor resistance value, the high value polyresistor comprise at least more
Crystal silicon layer, it is characterised in that the method for the regulation high value polyresistor resistance value comprises at least following steps：
Step S1, the polysilicon layer is monitored, collects Monitoring Data；
Step S2, according to the Monitoring Data, estimate the resistance value of high value polyresistor；
Step S3, when resistance value and the desired value of the high value polyresistor estimated have differences, in semiconductor core
During the online production of piece, masking layer is formed on the polysilicon layer, and according to the high resistant value polysilicon electricity estimated
Device resistance value is hindered, regulates and controls the translucency of the masking layer, so that the resistance value of the high value polyresistor reaches target
Value.
2. the method for regulation high value polyresistor resistance value according to claim 1, it is characterised in that step S1
In, online and offline monitoring is carried out to the polysilicon layer, collects online monitoring data and off-line monitoring data；Wherein, it is described
Online monitoring data comprises at least on-line monitoring polysilicon layer CD data, and the off-line monitoring data comprise at least offline
Monitor polysilicon layer resistance data；
In the step S2, the method for estimating the resistance value of the high value polyresistor is：Statistics resistance relation factor-
Resistance associated diagram, wherein, the resistance relation factor comprises at least online polysilicon layer critical size and offline polysilicon layer hinders
Value, the resistance relation factor-resistance associated diagram comprise at least online polysilicon layer critical size-resistance associated diagram and offline more
Crystal silicon layer resistance-resistance associated diagram；Associated according to the online monitoring data with the online polysilicon layer critical size-resistance
The corresponding relation of figure, the first valuation of the high value polyresistor resistance value is obtained, according to the off-line monitoring data
With the corresponding relation of the offline polysilicon layer resistance-resistance associated diagram, the high value polyresistor resistance value is obtained
The second valuation, take the high value polyresistor resistance value the first valuation and the second valuation average value be used as described in
The high value polyresistor resistance value estimated.
3. the method for regulation high value polyresistor resistance value according to claim 1, it is characterised in that step S1
In, the polysilicon layer is monitored on-line, collects online monitoring data；Wherein, the online monitoring data comprises at least
Monitor polysilicon layer CD data on-line；
In the step S2, the method for estimating the resistance value of the high value polyresistor is：Statistics resistance relation factor-
Resistance associated diagram, wherein, the resistance relation factor comprises at least online polysilicon layer critical size, the resistance association because
Element-resistance associated diagram comprises at least online polysilicon layer critical size-resistance associated diagram；According to the online monitoring data and institute
The corresponding relation of online polysilicon layer critical size-resistance associated diagram is stated, obtains the high value polyresistor estimated
Resistance value.
4. the method for regulation high value polyresistor resistance value according to claim 1, it is characterised in that step S1
In, off-line monitoring is carried out to the polysilicon layer, collects off-line monitoring data；Wherein, the off-line monitoring data comprise at least
Off-line monitoring polysilicon layer resistance data；
In the step S2, the method for estimating the resistance value of the high value polyresistor is：Statistics resistance relation factor-
Resistance associated diagram, wherein, the resistance relation factor comprises at least offline polysilicon layer resistance, the resistance relation factor-resistance
Value associated diagram comprises at least offline polysilicon layer resistance-resistance associated diagram；According to off-line monitoring data and described offline more
The corresponding relation of crystal silicon layer resistance-resistance associated diagram, obtain the high value polyresistor resistance value estimated.
5. the method for the regulation high value polyresistor resistance value according to claim any one of 2-4, its feature exist
In the method for statistics resistance relation factor-resistance associated diagram is：Test multiple partly leading using the production of same process processing procedure in the past
Body chip, obtain the existing resistance of multiple high value polyresistors；The each high value polyresistor of statistics has
Resistance and corresponding resistance relation factor, resistance relation factor-resistance associated diagram is formed in the form of coordinate diagram.
6. the method for regulation high value polyresistor resistance value according to claim 2, it is characterised in that to described
The method that polysilicon layer is monitored on-line is：To the polycrystalline deposited described in board online production during high value polyresistor
Silicon layer is monitored and measured, to obtain online monitoring data；
To the polysilicon layer carry out off-line monitoring method be：One blank wafer is provided；When board suspends described in production offline
During high value polyresistor, the depositing polysilicon layer on the blank wafer, ion implanting is carried out to the polysilicon layer,
Polysilicon layer after ion implanting is monitored and measured, to obtain off-line monitoring data；
Wherein, same process processing procedure depositing polysilicon layer is used when carrying out online and offline monitoring to the polysilicon layer；Board
Adopted when offline pause produces the high value polyresistor and described in board online production during high value polyresistor
Ion implanting is carried out to the polysilicon layer with same process processing procedure.
7. the method for regulation high value polyresistor resistance value according to claim 3, it is characterised in that to described
The method that polysilicon layer is monitored on-line is：To the polycrystalline deposited described in board online production during high value polyresistor
Silicon layer is monitored and measured, to obtain online monitoring data.
8. the method for regulation high value polyresistor resistance value according to claim 4, it is characterised in that to described
The method that polysilicon layer is monitored on-line is：One blank wafer is provided；When board suspends the production high value polycrystalline offline
During silicon resistor, the depositing polysilicon layer on the blank wafer, ion implanting is carried out to the polysilicon layer, to ion implanting
Polysilicon layer afterwards is monitored and measured, to obtain off-line monitoring data；Wherein, deposited on the blank wafer described more
Crystal silicon layer and to the polysilicon layer carry out ion implanting when, using with high value polyresistor described in board online production
When identical manufacturing process.
9. the method for the regulation high value polyresistor resistance value according to claim any one of 1-4, its feature exist
In in the step S3, the method for regulating and controlling the light transmittance for the masking layer being covered on the high value polyresistor is：System
The light transmittance of the existing resistance of the high value polyresistor and the corresponding masking layer is counted, forms light transmittance-resistance
It is worth associated diagram, while counts the light transmittance of the masking layer and the gas flow of the corresponding generation masking layer, is formed
Light transmittance-gas flow contingency table；Existed according to the high value polyresistor resistance value estimated and the desired value
Difference, obtain the high value polyresistor resistance value estimated and closed with the desired value in the light transmittance-resistance
Join the difference of corresponding light transmittance in figure；According to the high value polyresistor resistance value estimated and the desired value it
Between the existing masking layer transmissivity difference, with reference to the light transmittance-gas flow contingency table, by adjusting described in generation
The gas flow of masking layer regulates and controls the light transmittance of the masking layer, to change the consistency of the masking layer, makes the high resistant
Value polysilicon resistance value reaches the desired value.
10. the method for regulation high value polyresistor resistance value according to claim 9, it is characterised in that use
CVD or PVD generate the masking layer, and the gas for generating the masking layer comprises at least SiH4, the masking layer it is saturating
Light rate is suitable to by adjusting SiH4Flow regulated and controled.
11. the method for the regulation high value polyresistor resistance value according to claim any one of 1-4, its feature exist
In the masking layer is self-aligned metal silicate layer or silicon rich oxide layer.
12. the method for the regulation high value polyresistor resistance value according to claim any one of 1-4, its feature exist
In the high value polyresistor comprises at least soi structure, and the soi structure includes：Substrate, on the substrate
Local oxidation of silicon layer or shallow groove isolation layer, on the local oxidation of silicon layer or shallow groove isolation layer from
Polysilicon layer after son injection.
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| US5065221A (en) * | 1988-09-30 | 1991-11-12 | Kabushiki Kaisha Toshiba | Trimming resistor element for microelectronic circuit |
| CN102110593A (en) * | 2010-12-15 | 2011-06-29 | 无锡中微晶园电子有限公司 | Method for improving stability of polysilicon thin-film resistor |
| CN103346142A (en) * | 2013-06-04 | 2013-10-09 | 上海华力微电子有限公司 | Test key structure and method for monitoring etching capacity of contact holes in etching process |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US5065221A (en) * | 1988-09-30 | 1991-11-12 | Kabushiki Kaisha Toshiba | Trimming resistor element for microelectronic circuit |
| CN102110593A (en) * | 2010-12-15 | 2011-06-29 | 无锡中微晶园电子有限公司 | Method for improving stability of polysilicon thin-film resistor |
| CN103346142A (en) * | 2013-06-04 | 2013-10-09 | 上海华力微电子有限公司 | Test key structure and method for monitoring etching capacity of contact holes in etching process |
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