WO2023155203A1

WO2023155203A1 - Method for simulating circuit, electronic device, computer-readable storage medium, and program product

Info

Publication number: WO2023155203A1
Application number: PCT/CN2022/077139
Authority: WO
Inventors: 孙立杰; 黄威森; 余华涛
Original assignee: 华为技术有限公司
Priority date: 2022-02-21
Filing date: 2022-02-21
Publication date: 2023-08-24
Also published as: CN116940929A

Abstract

The present disclosure relates to a method for simulating a circuit. The method comprises: receiving a local extraction indication which is used for determining a local mismatch of adjacent interconnection lines in a circuit layout; generating target netlist data in response to having received the local extraction indication and on the basis of an interconnection line model library, an interconnection line mismatch model set and the circuit layout; and simulating the target netlist data, so as to generate a local simulation result for the adjacent interconnection lines. By using the interconnection line model library, the interconnection line mismatch model set and the circuit layout when the local extraction indication has been received, a parasitic capacitance representation of adjacent interconnection lines and a resistance representation of the adjacent interconnection lines in a corresponding interconnection line mismatch model in the interconnection line mismatch model set can be extracted. In addition, since the parasitic capacitance representation and the parasitic resistance representation each include a Monte Carlo factor, the situation of a local fluctuation can be represented in the parasitic capacitance representation and the parasitic resistance representation.

Description

Method, electronic device, computer-readable storage medium and program product for simulating a circuit

technical field

The present disclosure relates to the field of hardware design, and more particularly to a method for simulating a circuit, an electronic device, a computer-readable storage medium and a program product.

Background technique

In the process of designing and manufacturing integrated circuit chips, it usually includes stages such as specification formulation, integrated circuit design, chip manufacturing, packaging and testing, among which integrated circuit design includes stages such as circuit design, layout design and mask making. Before the designed circuit is used for manufacturing, it is usually necessary to simulate the designed circuit to ensure the correctness of the circuit design and reduce performance degradation caused by process fluctuations in the manufacturing process.

For example, although adjacent interconnect lines are given the same line width and line spacing during the design process, they are modified by optical proximity correction (OPC), photolithography, etching, chemical mechanical polishing, (chemical mechanical The impact of polishing, CMP and other processes will cause shape mismatches such as low error region (LER) and erosion (erosion) in adjacent interconnect lines, and then produce mismatch effects of parasitic capacitance and resistance, which is also Called the local fluctuation effect (local variation).

The symmetry requirements of analog circuit design such as current mirror pair layout are extremely strict, not only the local fluctuation of the device needs to be evaluated, but also the mismatch of adjacent interconnect lines needs to be evaluated. Local fluctuations at the device level can be simulated by a simulation program with integrated circuit emphasis (SPICE) simulator using a mismatch model for Monte Carlo simulation, but local fluctuations in the electrical characteristics of interconnect lines are usually difficult to obtain. This is because the electrical characteristics of the interconnection line are usually obtained by parasitic extraction of the layout with a layout parasitic extraction (LPE) tool. The layout parasitic parameters not only have many components, but also have complex distributions, so conventional solutions usually face huge problems. Simulation calculations. In a conventional solution, usually only the electrical characteristics of the interconnection lines under several fixed process angles are extracted. The fixed process angle usually represents the limit of the process, which may excessively amplify the influence of the local fluctuations of the interconnection lines, thus resulting in over-design.

Contents of the invention

In view of the above-mentioned problems, the embodiments of the present disclosure aim to provide a method for simulating a circuit, an electronic device, a computer-readable storage medium, and a program product, which can be used to avoid over-designing a circuit for a process corner situation and can reflect interconnection Local fluctuations of the parasitic parameters in the line.

According to a first aspect of the present disclosure, a method for simulating a circuit is provided. The method includes receiving local extraction indications for determining local mismatches of adjacent interconnect lines in a circuit layout. The method also includes generating target netlist data including a plurality of extracted parasitic parameter representations based on the interconnect model library, the interconnect mismatch model set, and the circuit layout in response to receiving the partial extraction indication , the interconnect model library includes multiple representations of the 3D structure of multiple interconnects, the interconnect mismatch model set includes representations of parasitic capacitance between adjacent interconnects and resistance representations of adjacent interconnects, parasitic At least one of the capacitive representation and the resistive representation is associated with a Monte Carlo factor. The method further includes: simulating the target netlist data to generate local simulation results for adjacent interconnect lines. By using the interconnect model library, interconnect mismatch model set, and circuit layout with local extraction instructions received, it is possible to extract adjacent The parasitic capacitance of an interconnect line is represented and the resistance of an adjacent interconnect line is represented. In addition, since the representations of parasitic capacitance and resistance include Monte Carlo factors, the situation of local fluctuations can be represented in the representation of parasitic capacitance and resistance. Compared with the conventional scheme of calculating the electrical characteristics of the interconnection line under the limit process angle, the technical solution disclosed in the present disclosure can not only avoid the over-design caused by the limit process angle, but also reflect the local fluctuation of the interconnection line, thereby providing Moderately correct circuit design.

In a possible implementation manner of the first aspect, the method further includes: generating an interconnection mismatch model set based on process parameters for the circuit layout and an interconnection model library. By substituting the process parameters of the circuit layout into the corresponding interconnect model library, the user can flexibly configure the interconnect mismatch model set for different process parameters, thereby providing accurate information about the local fluctuations of the parasitic parameters of the interconnect simulation.

In a possible implementation manner of the first aspect, generating the target netlist data based on the interconnect model library, the interconnect mismatch model set, and the circuit layout includes: comparing the circuit layout with the interconnect model library to The generation includes matching the set of interconnect structures; and extracting the set of matching interconnect structures using the set of interconnect mismatch models to generate target netlist data. By comparing the circuit layout with the interconnection model library, it is possible to extract interconnection structures including adjacent interconnections that need to be paid attention to in the circuit layout, and reduce the calculation amount of interconnections that do not need to be paid attention to.

In a possible implementation manner of the first aspect, generating the interconnection mismatch model set based on the process parameters for the circuit layout and the interconnection model library includes: the field solver based on the process parameters for the interconnection model library The model in is parsed to generate a set of interconnect mismatch models.

In a possible implementation manner of the first aspect, the analysis of the model in the interconnection model library based on the process parameters by the field solver includes: the field solver uses a boundary source or random walk algorithm to analyze the model based on the process parameters Models in the Interconnect Model Library are resolved.

In a possible implementation manner of the first aspect, the method further includes: receiving a global extraction instruction for determining interconnection lines in the circuit layout; in response to receiving the global extraction instruction, based on the interconnection line model library, resistor Capacitor process file database and circuit layout, generate global netlist data, global netlist data includes electrical characteristics of interconnection lines under multiple process angles, interconnection line model library includes multi-dimensional structure of multiple interconnection lines representation; and simulate the global netlist data to generate global simulation results for interconnect lines under multiple process corners. By also setting the global extraction instruction, not only the simulation of the local fluctuation situation of the parasitic parameter of the interconnection line can be provided, but also the extraction of the electrical characteristics of the interconnection line under a conventional process angle can be provided. This can bring greater flexibility to users to meet different needs.

In a possible implementation manner of the first aspect, different types of parasitic capacitance representations in the parasitic capacitance representation and the resistance representation are assigned different Monte Carlo factors. In a possible implementation of the first aspect, the Monte Carlo factors include Gaussian factors. It is found through research that the use of Gaussian factors can basically cover the local fluctuations of the parasitic parameters of the interconnection lines, so that the local fluctuations of the parasitic parameters of the interconnection lines can be simulated in a simple manner.

According to a second aspect of the present disclosure, an electronic device is provided. The electronic device includes a receiving unit, a generating unit and a simulation unit. The receiving unit is configured to receive local extraction indications for determining local mismatches of adjacent interconnect lines in the circuit layout. The generation unit is configured to: generate target netlist data including a plurality of extracted parasitic parameters based on the interconnect model library, the interconnect mismatch model set, and the circuit layout in response to receiving the partial extraction instruction representation, the interconnect model library includes multiple representations of the 3D structure of multiple interconnects, the interconnect mismatch model set includes representations of parasitic capacitance between adjacent interconnects and resistance representations of adjacent interconnects, At least one of the parasitic capacitance representation and the resistance representation is associated with a Monte Carlo factor. The simulation unit is configured to: simulate the target netlist data to generate a local simulation result for adjacent interconnection lines. By using the interconnect model library, the interconnect mismatch model set, and the circuit layout with local extraction instructions received, it is possible to extract the relevant information in the interconnect mismatch model corresponding to the interconnect mismatch model set. The parasitic capacitance of adjacent interconnect lines is represented and the resistance of adjacent interconnect lines is represented. In addition, since the representations of parasitic capacitance and resistance contain Monte Carlo factors, local fluctuations can be represented in the representation of parasitic capacitance and resistance. Compared with the conventional scheme of calculating the electrical characteristics of the interconnection line under the limit process angle, the technical solution disclosed in the present disclosure can not only avoid the overdesign caused by the limit process angle, but also reflect the local fluctuation of the interconnection line, thereby Provides moderately correct circuit design.

In a possible implementation manner of the second aspect, the generating unit is further configured to: generate an interconnection mismatch model set based on process parameters for the circuit layout and an interconnection model library. By substituting the process parameters of the circuit layout into the corresponding interconnect model library, the user can flexibly configure the interconnect mismatch model set for different process parameters, thereby providing accurate information about the local fluctuations of the parasitic parameters of the interconnect simulation.

In a possible implementation manner of the second aspect, the generation unit is further configured to: compare the circuit layout with the interconnection model library to generate a structure set including matching interconnections; and use the interconnection mismatch model The set extracts the set of matching interconnect structures to generate the target netlist data. By comparing the circuit layout with the interconnection model library, it is possible to extract interconnection structures including adjacent interconnections that need to be paid attention to in the circuit layout, and reduce the calculation amount of interconnections that do not need to be paid attention to.

In a possible implementation manner of the second aspect, the generation unit is further configured to: use the field solver to analyze the models in the interconnection model library based on the process parameters to generate the interconnection mismatch model set.

In a possible implementation manner of the second aspect, the generation unit is further configured as: the field solver uses a boundary source or a random walk algorithm to analyze the models in the interconnect model library based on the process parameters.

In a possible implementation manner of the second aspect, the receiving unit is further configured to: receive a global extraction instruction for determining an interconnection line in the circuit layout; the generating unit is further configured to: respond to receiving the global extraction instruction , based on the interconnection model library, the resistor and capacitor process file database and the circuit layout, generate global netlist data. The global netlist data includes the electrical characteristics of the interconnection lines under multiple process angles. The interconnection model library includes multiple multiple representations of the three-dimensional structures of the interconnect lines; and the simulation unit is further configured to: simulate the global netlist data to generate global simulation results for the interconnect lines under the plurality of process corners. By also setting the global extraction instruction, not only the simulation of the local fluctuation situation of the parasitic parameter of the interconnection line can be provided, but also the extraction of the electrical characteristics of the interconnection line under a conventional process angle can be provided. This can bring greater flexibility to users to meet different needs.

In a possible implementation manner of the second aspect, different types of parasitic capacitance representations in the parasitic capacitance representation and the resistance representation are assigned different Monte Carlo factors. In a possible implementation manner of the second aspect, the Monte Carlo factors include Gaussian factors. It is found through research that the use of Gaussian factors can basically cover the local fluctuations of the parasitic parameters of the interconnection lines, so that the local fluctuations of the parasitic parameters of the interconnection lines can be simulated in a simple manner.

In a third aspect of the present disclosure, an electronic device is provided. The electronic device comprises: at least one processor; at least one memory, the at least one memory being coupled to the at least one processor and storing instructions for execution by the at least one processor, the instructions, when executed by the at least one processor, cause the device The method according to the first aspect is performed.

In a fourth aspect of the present disclosure, a computer readable storage medium is provided. A computer-readable storage medium stores a computer program which, when executed by a processor, implements the method according to the first aspect.

In a fifth aspect of the present disclosure, a computer program product is provided. The computer program product comprises computer-executable instructions which, when executed by a processor, cause a computer to implement the method according to the first aspect.

It should be understood that what is described in the Summary of the Invention is not intended to limit the key or important features of the embodiments of the present disclosure, nor is it intended to limit the scope of the present disclosure. Other features of the present disclosure will be readily understood through the following description.

Description of drawings

The above and other features, advantages and aspects of the various embodiments of the present disclosure will become more apparent with reference to the following detailed description when taken in conjunction with the accompanying drawings. In the drawings, identical or similar reference numerals denote identical or similar elements, wherein:

FIG. 1 shows a schematic perspective view of an interconnect structure of a conventional path;

Fig. 2 shows the flowchart of the design and manufacture process of integrated circuit;

FIG. 3 shows a schematic flowchart for simulating a circuit according to some embodiments of the present disclosure;

FIG. 4 shows a schematic diagram of a parasitic distribution of an interconnect model according to some embodiments of the present disclosure;

FIG. 5 shows a schematic diagram of parasitic distribution of another interconnect model according to other embodiments of the present disclosure;

FIG. 6 shows a schematic diagram of a labeled interconnect structure according to some embodiments of the present disclosure;

Figure 7 shows a schematic block diagram of an example device that may be used to implement embodiments of the present disclosure; and

FIG. 8 shows a schematic block diagram of an electronic device according to some embodiments of the present disclosure.

Detailed ways

Embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although certain embodiments of the present disclosure are shown in the drawings, it should be understood that the disclosure may be embodied in various forms and should not be construed as limited to the embodiments set forth herein; A more thorough and complete understanding of the present disclosure. It should be understood that the drawings and embodiments of the present disclosure are for exemplary purposes only, and are not intended to limit the protection scope of the present disclosure.

In the description of the embodiments of the present disclosure, the term "comprising" and its similar expressions should be interpreted as an open inclusion, that is, "including but not limited to". The term "based on" should be understood as "based at least in part on". The term "one embodiment" or "the embodiment" should be read as "at least one embodiment". The terms "first", "second", etc. may refer to different or the same object. The term "and/or" means at least one of the two items associated with it. For example "A and/or B" means A, B, or A and B. Other definitions, both express and implied, may also be included below.

It should be understood that for the technical solutions provided by the embodiments of the present application, in the introduction of the following specific embodiments, some repetitions may not be repeated, but it should be considered that these specific embodiments have been referred to each other and can be combined with each other.

As described above, local fluctuations in the electrical characteristics of interconnect lines are generally difficult to obtain. This is because the electrical characteristics of the interconnection line are usually obtained by parasitic extraction of the layout by the LPE tool. The parasitic parameters of the layout not only have many components, but also have complex distribution. Therefore, conventional solutions usually face a huge amount of simulation calculation. In a conventional solution, usually only the electrical characteristics of the interconnection lines under several fixed process angles are extracted. The fixed process angle usually represents the limit of the process, which may over-magnify the influence of local fluctuations in the interconnection lines, resulting in over-design.

In the present disclosure, by using an interconnect model library, an interconnect mismatch model set, and a circuit layout in situations where local extraction instructions are received, it is possible to extract the corresponding interconnect mismatch from the interconnect mismatch model set. Parasitic capacitive and resistive representations of adjacent interconnect structures in the model. In addition, since the representations of parasitic capacitance and resistance contain Monte Carlo factors, the situation of local fluctuations can be represented in the representation of parasitic capacitance and resistance. Through simulation, it is possible to obtain local fluctuations of parasitic parameters that may occur in subsequent processes, so that the local fluctuations can be pre-adjusted at the design stage. In this way, compared with the conventional solution of calculating the electrical characteristics of the interconnection line at the limit process angle, the technical solution disclosed in the present disclosure can not only avoid the overdesign caused by the limit process angle, but also reflect the local fluctuation of the interconnection line situation, thereby providing moderately correct circuit design.

FIG. 1 shows a schematic perspective view of an interconnect structure 100 of a conventional path. Interconnect structure 100 has an input inverter 102 and three fan-out

inverters

104 , 106 and 108 . The inverters are connected through interconnection lines. In this interconnection structure, considering only simplified backend of line (BEOL) parasitics, there are 12 independent parasitic resistances and 24 independent parasitic capacitances. If each is extracted by Monte Carlo, there will be at least 36 independent variables for random calculation. For post-layout simulation, such a huge simulation calculation cannot be realized at all. Therefore, generally only fixed process angle extraction is used to characterize the limit case of the process. Extraction under a fixed process angle will over-amplify the influence of local fluctuations, resulting in over-design.

FIG. 2 shows a flowchart of a design and manufacture process 200 for an integrated circuit. The design-to-manufacture process 200 begins with specification development 220 . In the stage of specification formulation 210, the functional and performance requirements that the integrated circuit needs to meet are determined. Then, in the stage of integrated circuit design 220 , circuit design 222 is first performed by means of electronic design automation (EDA) software. After the circuit is determined, the physical design 224 is performed to determine the layout and wiring of the circuit units in the integrated circuit, so as to obtain the circuit layout. After obtaining the circuit layout, mask fabrication 226 may be performed to obtain masks for forming the designed circuits on the wafer. Subsequently, in the stage of manufacturing 230, integrated circuits are formed on the wafer through processes such as photolithography, etching, ion implantation, thin film deposition, and polishing. In the stage of packaging 240 , the wafer is diced to obtain bare chips, and the bare chips are packaged through processes such as bonding, welding, and molding to obtain chips. The resulting chip is tested in a testing 250 stage to ensure that the performance of the finished chip meets the requirements established in specification 220 . Finally, the tested chip 260 can be delivered to the customer.

Layout design 224 mainly includes steps such as division, layout planning, layout, clock tree synthesis, and wiring, and involves evaluation indicators such as routability, delay, power consumption, area, and manufacturability. In the layout design 224, it is necessary to evaluate the local fluctuation of the parasitic parameters of the interconnection lines (especially adjacent interconnection lines).

FIG. 3 shows a schematic flowchart of a method 300 for simulating a circuit according to some embodiments of the present disclosure. At 302, an electronic device, such as a computer, receives an input from a user, ie, a local extraction indication for determining a local mismatch of adjacent interconnect lines in a circuit layout. In one embodiment, a computer program such as EDA software can provide a number of user options on the interface, such as global mode options and local extraction options. In case the user selects the local extraction for local mismatch option, the user actually inputs a local extraction instruction for determining the local mismatch of adjacent interconnect lines in the circuit layout to the electronic device. In another embodiment, the user may also cause the electronic device to execute the method 300 by inputting a command. This disclosure is not limited in this regard. It can be understood that the method 300 shown in FIG. 3 may be executed by an electronic device having a computing function, such as a personal computer, a workstation, a server, and the like. This disclosure is not limited in this regard.

At 304, the electronic device generates target netlist data based on the interconnect model library, the interconnect mismatch model set, and the circuit layout in response to receiving the partial extraction indication. In one embodiment, the library of interconnect models includes a plurality of representations of the three-dimensional structures of the plurality of interconnects. For example, the interconnect model library may include a pizza structure in which two layers of metal interconnects overlap or a sandwich structure in which three layers of metal interconnects overlap. EDA software can include multiple typical interconnect model structures. In addition, users can also customize the interconnection model structure according to their own circuit design requirements to form an interconnection model library, or supplement the default interconnection model library in EDA software.

In one embodiment, the electronic device can invoke the field solver of the EDA tool. The field solver is based on the boundary element or random walk (floating random walk) algorithm and relies on a large number of built-in interconnection model structures of EDA tools (such as the interconnection model structure from the interconnection model library), which will come from Each process parameter in the interconnection process file is substituted into the interconnection model structure for simulation to form an interconnection mismatch model set. The process parameters include, for example, the width and thickness of the conductors of the interconnection lines, and the thickness and dielectric constant of the dielectric layer between or near the interconnection lines. It will be appreciated that other interconnect model analysis tools and other algorithms may also be used. The interconnect mismatch model set includes a representation of parasitic capacitance between adjacent interconnects and a representation of resistance between adjacent interconnects. At least one of the parasitic capacitance representation and the resistance representation is associated with a Monte Carlo factor.

FIG. 4 shows a schematic diagram of a parasitic distribution of an interconnect model 400 according to some embodiments of the present disclosure. The interconnect model 400 is a conventional sandwich crossover structure in which both parasitic capacitance and resistance of adjacent interconnect lines are defined. The sandwich cross structure includes a first-layer metal interconnection MN ₊₁ 402, a plurality of second-layer metal interconnection MN 404-2, 404-4, 404-6 (hereinafter individually or collectively referred to as 404) and a second-layer metal interconnection _MN 404-2, 404-4, 404-6 The three-layer metal interconnection line M _N-1 406 , wherein M _N+1 402 and M _N-1 406 are perpendicular to the extending direction of M _N 404 . The thickness of the dielectric layer between MN _-1 406 and _MN 404 is denoted by IMDBt, and the thickness of the dielectric layer between MN ₊₁ 402 and _MN 404 is denoted by IMDTt. The width of the interconnection line is represented by Mw, and the thickness of the interconnection line is represented by Mt. The pitch between adjacent interconnect lines in the same layer is denoted by P-Mw. In this sandwich structure, there are two fringe parasitic capacitances denoted by Cft and vertical overlay capacitance denoted by Cat between the interconnection lines _MN 404 - 4 and MN ₊₁ 402 . There are two fringe parasitic capacitances denoted by Cfb and vertical overlay capacitance denoted by Cab between the interconnection line M _N 404-4 and M _N-1 406 . In addition, there is a same-layer parasitic coupling capacitance denoted by Cc between the interconnection _MN 404-2 and the interconnection _MN404-4 . Similarly, there is a same-layer parasitic coupling capacitance denoted by Cc between the interconnection _MN 404-6 and the interconnection _MN 404-4.

The parasitic capacitance and resistance of the sandwich cross structure in FIG. 4 can thus be represented by the following equations (1)-(7).

Cc＝f(Mw,P-Mw,Mt)*L (1)

Cab＝f(Mw,IMDBt)*L (2)

Cat＝f(Mw,IMDTt)*L (3)

Cfb＝f(Mt,P-Mw,IMDBt)*L (4)

Cft＝f(Mt,P-Mw,IMDTt)*L (5)

Ctotal＝2*Cc+Cab+Cat+2*Cfb+2*Cft (6)

R＝Rho*L/(Mw*Mt) (7)

Among them, f() represents the function, L represents the length of the interconnection line, Ctotal represents the total parasitic capacitance, and Rho represents the resistivity.

In order to reflect the local fluctuations caused by the process, in some embodiments of the present disclosure, Monte Carlo factors, such as Gaussian factors, are added to the formulas (1)-(7). Equations (1)-(7) can thus be rewritten as the following equations (1A)-(7A).

Cc＝f(Mw*a0,P-Mw*a0,Mt*a1)*L (1A)

Cab＝f(Mw*a0,IMDBt*a2)*L (2A)

Cat＝f(Mw*a0,IMDTt*a3)*L (3A)

Cfb＝f(Mt*a1,P-Mw*a0,IMDBt*a2)*L (4A)

Cft＝f(Mt*a1,P-Mw*a0,IMDTt*a3)*L (5A)

Ctotal＝2*Cc+Cab+Cat+2*Cfb+2*Cft (6A)

R＝Rho*a4*L/(Mw*a0*Mt*a1) (7A)

Among them, a0-a4 represent different Monte Carlo factors, such as Gaussian factors. It can be understood that since Mw and P-Mw represent the width of the interconnection line and the width of the pitch, the two can be considered as the same type of parameters and can be expressed using the same Gaussian factor a0. In other embodiments, Mw and P-Mw may be assigned different Monte Carlo factors. In addition, since the length L of the interconnection line is usually larger than the width and thickness, local fluctuations have limited influence on it, so the Monte Carlo factor may not be assigned to the length of the interconnection line. It can be understood that different types of parasitic capacitance representations among the parasitic capacitance representation and the resistance representation are assigned different Monte Carlo factors, such as combinations of different Monte Carlo factors. Specifically, different types of process parameters such as interconnect line width, thickness, thickness of dielectric layer, etc. in the representation of parasitic capacitance and resistance can be assigned different Monte Carlo factors. Where different materials are used to form the interconnection lines, the resistivities of the different materials may also be assigned different Monte Carlo factors.

FIG. 5 shows a schematic diagram of a parasitic distribution of an interconnect model 500 according to other embodiments of the present disclosure. The interconnection model 500 is a multi-layer vertical structure, which includes a first-level metal interconnection MN ₊₁ 502, a plurality of second-level metal interconnection _MN 504-2, 504-4, 504-6 (below individually or collectively referred to as 504), a plurality of third-level metal interconnections MN _-1 506-2, 506-4 (hereinafter individually or collectively referred to as 506), and fourth-level metal interconnections _MN-2 508 , wherein M _N+1 502 and M _N-2 508 are perpendicular to the extension directions of M _N 504 and M _N-1 506 . The thickness of the dielectric layer between MN _-1 506 and _MN 504 is denoted by IMDBt, the thickness of the dielectric layer between MN ₊₁ 502 and _MN 504 is denoted by IMDTt, and _MN-2 508 and _MN The thickness of the dielectric layer between _-1 506 is denoted by IMDTtx. The width of the interconnection line is represented by Mw, the thickness of the interconnection line in the _MN layer is represented by Mt, and the thickness of the interconnection line in the _MN-1 layer is represented by Mtx. The pitch between adjacent interconnect lines in M _N is denoted by P-Mw, and the pitch between adjacent interconnect lines in M _N-1 layer is denoted by Mwx. In the multilayer vertical structure, there are two fringe parasitic capacitances denoted by Cft and vertical overlay capacitance denoted by Cat between the interconnection lines _MN 504 - 4 and MN ₊₁ 502 . There are two fringe parasitic capacitances denoted by Cfb between the interconnect lines M _N 504-4 and M _N-1 506 . In addition, there are two fringe parasitic capacitances denoted by Cfbx and vertical overlay capacitance denoted by Cab between the interconnect lines _MN 504-4 and _MN-2 508 . There is a same-layer parasitic coupling capacitance denoted by Cc between the interconnection _MN 504-2 and the interconnection _MN504-4 . Similarly, there is a same-layer parasitic coupling capacitance denoted by Cc between the interconnection line _MN 504-6 and the interconnection line _MN504-4 .

The parasitic capacitance and resistance of the multilayer vertical structure in FIG. 5 can thus be represented by the following equations (8)-(15).

Cc＝f(Mw,P-Mw,Mt)*L (8)

Cab＝f(Mw,IMDBt+Mtx+IMDBtx)*L (9)

Cat＝f(Mw,IMDTt)*L (10)

Cfb＝f(Mt,P-Mw,IMDBt,Mwx)*L (11)

Cft＝f(Mt,P-Mw,IMDTt)*L (12)

Cfbx＝f(Mt,P-Mw,IMDBt+Mtx+IMDBtx) (13)

Ctotal＝2*Cc+Cab+Cat+2*Cfb+2*Cft+2*Cfbx (14)

R＝Rho*L/(Mw*Mt) (15)

Among them, L represents the length of the interconnection line, Ctotal represents the total parasitic capacitance, and Rho represents the resistivity.

In order to reflect the local fluctuations caused by the process, in some embodiments of the present disclosure, Monte Carlo factors, such as Gaussian factors, are added to the formulas (8)-(15). Equations (8)-(15) can thus be rewritten as the following equations (8A)-(15A).

Cc＝f(Mw*a0,P-Mw*a0,Mt*a1)*L (8A)

Cab＝f(Mw*a0,IMDBt*a2+Mtx*a3+IMDBtx*a4)*L (9A)

Cat＝f(Mw*a0,IMDTt*a5)*L (10A)

Cfb＝f(Mt*a1,P-Mw*a0,IMDBt*a2,Mwx*a6)*L (11A)

Cft＝f(Mt*a1,P-Mw*a0,IMDTt*a3)*L (12A)

Cfbx＝f(Mt*a1,P-Mw*a0,IMDBt*a2+Mtx*a3+IMDBtx*a4) (13A)

Ctotal＝2*Cc+Cab+Cat+2*Cfb+2*Cft+2*Cfbx (14A)

R＝Rho*a7*L/(Mw*a0*Mt*a1) (15A)

Among them, a0-a7 represent different Monte Carlo factors, such as Gaussian factors. It can be understood that since Mw and P-Mw represent the width of the interconnection line and the width of the pitch, the two can be considered as the same type of parameters and can be expressed using the same Gaussian factor a0. In other embodiments, Mw and P-Mw may be assigned different Monte Carlo factors. In addition, since the length L of the interconnection line is usually larger than the width and thickness, local fluctuations have limited influence on it, so the Monte Carlo factor may not be assigned to the length of the interconnection line. It can be understood that different types of parasitic capacitance representations among the parasitic capacitance representation and the resistance representation are assigned different Monte Carlo factors, such as combinations of different Monte Carlo factors. Specifically, different types of process parameters such as interconnect line width, thickness, thickness of dielectric layer, etc. in the representation of parasitic capacitance and resistance can be assigned different Monte Carlo factors. In cases where different materials are used to form the interconnect lines, the resistivities of the different materials may also be assigned different Monte Carlo factors.

An example of an interconnect mismatch model for generating local fluctuations of interconnect parasitic parameters is described above for some embodiments of the present disclosure, but the present disclosure is not limited thereto. In some embodiments, a resistance-capacitance (RC) process file database may also be generated by the field solver using a boundary element or random walk method based on the process parameters and the interconnect model library. This can provide the basis for subsequent global simulation results, and will be described below.

The target netlist data includes a plurality of extracted parasitic parameter representations. FIG. 6 shows a schematic diagram of a labeled interconnect structure 600 according to some embodiments of the present disclosure. The interconnect structure 600 corresponds to the interconnect model 400 of FIG. 4 , thus various aspects described with respect to the interconnect model 400 may be selectively applied to the interconnect structure 600 . The interconnection junction 600 has the parasitic capacitance Cc from label A to label C and label A to label B, the parasitic capacitance Cab+2*2Cft from label A to label D, the parasitic capacitance Cab+2*Cft from label A to label E, Interconnects label A to label A-1 have a resistance of R. An example of netlist data for the interconnect structure 600 may be shown as follows:

C1A C f(Mw*a0,P-Mw*a0,Mt*a1)*L

C2A B f(Mw*a0,P-Mw*a0,Mt*a1)*L

C3A D f(Mw*a0,IMDTt*a3)*L+2*f(Mt*a1,P-Mw*a0,IMDTt*a3)*L

C4A E f(Mw*a0,IMDBt*a2)*L+2*f(Mt*a1,P-Mw*a0,IMDBt*a2)*L

R1A A-1Rho*a4*L/(Mw*a0*Mt*a1)

The target netlist data therefore exemplarily includes extracted parasitic parameter representations C1 , C2 , C3 , C4 and R1 . The target netlist data includes an interconnection adaptation model adapted to the parasitic parameters of the interconnection, which can be used for Monte Carlo simulation and characterizes the local fluctuation effect of the interconnection. It can be understood that the interconnect model 500 in FIG. 5 can also be used to obtain similar target netlist data for representation, and can also be used for Monte Carlo simulation.

In one embodiment, the electronic device can generate an interconnection mismatch model set based on process parameters for the circuit layout and an interconnection model library. For example, an electronic device may compare a circuit layout to a library of interconnect models to generate a set of structures including matching interconnects. The matching interconnection structure set may include interconnection structures corresponding to or matching at least one model in the interconnection model library in the circuit layout (specifically, the interconnection layout). By comparing the circuit layout with the interconnection model library, it is possible to extract interconnection structures including adjacent interconnections that need to be paid attention to in the circuit layout, and reduce the calculation amount of interconnections that do not need to be paid attention to. The electronic device then extracts the set of matching interconnect structures using the set of interconnect mismatch models to generate target netlist data, such as that shown above for interconnect structure 600 of FIG. 6 . By substituting the process parameters of the circuit layout into the corresponding interconnect model library, the user can flexibly configure the interconnect mismatch model set for different process parameters, thereby providing accurate information about the local fluctuations of the parasitic parameters of the interconnect simulation.

At 306, the electronic device simulates the target netlist data to generate local simulation results for adjacent interconnect lines. By using the interconnect model library, interconnect mismatch model set, and circuit layout with local extraction instructions received, it is possible to extract adjacent The parasitic capacitance of an interconnect line is represented and the resistance of an adjacent interconnect line is represented. In addition, since the representations of parasitic capacitance and resistance contain Monte Carlo factors, the situation of local fluctuations can be represented in the representation of parasitic capacitance and resistance. Compared with the conventional scheme of calculating the electrical characteristics of the interconnection line under the limit process angle, the technical solution disclosed in the present disclosure can not only avoid the over-design caused by the limit process angle, but also reflect the local fluctuation of the interconnection line, thereby providing Moderately correct circuit design.

In some other embodiments, if the user enters a global extraction command or selects a global extraction option, the electronic device can call the RC process file database, and can generate target netlist data in a manner similar to the above, based on the interconnect model library , Resistor and capacitor process file database and circuit layout, and generate global netlist data. The global netlist data includes electrical characteristic representations of interconnect lines under multiple process corners, the interconnect line model library includes multiple representations of three-dimensional structures of multiple interconnect lines; and the global netlist data is simulated to generate Global simulation results for interconnect lines under multiple process corners. By also setting the global extraction instruction, not only the simulation of the local fluctuation situation of the parasitic parameter of the interconnection line can be provided, but also the extraction of the electrical characteristics of the interconnection line under a conventional process angle can be provided. This can bring greater flexibility to users to meet different needs.

Fig. 7 shows a schematic block diagram of an example device that may be used to implement embodiments of the present disclosure. As shown, the device 700 includes a computing unit 701 that may be loaded into RAM 703 and/or Computer program instructions in ROM 702 to perform various appropriate actions and processes. In the RAM 703 and/or the ROM 702, various programs and data necessary for the operation of the device 700 can also be stored. Computing unit 701 and RAM 703 and/or ROM 702 are connected to each other via bus 704. An input/output (I/O) interface 705 is also connected to the bus 704 .

Multiple components in the device 700 are connected to the I/O interface 705, including: an input unit 706, such as a keyboard, a mouse, etc.; an output unit 707, such as various types of displays, speakers, etc.; a storage unit 708, such as a magnetic disk, an optical disk, etc. ; and a communication unit 709, such as a network card, a modem, a wireless communication transceiver, and the like. The communication unit 709 allows the device 700 to exchange information/data with other devices over a computer network such as the Internet and/or various telecommunication networks.

The computing unit 701 may be various general-purpose and/or special-purpose processing components having processing and computing capabilities. Some examples of computing units 701 include, but are not limited to, central processing units (CPUs), graphics processing units (GPUs), various dedicated artificial intelligence (AI) computing chips, various computing units that run machine learning model algorithms, digital signal processing processor (DSP), and any suitable processor, controller, microcontroller, etc. The calculation unit 701 executes various methods and processes described above, such as the method 400 . For example, in some embodiments, method 300 may be implemented as a computer software program tangibly embodied on a machine-readable medium, such as storage unit 708 . In some embodiments, part or all of the computer program may be loaded and/or installed onto the device 700 via RAM and/or ROM and/or communication unit 709 . When a computer program is loaded into RAM and/or ROM and executed by computing unit 701, one or more steps of method 300 described above may be performed. Alternatively, in other embodiments, the computing unit 701 may be configured to execute the method 300 in any other suitable manner (for example, by means of firmware).

Program codes for implementing the methods of the present disclosure may be written in any combination of one or more programming languages. These program codes may be provided to a processor or controller of a general-purpose computer, a special purpose computer, or other programmable data processing devices, so that the program codes, when executed by the processor or controller, make the functions/functions specified in the flow diagrams and/or block diagrams Action is implemented. The program code may execute entirely on the machine, partly on the machine, as a stand-alone software package partly on the machine and partly on a remote machine or entirely on the remote machine or server.

In the context of the present disclosure, a machine-readable medium may be a tangible medium that may contain or store a program for use by or in conjunction with an instruction execution system, apparatus, or device. A machine-readable medium may be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium may include, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination of the foregoing. More specific examples of machine-readable storage media would include one or more wire-based electrical connections, portable computer discs, hard drives, random access memory (RAM), read only memory (ROM), erasable programmable read only memory (EPROM or flash memory), optical fiber, compact disk read only memory (CD-ROM), optical storage, magnetic storage, or any suitable combination of the foregoing.

FIG. 8 shows a schematic block diagram of an electronic device 800 according to some embodiments of the present disclosure. FIG. 6 shows a block diagram of an example electronic device 600 for designing a circuit according to an embodiment of the disclosure. The electronic device 800 may include a plurality of modules for performing corresponding steps in the method 300 as discussed in FIG. 3 . As shown in FIG. 8 , an electronic device 800 includes a receiving unit 802, a generating unit 804, and a simulation unit 806. The receiving unit 802 is configured to: receive a local extraction indication for determining a local mismatch of adjacent interconnect lines in the circuit layout. The generation unit 804 is configured to: in response to receiving the partial extraction instruction, generate target netlist data based on the interconnect model library, the interconnect mismatch model set, and the circuit layout, the target netlist data including a plurality of extracted parasitic Parametric representation, the interconnect model library includes multiple representations of the 3D structure of multiple interconnects, the interconnect mismatch model set includes representations of parasitic capacitance between adjacent interconnects and resistance representations of adjacent interconnects , at least one of the parasitic capacitance representation and resistance representation is associated with a Monte Carlo factor. The simulation unit 806 is configured to: perform simulation on the target netlist data to generate a local simulation result for adjacent interconnect lines. By using the interconnect model library, the interconnect mismatch model set, and the circuit layout with local extraction instructions received, it is possible to extract the relevant information in the interconnect mismatch model corresponding to the interconnect mismatch model set. The parasitic capacitance of adjacent interconnect lines is represented and the resistance of adjacent interconnect lines is represented. In addition, since the representations of parasitic capacitance and resistance contain Monte Carlo factors, the situation of local fluctuations can be represented in the representation of parasitic capacitance and resistance. Compared with the conventional scheme of calculating the electrical characteristics of the interconnection line under the limit process angle, the technical solution disclosed in the present disclosure can not only avoid the overdesign caused by the limit process angle, but also reflect the local fluctuation of the interconnection line, thereby Provides moderately correct circuit design.

In some embodiments, the generation unit 804 is further configured to: generate an interconnection mismatch model set based on the process parameters for the circuit layout and the interconnection model library. By substituting the process parameters of the circuit layout into the corresponding interconnect model library, the user can flexibly configure the interconnect mismatch model set for different process parameters, thereby providing accurate information about the local fluctuations of the parasitic parameters of the interconnect simulation.

In some embodiments, the generation unit 804 is further configured to: compare the circuit layout with the interconnect model library to generate a structure set including matching interconnect lines; and use the interconnect mismatch model set to match the interconnect lines The structure set is extracted to generate the target netlist data. By comparing the circuit layout with the interconnection model library, it is possible to extract interconnection structures including adjacent interconnections that need to be paid attention to in the circuit layout, and reduce the calculation amount of interconnections that do not need to be paid attention to.

In some embodiments, the generation unit 804 is further configured to: use the field solver to analyze the models in the interconnection model library based on the process parameters to generate the interconnection mismatch model set.

In some embodiments, the generation unit 804 is further configured as: the field solver uses boundary source or random walk algorithm to solve the model in the interconnect model library based on the process parameters.

In some embodiments, the receiving unit 802 is further configured to: receive a global extraction indication for determining an interconnection line in the circuit layout; the generation unit 804 is further configured to: in response to receiving the global extraction indication, based on the interconnection line Model library, resistor and capacitor process file database and circuit layout, generate global netlist data, global netlist data includes electrical characteristics of interconnection lines under multiple process angles, interconnection line model library includes multiple interconnection lines multiple representations of the three-dimensional structure; and the simulation unit 806 is further configured to: simulate the global netlist data to generate global simulation results for interconnect lines under multiple process corners. By also setting the global extraction instruction, not only the simulation of the local fluctuation situation of the parasitic parameter of the interconnection line can be provided, but also the extraction of the electrical characteristics of the interconnection line under a conventional process angle can be provided. This can bring greater flexibility to users to meet different needs.

In some embodiments, different types of parasitic capacitance representations in the parasitic capacitance representation and the resistance representation are assigned different Monte Carlo factors. In some embodiments, the Monte Carlo factors include Gaussian factors. It is found through research that the use of Gaussian factors can basically cover the local fluctuations of the parasitic parameters of the interconnection lines, so that the local fluctuations of the parasitic parameters of the interconnection lines can be simulated in a simple manner.

Although the subject matter has been described in language specific to structural features and/or methodological acts, it is to be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or acts described above. Rather, the specific features and acts described above are merely example forms of implementing the claims.

Claims

A method for simulating a circuit comprising:

receiving local extraction indications for determining local mismatches of adjacent interconnect lines in a circuit layout;

generating target netlist data including a plurality of extracted parasitic parameters based on the interconnect model library, the set of interconnect mismatch models, and the circuit layout in response to receiving the partial extraction indication representation, the interconnect model library includes multiple representations of the three-dimensional structure of a plurality of interconnects, and the interconnect mismatch model set includes representations of parasitic capacitance between adjacent interconnects and the phase a resistance representation of adjacent interconnect lines, at least one of said parasitic capacitance representation and said resistance representation being associated with a Monte Carlo factor; and

Simulating the target netlist data to generate a local simulation result for the adjacent interconnection lines.
The method according to claim 1, further comprising:

The interconnect mismatch model set is generated based on the process parameters for the circuit layout and the interconnect model library.
The method according to claim 2, wherein generating target netlist data based on the interconnect model library, the interconnect mismatch model set, and the circuit layout comprises:

comparing the circuit layout to the library of interconnect models to generate a set of structures comprising matching interconnects; and

The set of matching interconnect structures is extracted using the set of interconnect mismatch models to generate the target netlist data.
The method according to claim 2 or 3, wherein generating the interconnect mismatch model set based on the process parameters for the circuit layout and the interconnect model library comprises:

Models in the interconnect model library are parsed by a field solver based on the process parameters to generate the interconnect mismatch model set.
The method of claim 4, wherein resolving the models in the interconnect model library based on the process parameters by a field solver comprises:

The field solver uses a boundary source or random walk algorithm to resolve models in the interconnect model library based on the process parameters.
The method according to any one of claims 1-5, further comprising:

receiving global extraction instructions for determining interconnect lines in the circuit layout;

In response to receiving the global extraction instruction, generating global netlist data based on the interconnection model library, the resistor-capacitor process file database, and the circuit layout, the global netlist data includes interconnections under multiple process corners a representation of the electrical properties of the wire, the library of interconnect wire models comprising a plurality of representations of the three-dimensional structure of the plurality of interconnect wires; and

Simulating the global netlist data to generate a global simulation result for the interconnection lines under the multiple process corners.
The method according to any one of claims 1-6, wherein different types of parasitic capacitance representations of the parasitic capacitance representation and the resistance representation are assigned different Monte Carlo factors.
The method according to any one of claims 1-7, wherein said Monte Carlo factors comprise Gaussian factors.
An electronic device comprising:

a receiving unit configured to: receive a local extraction indication for determining a local mismatch of adjacent interconnect lines in the circuit layout;

A generating unit configured to: generate target netlist data based on the interconnect model library, the interconnect mismatch model set, and the circuit layout in response to receiving the partial extraction instruction, the target netlist data including a plurality of extracted parasitic parameter representations, the interconnect model library includes a plurality of representations of the three-dimensional structure of the interconnects, the interconnect mismatch model set includes a representation of parasitic capacitance and a representation of resistance of said adjacent interconnect line, at least one of said representation of parasitic capacitance and said representation of resistance being associated with a Monte Carlo factor; and

The simulation unit is configured to: perform simulation on the target netlist data to generate a local simulation result for the adjacent interconnection lines.
The electronic device according to claim 9, wherein the generating unit is further configured to: generate the interconnection mismatch model set based on the process parameters for the circuit layout and the interconnection model library.
The electronic device according to claim 10, wherein the generating unit is further configured to:

comparing the circuit layout to the library of interconnect models to generate a set of structures comprising matching interconnects; and

The set of matching interconnect structures is extracted using the set of interconnect mismatch models to generate the target netlist data.
The electronic device according to claim 10 or 11, wherein the generating unit is further configured to:

Models in the interconnect model library are parsed by a field solver based on the process parameters to generate the interconnect mismatch model set.
The electronic device according to claim 12, wherein the generating unit is further configured to:

The field solver uses a boundary source or random walk algorithm to resolve models in the interconnect model library based on the process parameters.
The electronic device according to any one of claims 9-13, wherein

The receiving unit is further configured to: receive a global extraction indication for determining an interconnection line in the circuit layout;

The generating unit is further configured to: in response to receiving the global extraction instruction, generate global netlist data based on the interconnect model library, the resistor capacitor process file database and the circuit layout, the global netlist data includes Electrical characteristic representations of interconnect lines at a plurality of process corners, the interconnect model library comprising a plurality of representations of three-dimensional structures of the plurality of interconnect lines; and

The simulation unit is further configured to: simulate the global netlist data to generate a global simulation result for the interconnection lines under the plurality of process corners.
The electronic device according to any one of claims 9-14, wherein different types of parasitic capacitance representations of the parasitic capacitance representation and the resistance representation are assigned different Monte Carlo factors.
The electronic device according to any one of claims 9-15, wherein the Monte Carlo factors comprise Gaussian factors.
An electronic device comprising:

at least one processor;

at least one memory coupled to the at least one processor and storing instructions for execution by the at least one processor that, when executed by the at least one processor, cause the The device performs the method according to any one of claims 1-8.
A computer-readable storage medium, wherein the computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the method according to any one of claims 1 to 8 is implemented.
A computer program product, characterized in that the computer program product includes computer-executable instructions, and when the computer-executable instructions are executed by a processor, the computer implements the method according to any one of claims 1 to 8. method.