CN104617075A - 一种引线框架的封装结构及其制造方法 - Google Patents

一种引线框架的封装结构及其制造方法 Download PDF

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CN104617075A
CN104617075A CN201410162691.5A CN201410162691A CN104617075A CN 104617075 A CN104617075 A CN 104617075A CN 201410162691 A CN201410162691 A CN 201410162691A CN 104617075 A CN104617075 A CN 104617075A
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lead frame
conductive pole
connecting portion
dielectric layer
tin ball
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CN104617075B (zh
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廖宗仁
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Chipmos Technologies Inc
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Chipmos Technologies Inc
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Abstract

本公开提供一种引线框架的封装结构，其包含一裸晶、一介电层、至少一导电柱、至少一引线框架以及至少一锡球。介电层设置于裸晶的表面上。至少一导电柱穿透介电层并设置该表面上。至少一引线框架设置于介电层上并与至少一导电柱间有一间隔。锡球填充该间隔并电性连接该至少一导电柱及该至少一引线框架。

Description

一种引线框架的封装结构及其制造方法
技术领域
本公开涉及一种封装结构，更具体地说，涉及一种引线框架的封装结构。
背景技术
目前的晶圆级封装只能做单面的线路重布层(RDL)及球下冶金层(UBM)。因此当要形成3D积体电路的结构时，就会造成问题。此外，单面的线路重布层(RDL)及球下冶金层(UBM)无法用来进行晶圆对晶圆或晶圆对裸晶之间的结合(bonding)。
发明内容
本公开提供一种引线框架的封装结构，其包含一裸晶、一介电层、至少一导电柱、至少一引线框架以及至少一锡球。
该裸晶包含一表面，而该介电层设置于该表面上。该至少一导电柱穿透该介电层并设置该表面上。该至少一引线框架(lead frame)，设置于该介电层上并与该导电柱间有一间隔。该至少一锡球填充该间隔，并以电性连接该至少一导电柱及该至少一引线框架。
本公开另提供一种多层积体电路结构，其包含一第一封装结构及一第二封装结构。该第一封装结构及该第二封装结构分别包含各自的裸晶、介电层、至少一导电柱、至少一引线框架以及至少一锡球。而该第一封装结构的该至少一引线框架电性连接该第二封装结构的该至少一引线框架，而完成3D积体电路结构。
本公开亦提供一种封装结构的制造方法，包含下列步骤：
提供一裸晶，包含一表面；
形成一至少一导电柱于该表面上；
形成一介电层于该表面上，其中该至少一导电柱穿透该介电层；
设置至少一引线框架于该介电层上，其中该至少一引线框架与该导电柱间有一间隔；以及
设置一锡球，其中该锡球填充该间隔。
上文已相当广泛地概述本公开的技术特征，以使下文的本公开详细描述得以获得较佳了解。构成本公开的申请专利范围标的的其他技术特征将描述于下文。本领域技术人员应了解，可相当容易地利用下文揭示的概念与特定实施例可作为修改或设计其他结构或制程而实现与本公开相同的目的。本领域技术人员亦应了解，这类等效建构无法脱离后附的申请专利范围所界定的本公开的精神和范围。
附图说明
下列图示系并入说明书内容的一部分，以供阐述本公开的各种实施例，进而清楚解释本公开的技术原理。
为了使本公开的叙述更加详尽与完备，可参照下列描述并配合下列图式，其中类似的元件符号代表类似的元件。然以下实施例中所述，仅用以说明本公开，并非用以限制本公开的范围。
图1为根据本公开的一实施例的裸晶及至少一导电柱设置于其上的示意图；
图2为根据本公开的一实施例的介电层设置于裸晶的表面的示意图；
图3为根据本公开的一实施例的引线框架设置于介电层上的示意图；
图4为根据本公开的一实施例的引线框架与至少一导电柱具有间隔的仰视图；
图5为根据本公开的一实施例的引线框架环绕至少一导电柱具有间隔的剖面图；
图6为根据本公开的一实施例的至少一锡球填充间隔的仰视图；
图7为根据本公开的一实施例的复数个引线框架的封装结构堆迭的示意图；
图8为根据本公开的一实施例的复数个引线框架的封装结构堆迭并用封装层封装的示意图；
图9为根据本公开的一实施例的基层的示意图；
图10为根据本公开的一实施例的基层及金属层的示意图；
图11为根据本公开的一实施例的设置光阻于金属层上以供显影蚀刻的示意图；
图12为根据本公开的一实施例的金属层经蚀刻而形成孔洞的示意图；
图13为根据本公开的一实施例的移除图案光阻的示意图；
图14为根据本公开的一实施例的裸晶翻转设置于蚀刻后的金属层的示意图；
图15为根据本公开的一实施例的引线框架设置于金属层下的示意图；
图16为根据本公开的一实施例的封装层设置于裸晶上的示意图；图17为根据本公开的一实施例的设置引线框架于环绕复数个导电柱的仰视图；
图18为根据本公开的一实施例的去除部份金属层并移除裸晶封装层背面设置锡球的示意图；
图19为根据本公开的一实施例的锡球填充复数个间隔及覆盖导电柱的仰视图；以及
图20为根据本公开的一实施例的复数个如图18所示的封装结构堆迭的示意图。
具体实施方式
本公开的引线框架的封装结构的制造方法包含下列所述的各种图式的步骤，然而并不限于此，亦可因应不同的设计而省略或修正特定步骤。
如图1所示，提供一裸晶10，而裸晶10包含一表面11。
在此实施例中，形成至少一导电柱30于该表面11上。在此说明书及申请专利范围中的名词「上」包含第一物件直接或间接地设置于第二物件的上方。例如，至少一导电柱30设置于表面11上就包含，至少一导电柱30「直接」设置于表面11上及至少一导电柱30「间接」设置于表面11上，两种意义。此处的「间接」系指两个物件在某一方位的垂直方向中具有上与下的关系，且两者中间仍有其他物体、物质或间隔将两者隔开，该导电柱30可为电镀铜柱或其它具导电性的金属材质。
如图2所示，一介电层20形成于表面11上，但不覆盖导电柱30。换言的，导电柱30穿透介电层20。如图2所示，导电柱30凸出于表面11的介电层20上。
如图3所示，设置至少一引线框架40于介电层20上。在此实施例中，引线框架40包含连接部41及支撑部42。连接部41与支撑部42形成L型。换言的，连接部41与支撑部42彼此连接且连接部41垂直于支撑部42。然而在其他实施例(图未示)中，连接部41与支撑部42亦可设计为其他结构，而不必然为L型。
如图4所示，引线框架40的连接部41的末端为环状或框形，引线框架40的连接部41与导电柱30之间有一间隔50。该间隔50具有一预设距离D，其可供调整而供锡球更容易容置或结合。在其他实施例(图未示)中，连接部41的末端为亦可为直线状或长条状，此时连接部41的末端与导电柱30之间亦可有一间隔50。
如图5所示，设置至少一锡球60来填充间隔50。具体而言，锡球60设置于导电柱30上用以连接引线框架40的连接部41的末端，并据以做为对外电性连接的端子。如图6所示，锡球60可用于电性连接导电柱30与引线框架40，以供电讯号藉由引线框架40来传输。换言的，本公开系电性连接至少一锡球60、至少一导电柱30及至少一引线框架40。
在此实施例中，于锡球60填充前，连接部41环绕至少一导电柱30。于锡球60填充后，锡球60电性连接引线框架40的连接部41，并使引线框架40与导电柱30固接。而锡球60形成的方式可利用锡膏预先形成于连接部41与导电柱30上，利用回焊的方式，使锡膏形成锡球，在另一可行的实施例中，亦可利用锡料预设于该连接部41与导电柱30上，再利用置球(Ball Drop)或电镀的方式将锡球60在形成于导电柱30上。
如图5及图6所示，本公开的引线框架的封装结构100包含裸晶10、介电层20、至少一导电柱30、至少一引线框架40以及至少一锡球60。虽然此实施例显示两支导电柱30、两支引线框架40以及两个锡球60，但是本公开亦可用单一导电柱30、单一引线框架40及单一锡球60或多于二以上的数量均可完成本公开的引线框架的封装结构100的功能。是故，本公开的实施例不必然限缩于图式中。
如图7所示，本公开的多层积体电路结构200包含复数个引线框架的封装结构。在此实施例中，第一封装结构110的至少一引线框架40的支撑部42电性连接第二封装结构120的至少一引线框架40。具体而言，一连接锡球61连接第一封装结构110的支撑部42与第二封装结构120的支撑部42，做为电性连接，此外，每一封装结构的锡球60可立置于相邻间的裸晶10表面上，以提供堆迭结构的稳定性。在此实施例中，多层积体电路结构200具有三个引线框架的封装结构。然而，多层积体电路结构200亦可只含有两个引线框架的封装结构或两个以上的个引线框架的封装结构。
如图8所示，以一封装层70包覆复数个裸晶10。具体而言，封装层70可包覆大部分的多层积体电路结构200，并暴露最底层的引线框架的封装结构100的锡球60。
本公开提供另一种引线框架的封装结构的制造方法，其包含下列所述的各种图式的步骤，然而并不限于此，亦可因应不同的设计而省略或修正特定步骤。
如图9所示，基层12上设置一金属层71(例如铜膜Cu film)而如图10所示。该基层12例如是金属、玻璃或硅基板等可供承载的载板。
如图11所示，设置一光阻90于金属层71上而后将光阻90图案化而如图12所示。具体而言，图案光阻90只暴露部分区域91。该部分区域91将进一步进行蚀刻位于部分区域91的金属层71。
如图13所示，此时，图案光阻90已经去除，而留下蚀刻后的金属层71于基层12上。
如图14所示，基层12去除后，裸晶10翻转朝下而使导电柱30穿过蚀刻后的金属层71的孔洞并使介电层20设置于金属层71上。
如图15所示，引线框架40设置于金属层71下，此时引线框架40的支撑部42穿越蚀刻后的金属层71的孔洞且连接部41允许导电柱30穿越连接部41的孔洞。
如图16所示，进行一封胶制程，使封装层70包覆裸晶10、金属层71及引线框架40。其中，支撑部42伸置于封装层70内部，因此支撑部42可加强封装层70的强度。
如图17所示，引线框架40的连接部41环绕导电柱30。由于金属层71并无接触导电柱30，因此连接部41与导电柱30间的介电层20将暴露出来。
如图18所示，局部去除位于介电层20上设置于两导电柱30之间的金属层71，进而于引线框架40与介电层20间形成间隙21。具体而言，引线框架40的连接部41与介电层20间具有间隙21，间隙21可供引线框架40或介电层20散热，以避免晶片过热。此外，部分的金属层71设置于连接部41与封装层70之间，以供将介电层20的热能传导至封装层70的侧边并解决3D积体电路堆迭的散热问题。
如图18所示，引线框架40的支撑部42穿伸于封装层70后，接着进行一移除封装层70使支撑部742局部曝光的步骤，其中移除的方式例如是施行一道蚀刻制程，例如是CO2雷射，以暴露出局部的支撑部42，接着，再电性连接至一锡球80形成于封装层70背面。另一可行的实施例中，移除封装层的方式例如是研磨封装层70背面，以暴露出局部的支撑部42，接着再电性连接一锡球80；具体而言，锡球80系设置于支撑部42之上。此外，在此实施例中，锡球60亦设置于导电柱30之上。此外，由于封装层70具有引线框架40的支撑部42的支撑骨架，所以封装层70整体较不会有因为堆迭而弯曲(warpage)的问题。再者，目前的晶圆级封装只能做单面的线路重布层(RDL)及球下冶金层(UBM)。由于背面锡球80系设置于支撑部42之上，因此本公开可完成将双面的电路配置。是故，本公开可完成堆迭的3D积体电路结构。
如图19所示，锡球60连接引线框架40的连接部41与导电柱。换言的，裸晶10可藉由导电柱30、锡球60、连接部41及支撑部42电性连接至背面锡球80，而使电讯号可传输至封装层70背面。在此实施例中，引线框架40的连接部41的末端为环状、框状。在其他实施例(图未示)中，连接部41的末端亦可为直线状或长条状。在图17所示的实施例中，一个平面可包含复数个封装结构130。
此外，如图20所示，上述平面的复数个封装结构130亦可于垂直方向上相互堆迭而形成另一种多层积体电路结构210。
本公开的技术内容及技术特点已揭示如上，然而本公开所属技术领域中具有通常知识者应了解，在不背离后附申请专利范围所界定的本公开精神和范围内，本公开的教示及揭示可作种种的替换及修饰。例如，上文揭示的许多装置或结构可以不同的方法实施或以其它结构予以取代，或者采用上述二种方式的组合。
附图标记说明
10  裸晶
11  表面
12  基层
20  介电层
21  间隙
30  导电柱
40  引线框架
41  连接部
42  支撑部
50  间隔
60  锡球
61  连接锡球
70  封装层
71  金属层
80  锡球
90  光阻
91  部分区域
100 封装结构
110 第一封装结构
120 第二封装结构
130 封装结构
200 多层积体电路结构
210 多层积体电路结构
D   预设距离

Claims (17)

1.一种引线框架的封装结构，包含：
一裸晶，包含一表面；
一介电层，设置于所述表面上；
至少一导电柱，穿透所述介电层并设置所述表面上；
至少一引线框架，设置于所述介电层上并与所述导电柱间有一间隔；以及
至少一锡球，填充所述间隔，以电性连接所述至少一导电柱及所述至少一引线框架。
2.根据权利要求1所述的连接结构，其中所述至少一引线框架包含一连接部与所述至少一锡球电性连接，所述连接部环绕所述至少一导电柱，以形成所述间隔。
3.根据权利要求2所述的连接结构，其中所述至少一引线框架另包含一支撑部与所述连接部连接且所述支撑部垂直于所述连接部。
4.根据权利要求1所述的连接结构，进一步包含一封装层包覆所述裸晶。
5.根据权利要求4所述的连接结构，其中所述至少一引线框架包含一支撑部，所述支撑部穿透所述封装层并电性连接至少一锡球。
6.根据权利要求5所述的连接结构，进一步包含一金属层，其中所述至少一引线框架另包含一连接部，所述金属层设置于所述连接部与所述封装层之间，且所述连接部与所述至少一锡球电性连接，所述连接部环绕所述至少一导电柱。
7.根据权利要求6所述的连接结构，其中所述连接部与所述介电层间有一间隙。
8.一种多层积体电路结构，包含：
一第一封装结构，为如权利要求1所述的封装结构；以及
一第二封装结构，为如权利要求1所述的封装结构；
其中所述第一封装结构的所述至少一引线框架电性连接所述第二封装结构的所述至少一引线框架。
9.一种封装结构的制造方法，包含：
提供一裸晶，包含一表面；
形成至少一导电柱于所述表面上；
形成一介电层于所述表面上，其中所述至少一导电柱穿透所述介电层；
设置至少一引线框架于所述介电层上，其中所述至少一引线框架与所述导电柱间有一间隔；以及
设置一锡球，其中所述锡球填充所述间隔。
10.根据权利要求9所述的制造方法，进一步包含步骤：电性连接所述至少一锡球、所述至少一导电柱及所述至少一引线框架。
11.根据权利要求9所述的制造方法，其中所述至少一引线框架包含一连接部并进一步包含步骤：电性连接所述连接部与所述至少一锡球及环绕所述连接部于所述至少一导电柱。
12.根据权利要求11所述的制造方法，其中所述至少一引线框架另包含一支撑部，所述支撑部与所述连接部连接且所述支撑部垂直于所述连接部。
13.根据权利要求12所述的制造方法，进一步包含步骤：以一封装层包覆所述裸晶。
14.根据权利要求13所述的制造方法，进一步包含步骤：设置一金属层于所述介电层上。
15.根据权利要求14所述的制造方法，进一步包含步骤：移除所述封装层以暴露出所述支撑部。
16.根据权利要求15所述的制造方法，进一步包含步骤：设置至少一锡球于所述暴露出的支撑部上。
17.根据权利要求15所述的制造方法，移除所述封装层的方法包含蚀刻或研磨所述封装层。
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CN105934095B (zh) * 2016-06-28 2019-02-05 Oppo广东移动通信有限公司 Pcb板及具有其的移动终端

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