CN104603919B - Thin film transistor (TFT) and display device - Google Patents

Thin film transistor (TFT) and display device Download PDF

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Publication number
CN104603919B
CN104603919B CN201380045020.4A CN201380045020A CN104603919B CN 104603919 B CN104603919 B CN 104603919B CN 201380045020 A CN201380045020 A CN 201380045020A CN 104603919 B CN104603919 B CN 104603919B
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oxide semiconductor
semiconductor layer
tft
film
layer
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CN104603919A (en
Inventor
三木绫
森田晋也
后藤裕史
田尾博昭
钉宫敏洋
安秉斗
金建熙
朴辰玄
金连洪
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Kobe Steel Ltd
Samsung Display Co Ltd
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Kobe Steel Ltd
Samsung Display Co Ltd
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
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    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
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    • H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel
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    • H10K59/10—OLED displays
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    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
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    • H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
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    • H01L2924/13069—Thin film transistor [TFT]

Abstract

The present invention provides a kind of thin film transistor (TFT), and it is in the thin film transistor (TFT) for possessing oxide semiconductor layer film, and for light or deviated stress etc., the variable quantity of threshold voltage is small and stress tolerance is excellent.The thin film transistor (TFT) of the present invention is the thin film transistor (TFT) for possessing gate electrode, the oxide semiconductor layer of individual layer for channel layer, the etch stop layer on surface for protecting oxide semiconductor layer, source-drain electrode and the gate insulating film being configured between gate electrode and channel layer; wherein; the metallic element for constituting oxide semiconductor layer is made up of In, Zn and Sn, and the hydrogen concentration in the gate insulating film directly contacted with the oxide semiconductor layer is controlled in below 4 atom %.

Description

Thin film transistor (TFT) and display device
Technical field
The present invention relates to the thin film transistor (TFT) for display devices such as liquid crystal display or organic el displays (TFT), with And possess the display device of the thin film transistor (TFT).
Background technology
Amorphous (noncrystalline) oxide semiconductor is compared with general non-crystalline silicon (a-Si), with high carrier mobility (it is also referred to as field-effect mobility.Hereinafter sometimes referred to simply as " mobility ".), optical band gap is big, can be with film formation at low temp.Therefore, Expect that it should towards require large-scale, high-resolution, the display of new generation of high-speed driving or the low resin substrate of heat resistance etc. With (patent document 1 etc.).
In oxide semiconductor, the amorphous oxide semiconductor (In-Ga-Zn- that particularly indium, gallium, zinc and oxygen are constituted O, hereinafter sometimes referred to as " IGZO ".) because having very high carrier mobility, and be preferably used.For example in non-patent text Offer in 1 and 2, disclose is used for film crystalline substance by the oxide semiconductor thin-film of In: Ga: Zn=1.1: 1.1: 0.9 (atom % ratios) The semiconductor layer (active layer) of body pipe (TFT).
Use oxide semiconductor as thin film transistor (TFT) semiconductor layer when, do not require nothing more than carrier concentration (migration Rate) it is high, but also require that TFT switching characteristic (transistor characteristic, TFT characteristics) is excellent.Specifically, it is desirable to (1) on-state electricity Stream (applying maximum leakage current during positive voltage to gate electrode and drain electrode) is high；(2) off state current (applies negative to gate electrode respectively Voltage, applies leakage current during positive voltage to drain electrode) it is low；(3) (Subthreshold Swing make leakage current improve 1 to SS values Gate voltage required for digit magnitude) it is low；(4) threshold voltage (applies positive voltage to drain electrode, applies positive and negative any to gate voltage During a kind of voltage, the voltage that leakage current goes into circulation) do not change in time and keep stable；Also, (5) mobility It is high；Deng.
In addition, further requirement has used the TFT of the oxide semiconductor layers such as IGZO for voltage application or light irradiation etc. The tolerance (stress tolerance) of stress is excellent.Example has as noted：When being continuously applied voltage to gate electrode or prolonged exposure During the light of the blue wave band absorbed in the semiconductor layer, at gate insulating film and the semiconductor layer interface of thin film transistor (TFT), Electric charge is captured, and due to the change of the electric charge inside semiconductor layer, threshold voltage significantly changes (skew) to minus side, thus, TFT switching characteristic change.If causing switching characteristic to change because light irradiation or voltage apply the stress caused, it can recruit Cause the reliability reduction of display device itself.
In addition, for organic el display similarly, the light leaked from luminescent layer can be irradiated on semiconductor layer, cause threshold The problem of threshold voltage is equivalent at random.
Thus, the skew of especially threshold voltage can cause possess TFT liquid crystal display or organic el display etc. show The reliability reduction of showing device itself, therefore be strongly desired to improve stress tolerance (variable quantity before and after stress applies is few).
As the technology for the electrology characteristic for improving TFT, for example, patent document 2.Patent Document 2 discloses It is reduced to the hydrogen concentration of insulating barrier (including gate insulator) connected with forming the oxide semiconductor layer of channel region small In 6 × 1020Atom/cm3, suppress the technology that hydrogen spreads to oxide semiconductor layer.If hydrogen spreads to oxide semiconductor layer, Carrier in oxide semiconductor layer becomes superfluous, and therefore, threshold voltage changes to negative direction, even in not applied to gate electrode Under alive state (Vg=0V), leakage current also flows (often conducting), as the bad transistor of electrology characteristic.So special Recorded in sharp document 2 turns into the insulated by oxide that hydrogen concentration is reduced by the insulating barrier for making to connect with oxide semiconductor layer Layer, is spread so as to suppress hydrogen to oxide semiconductor layer, and oxygen is supplied from insulating barrier to the defect of oxide semiconductor layer, therefore brilliant The electrology characteristic of body pipe becomes good.The hydrogen concentration for being used to play in the insulating barrier of the effect is recorded in patent document 2 necessary Drop below 6 × 1020Atom/cm3.In addition, also describing being formed using plasma CVD method, such to reduce hydrogen dense In the case of the insulating barrier of degree, it is necessary to select gas not hydrogeneous in molecular structure (that is, without using usually used SiH4And make Use SiF4) used as accumulation property gas.But, in above-mentioned patent document 2, the raising of stress tolerance is not noticed completely (threshold voltage variation especially for light or deviated stress is reduced).
Prior art literature
Patent document
Patent document 1：Japanese Unexamined Patent Publication 2011-108873 publications
Patent document 2：Japanese Unexamined Patent Publication 2012-9845 publications
Non-patent literature
Non-patent literature 1：Solid-state physics, VOL44, P621 (2009)
Non-patent literature 2：Nature、VOL432、P488(2004)
The content of the invention
The invention problem to be solved
The present invention is completed in view of the above problems, and its object is to provide in the film for possessing oxide semiconductor layer film In transistor, for light or deviated stress etc., the variable quantity of threshold voltage is small and stress tolerance is excellent thin film transistor (TFT), with And possess the display device of thin film transistor (TFT).
Means for solving the problems
The thin film transistor (TFT) of the invention that can solve the problem that above-mentioned problem be possess gate electrode, for channel layer individual layer oxygen Compound semiconductor layer, the etch stop layer on surface for protecting oxide semiconductor layer, source-drain electrode and it is configured at gate electrode The thin film transistor (TFT) of gate insulating film between channel layer, it has following main points：Constitute the oxide semiconductor layer Metallic element is made up of In, Zn and Sn, and in the gate insulating film directly contacted with the oxide semiconductor layer Hydrogen concentration is controlled in below 4 atom %.
In a preferred embodiment of the invention, above-mentioned gate insulating film has the stacking knot of single layer structure or more than two layers Structure, in the case of with the stepped construction, the hydrogen concentration in the layer directly contacted with the oxide semiconductor layer is controlled System is in below 4 atom %.
In a preferred embodiment of the invention, the content by each metallic element relative to all metallic elements except oxygen When (atom %) is set to [In], [Zn] and [Sn], the oxide semiconductor layer meets following relation：
15≤[In]≤35、50≤[Zn]≤60、15≤[Sn]≤30。
Present invention additionally comprises possess it is above-mentioned any one of thin film transistor (TFT) display device.
Invention effect
In accordance with the invention it is possible to provide due to the hydrogen concentration in the gate insulating film that is directly contacted with oxide semiconductor layer Be lowered in appropriate scope, thus switching characteristic and stress tolerance it is excellent (specifically, not only back bias voltage apply before The offset of threshold voltage afterwards is few, and the offset of the threshold voltage before and after light irradiation and back bias voltage application is few) film crystalline substance Body pipe.If using the thin film transistor (TFT) of the present invention, the high display device of reliability can be obtained.
Brief description of the drawings
Fig. 1 is the constructed profile illustrated for the thin film transistor (TFT) to the present invention.
Embodiment
The oxide semiconductor layer being made up of defined metallic element is used for TFT activity by the present inventor etc. in order to provide Stress tolerance during layer (offset of the threshold voltage before and after back bias voltage applies and before and after light irradiation+back bias voltage application is few) Excellent thin film transistor (TFT), has been repeated investigation.If as a result, finding the grid that will directly be contacted with oxide semiconductor layer Hydrogen concentration in the dielectric film of pole is reduced in appropriate scope, then can reach expected purpose.Additionally, it was found that for such grid For the dielectric film of pole, at least suitable control will be exhausted with the grid that oxide semiconductor layer is directly contacted using plasma CVD method Condition (such as temperature, film forming power density, the SiH as accumulation gas during velum film forming4Relative to N2O flow-rate ratio) be Can, so as to complete the present invention.
That is, thin film transistor (TFT) of the invention is characterised by, possess gate electrode, for channel layer individual layer oxide half Conductor layer, the etch stop layer on surface for protecting oxide semiconductor layer, source-drain electrode (are also sometimes referred to as " S/D electricity Pole ") and the thin film transistor (TFT) of gate insulating film that is configured between gate electrode and channel layer, constitute the gold of oxide semiconductor layer Category element is made up of In, Zn and Sn, and the hydrogen concentration in the gate insulating film directly contacted with oxide semiconductor layer is controlled System is in below 4 atom %.
In this manual, [In], [Zn], [Sn] refer to In, Zn, Sn relative to all metallic elements except oxygen (O) Each content (atom %) of (In, Zn, Sn).
In this manual, " stress tolerance is excellent " refers to, is utilizing the method described in embodiment described later, difference Carry out (a) and apply experiment (NBTS) and (b) side to the stress of gate electrode application back bias voltage to the white plain edge of sample irradiation to grid When the stress that electrode is continuously applied back bias voltage applies experiment (LNBTS) 2 hours, following important document is met.
For (a) NBTS, the offset Δ Vth (absolute value) that stress applies the threshold voltage (Vth) before and after experiment is less than 5.0V。
For (b) LNBTS, the offset Δ Vth (absolute value) that stress applies the threshold voltage (Vth) before and after experiment is less than 5.0V, SS values are less than 0.55V/decade, and stress applies the variation delta Ion of the on state current (Ion) before and after experiment (definitely Value) it is less than 10%.
These assay methods are described in detail in the column of embodiment one described later.
It should be noted that in foregoing patent document 2, also disclosing that the hydrogen concentration in reduction gate insulator comes real The improved technology of existing electrology characteristic, but the present invention is different in the following areas.
First, it is resistance to provide the few stress of the variable quantity of the threshold voltage before and after stress applies as described above in the present invention By the excellent thin film transistor (TFT) of property to solve problem, on the other hand, in patent document 2, although be related to the record of threshold voltage, But the not record on raising stress tolerance.It is specify that according to the discussion result of the present inventor etc. by reducing gate insulator The hydrogen amount of film, back bias voltage stress tolerance (NBTS) is improved.Also it specify that by reducing the hydrogen amount of gate insulating film, to above-mentioned Back bias voltage+light irradiation stress tolerance (LNBTS) that NBTS addition of light irradiation is also improved.These opinions are not recorded in patent In document 2.
In addition, strictly speaking, the scope of the hydrogen concentration in the gate insulator of the two is also different.This is due to be used to obtain (it is described in detail later) caused by the film build method difference of the two of gate insulator.That is, as described above in patent document 2, as Gas is accumulated, without using the SiH generally used in the film forming of gate insulator4, and select using the SiF being often used without4, Thus the hydrogen concentration in gate insulator is reduced significantly to be less than 6 × 1020Atom/cm3(i.e. less than 0.667 atom %).With This is relative, in the present invention, premised on using the SiH4 generally used in the film forming of gate insulator, passes through suitable control gas Flow-rate ratio, temperature, film forming power density of body etc., so that the hydrogen concentration in gate insulator is reduced to below 4 atom %.If Hydrogen amount is terrifically reduced as patent document 2, then film-forming temperature during gate insulator film forming becomes too high, or input power Become too high, rate of film build terrifically slows down, therefore the cycle time increase of TFT manufactures, and be not suitable for.Therefore, from practical Viewpoint is set out, it is desirable to which the upper limit that the lower limit of the hydrogen concentration in gate insulator in the present invention is more than patent document 2 (is less than 0.667 atom %) and be more than 0.667 atom %.
Hereinafter, side reference picture 1, while being carried out specifically to the thin film transistor (TFT) (TFT) and its preferable production process of the present invention It is bright.But, Fig. 1 is the constructed profile illustrated for a preferred embodiment of the TFT to the present invention, and the present invention does not have It is limited in this meaning.Bottom gate type TFT for example in Fig. 1 is shown, but is not limited to this, can be successively in oxygen since substrate-side Possesses the top gate type TFT of gate insulating film and gate electrode on compound semiconductor layer.
As shown in figure 1, the TFT of present embodiment has sequentially formed gate electrode 2 and gate insulating film 3 on substrate 1, in grid Oxide semiconductor layer 4 is formd on pole dielectric film 3.Source-drain electrode 5 is formd on oxide semiconductor layer 4, in shape thereon Into diaphragm (dielectric film) 6, nesa coating 8 is electrically connected to drain electrode 5 via contact hole 7.In addition, partly being led in oxide On body layer 4, the etch stop layer 9 on the surface for protecting oxide semiconductor layer 4 is formd.
First, prepared substrate.If the substrate usually used in the field of display device for substrate 1 of the invention is then It is not particularly limited, can exemplifies such as alkali-free glass, soda-lime glass.Wherein it is preferred that alkali-free glass.
Then, gate electrode 2 is formed on substrate 1.The species of gate electrode 2 is also not particularly limited, and can use in this hair The gate electrode commonly used in bright technical field.Specifically it is preferable to use the low Al or Cu metals of resistivity, heat resistance are high Refractory metal or their alloy such as Mo, Cr, Ti.The method for forming gate electrode 2 is also not particularly limited, and can use Commonly used approach.
Next, forming gate insulating film 3.Gate insulating film 3 is configured at gate electrode 2 and the oxide as channel layer half Between conductor layer 4.And it is a feature of the present invention that in the gate insulating film 3 directly contacted with the oxide semiconductor layer Hydrogen concentration be controlled in below 4 atom %.According to the experimental result of the present inventor etc., it specify that by control and oxide half Hydrogen amount in the gate insulating film 3 that the interface of conductor layer 4 connects, deviated stress and the tolerance for light+negative bias compression show Write and improve (with reference to embodiment described later).
It should be noted that gate insulating film 3 can be made up of individual layer, more than two layers can also be laminated and constituted.Stacking The number of plies of structure is not particularly limited, but in view of productivity ratio, processability etc., is preferably laminated less than about three layers.
In the case that gate insulating film 3 has stepped construction, the hydrogen in the layer directly contacted with oxide semiconductor layer 4 is dense Degree is controlled in below 4 atom %, and the hydrogen concentration in the layer not contacted directly is not particularly limited.
If from the viewpoint of stress tolerance raising, the hydrogen concentration in gate insulating film 3 is the smaller the better, is preferably Below 3.5 atom %, more preferably below 3 atom %.From the viewpoint of above-mentioned characteristic, the hydrogen concentration in gate insulating film 3 Lower limit be not particularly limited, if but in view of the film build method of gate insulating film 3 described later, preferably above patent document 2 The upper limit (be less than 0.667 atom %) and be more than 0.667 atom %.
In the present invention, the hydrogen concentration in gate insulating film can pass through the film forming bar in suitable control plasma CVD method Part and be reduced to prescribed limit.
Specifically, first preferably by temperature control during film forming more than about 250 DEG C.Institute in embodiment as be described hereinafter Confirm, if temperature during film forming is less than 250 DEG C, can not fully reduce hydrogen concentration, and stress tolerance is reduced.Speculate this be by In film-forming temperature reduction causes the density of formed film to reduce, SiO2Si -- H bond increase in film.Preferred film-forming temperature For more than 270 DEG C, more preferably more than 300 DEG C.If it should be noted that in view of the ceiling temperature of used device Deng then its upper limit is preferably controlled in less than about 450 DEG C.
In addition, power density during film forming is preferably controlled in about 0.6W/cm2More than.Demonstrate,proved in embodiment as be described hereinafter It is real, if power density during film forming is less than about 0.6W/cm2, then hydrogen concentration can not be fully reduced, and stress tolerance is reduced. If speculating, this is because, film forming power density is too low, film density reduction, Si -- H bond is included into film.Preferred film forming work( Rate density is 0.66W/cm2More than, more preferably 0.7W/cm2More than.
In addition, gas during for film forming, preferably makes SiH4Relative to N2O tries one's best few, i.e. make SiH4/N2The stream that O is represented Amount is certain following than (volume ratio).When the flow-rate ratio is high, it is seen that SiO2Film density reduction, it is believed that largely contain Si -- H bond.
Membrance casting condition other than the above is not particularly limited, can be using the condition generally carried out.
For example for air pressure, as the air pressure of discharge stability degree, about 50~300Pa is preferably controlled in.
The gate insulating film 3 formed by the above method is with silicon oxide layer (SiO2) based on, in addition, the hydrogen in film Si-N keys can be included in the not increased scope of content.
For example, with SiO2For the silicon oxide layer (SiO of representativex) fine and close and embody good insulation characterisitic, but have film forming speed The slow shortcoming of degree.Therefore, by by the faster SiH of film forming speedxFilm and SiOxFilm layer is folded and constitutes gate insulating film 3, Neng Goushi Existing insulation characterisitic and productivity ratio are taken into account.Now, in order to ensure insulation characterisitic, SiNxThe thickness of film is relative to SiOxThe thickness of film Preferably less than 50 times, more preferably less than 25 times.
Then, oxide semiconductor layer 4 is formed on gate insulating film 3.The oxide semiconductor layer 4 is typically sandwiched in above-mentioned Between gate insulating film 3 and source-drain electrode (S/D electrodes) 5.In the present invention, the metallic element of oxide semiconductor layer 4 by In, Zn and Sn constitutes (oxide semiconductor layer=IZTO).
The summary of the effect of above-mentioned metallic element is as follows.
First, In has the effect for increasing carrier and improving mobility.But, if In quantitative changes are more, carrier becomes It is excessive and conductor, in addition, the stability for stress are reduced.
Sn has the effect for improving the decoction tolerances of oxide semiconductor layer such as wet etching.But, if Sn quantitative changes are more, Then etching and processing is reduced.
Zn is believed to be helpful in the stabilisation of non crystalline structure, also contributes to the stability for stress.But, if Zn Quantitative change is more, then oxide semiconductor thin-film is crystallized, or produces residue in etching.
Oxide semiconductor layer 4 is made up of individual layer.
[each metallic element is relative to except oxygen for the preferred metal ratio of each metallic atom of composition oxide semiconductor layer 4 The preferred content (atom %) of all metallic elements] preferably in the way of it can obtain good TFT characteristics etc., it is suitable, suitable Locality is controlled.
Specifically, the content (atom %) by each metallic element relative to all metallic elements except oxygen is set to When [In], [Zn] and [Sn], the metal of preferred oxides semiconductor layer 4 (IZTO) relation following than meeting.Thereby, it is possible to have Effect plays the ideal role of above-mentioned each element.
15≤[In]≤35 (more preferably 15≤[In]≤25)
50≤[Zn]≤60
15≤[Sn]≤30
The preferred thickness of oxide semiconductor layer 4 is about more than 10nm and below 200nm.
Oxide semiconductor layer 4 is preferably splashed by using the DC sputtering methods or RF of the sputtering target constituted with film identical The method of penetrating carrys out film forming.Or film forming can be come by using the cosputtering method of a variety of sputtering targets.
Oxide semiconductor layer 4 is carried out after wet etching, patterned.After immediately patterning, in order to improve oxidation The film quality of thing semiconductor layer 4, can be in such as temperature：250~350 DEG C of (preferably 300~350 DEG C), times：15~120 minutes It is heat-treated (preannealing) under conditions of (preferably 60~120 minutes).Thus, the on state current of transistor characteristic and field-effect Mobility rises, and improves transistor performance.
Then, in order to protect the surface of oxide semiconductor layer 4, etch stop layer 9 is formed.Etch stop layer 9 is with such as Formed by for the purpose of lower, that is, prevent that oxide semiconductor layer 4 is eclipsed when carrying out wet etching to source-drain electrode (S/D electrodes) 5 Carve and be damaged, and oxide semiconductor layer 4 surface produce defect and transistor characteristic reduction.The species of etch stop layer 9 It is not particularly limited, for example, SiO2Deng dielectric film.Etch stop layer 9 by plasma CVD method etc. film forming and Patterning, is formed to protect channel surface.
Next, in order to connect oxide semiconductor layer 4 and source-drain electrode 5 of next formation, implementing photoetching and dry corrosion Carve the patterning for carrying out electrode formation.
Then, source-drain electrode 5 is formed.Species for source-drain electrode 5 of the present invention is not particularly limited, and can use Conventional electrode.For example can be in the same manner as gate electrode, using metal or alloy such as Al, Mo or Cu, reality that can also be as be described hereinafter Apply example and use pure Mo.
, for example can be by magnetron sputtering method by metallic film film forming, Ran Houtong as the forming method of source-drain electrode 5 Cross photoetching and pattern, and carry out wet etching and form electrode.
As other forming methods of source-drain electrode 5, for example, by magnetron sputtering method by metallic film into Film, then passes through the method for lift-off (lift off) method formation.According to this method, electrode can be carried out without wet etching Processing.
Then, by the film forming of diaphragm (dielectric film) 6 on oxide semiconductor layer 4.Diaphragm 6 can be for example, by CVD Method film forming.It should be noted that because the surface of oxide semiconductor layer 4 is easy due to the plasma damage that CVD is caused (supposition is probably because the oxygen defect in oxide semiconductor Surface Creation turns into electron donor to earthed conductor.), it therefore, it can N is carried out before the film forming of diaphragm 62O plasma irradiatings.N2The irradiation condition of O plasmas can be remembered using following documents The condition of load.
J.Park etc., Appl.Phys.Lett., 93,053505 (2008).
Then, by photoetching and dry ecthing, formed in diaphragm 6 after contact hole 7, form nesa coating 8.It is transparent to lead The species of electrolemma 8 is not particularly limited, the nesa coating that ITO etc. can be used usually used.
In the present invention, also comprising the display device for possessing above-mentioned TFT.As display device, for example, liquid crystal Show device, organic el display etc..
The application is based on Japan's patent application the 2012-192666th and in April, 2013 filed in August in 2012 31 days The interests of Japan's patent application 2013-094087 CLAIM OF PRIORITYs filed in 26 days.Day filed in August in 2012 31 days Japan's patent application the 2013-094087th filed in national patent application the 2012-192666th and 26 days April in 2013 Specification full content as with reference to quoting in the application.
Embodiment
Hereinafter, enumerate embodiment and further illustrate the present invention, but the present invention is not limited by following embodiments, Ke Yi It can be adapted to be changed to implement in the range of purport foregoing, described later, these are all contained in the technical scope of the present invention.
Embodiment 1
The TFT shown in Fig. 1 is made in the following manner, evaluates stress tolerance etc..But, in the present embodiment, Fig. 1's is transparent The non-film forming of conducting film 8.
First, on glass substrate 1 (Corning Incorporated's system " EAGLE 2000 ", diameter 100mm × thickness 0.7mm), successively It regard 100nm Mo films as the film forming of gate electrode 2 and the SiO by 250nm2Film is used as the film forming of gate insulating film 3.
Gate electrode 2 is formed using pure Mo sputtering target by DC sputtering methods.Sputtering condition is set to as follows, film-forming temperature：Room Temperature, film forming power density：3.8W/cm2, carrier gas：Air pressure when Ar, film forming：2mTorr, Ar throughput：20sccm.
Gate insulating film 3 utilizes plasma CVD method, uses carrier gas：SiH4And N2O mixed gas and film forming.In detail and In speech, the present embodiment, 8 inches of circular electrodes (area 314cm is used2) as the electrode of CVD device, change by table 1 Suo Shi Temperature, power, the flow-rate ratio of above-mentioned gas (volume ratio) during film forming and by the film forming of gate insulating film 3 of individual layer.Air pressure is set to 133Pa (constant) (being not illustrated in table).
Then, for the oxide semiconductor layer (thickness 40nm) of the composition shown in table 1, using according to the oxygen can be formed The sputtering target that the mode of compound film have adjusted, passes through the sputtering film-forming of following conditions.
Sputter equipment：" CS-200 " of Co., Ltd. ULVAC manufactures
Substrate temperature：Room temperature
Air pressure：1mTorr
Partial pressure of oxygen：100×O2/(Ar+O2The volume % of)=4
Film forming power density：2.55W/cm2
Each content of the metallic element of the oxide semiconductor layer obtained in such a way passes through XPS (X-ray Photoelectron Spectroscopy) method analyzed.Specifically, using Ar ion pairs from most surface to 5nm or so Depth scope sputtered after, analyzed by following conditions.It should be noted that the oxidation determined by XPS methods Thing film used on Si substrates by with the forming thin film of above-mentioned same composition be 40nm sample.
X-ray source：Al Kα
X-ray power output：350W
Photoelectron exit angle：20°
As described so by after the film forming of oxide semiconductor layer 4, patterned by photoetching and wet etching.As wet Etching solution, has been used " ITO-07N " of the Northeast chemistry manufacture as the oxalic acid system wet etch solution of oxide semiconductor.
After oxide semiconductor layer 4 is patterned as described so, in order to improve the film quality of oxide semiconductor layer, carry out Pre-anneal treatment.Pre-anneal treatment is in vapor, carried out 60 minutes under atmospheric pressure, with 350 DEG C.
Then, in order to protect the surface of oxide semiconductor layer 4, formed and include SiO2(the thickness of etch stop layer 9 100nm).Specifically, " PD-220NL " manufactured using Samco companies, utilizes plasma CVD method film forming.In this implementation In example, the N diluted using nitrogen is used2O and SiH4Mixed gas as carrier gas, film forming under the following conditions.
Film-forming temperature：230℃
Air pressure：133Pa
Film forming power density：1.1W/cm2
SiH4/N2O flow-rate ratio (volume ratio)：0.04
For the etch stop layer 9 formed in such a way, in order to connect oxide semiconductor layer 4 and source-drain electrode 5, After photoetching is carried out, by reactive ion etching method (RIE), the patterning of electrode formation is carried out.
Then, using pure Mo, DC sputtering methods formation source-drain electrode 5 is passed through.Specifically, it is same with foregoing gate electrode Ground, by source-drain electrode with after Mo forming thin films (thickness is 100nm), the patterning of source-drain electrode is carried out by photoetching.
Formed in such a way after source-drain electrode 5, in order to protect oxide semiconductor layer 4, form diaphragm 6.It is used as guarantor Cuticula 6, uses SiO2(thickness 100nm) and SiN (thickness 150nm) stacked film (total thickness 250nm).Above-mentioned SiO2And SiN Formation " PD-220NL " that is manufactured using Samco companies, carried out using plasma CVD method.In the present embodiment, shape successively Into SiO2Film and SiN film.In SiO2N is used in the formation of film2O and SiH4Mixed gas, used in the formation of SiN film SiH4、N2、NH3Mixed gas.In either case, film forming power density is 0.32W/cm2, film-forming temperature is 150 ℃。
Then, by photoetching and dry ecthing, the contact tested for transistor characteristic evaluation is formed in diaphragm 6 Hole, so as to obtain Fig. 1 TFT.
For each TFT obtained in such a way, stress tolerance is evaluated in the following manner.
(1) evaluation of the stress tolerance (NBTS) of back bias voltage is applied
In the present embodiment, the stress for carrying out applying gate electrode back bias voltage applies experiment.It is as follows that stress applies condition.
Source voltage：0V
Drain voltage：10V
Gate voltage：-20V
Substrate temperature：60℃
Stress application time：2 hours
In the present embodiment, the change value of the threshold voltage when stress of 2 hours is applied is used as threshold voltage shift amount Δ Vth, using Δ Vth ＜ 5.0V situation as qualified in NBTS.
(2) evaluation of the stress tolerance (LNBTS) of light irradiation+application back bias voltage
In the present embodiment, the environment (stress) during actual liquid crystal panel driving is simulated, side is carried out to sample irradiation light The stress that (white light) side is continuously applied back bias voltage to gate electrode applies experiment.It is as follows that stress applies condition.Light source analogy liquid crystal The backlight of display and used White LED.
Source voltage：0V
Drain voltage：10V
Gate voltage：-20V
Substrate temperature：60℃
Stress application time：2 hours
Light source：White LED (the LED LXHL-PW01 of PHILIPS companies manufacture) 25000nit
In the present embodiment, the change value of the threshold voltage when stress of 2 hours is applied is used as threshold voltage shift amount Δ Vth, using the situation of the Δ Vth ＜ 5.0V in LNBTS as qualified.
(3) measure of SS values
SS values be make leakage current increase by 1 digit magnitude required for gate voltage minimum value.In the present embodiment, determine into SS values during stress test (LNBTS) of row above-mentioned (2), using SS value ＜ 0.55V/decade situation as qualified.
(4) measure of on state current (Δ Ion)
On state current (Δ Ion) refers to, the leakage current and transistor that gate voltage is 30V be on-state when electric current Value.In the present embodiment, the on state current before and after the stress test (LNBTS) of above-mentioned (2) is determined respectively, before stress test Afterwards, its variation delta Ion (absolute value) be less than 10% situation as qualified (A), more than 10% situation as unqualified (B)。
These results, which collect, to be shown in Table 1.Gas flow ratio (volume ratio) in each table is by N2O is set to SiH when 1004 The ratio between.
It should be noted that the most right column in each table sets " judgement " column, " A " is accompanied by meet all above-mentioned characteristics, It is unsatisfactory for being accompanied by " B " for any one characteristic.
[table 1]
It can be analyzed as follows by table 1.
IZTO is shown with table 1 as oxide semiconductor layer, changes the ratio and gate insulating film of each metallic element Membrance casting condition (temperature, film forming power density, gas flow ratio) when result.
As a result, temperature control during gate insulating film film forming is existed more than 250 DEG C, by the control of film forming power density 0.7W/cm2Above, by gas flow ratio (SiH4/N2O) No.1~4 of the control below 0.04,6,10~13,15,18~21, In 25~28, the hydrogen concentration in gate insulating film is reduced to prescribed limit, therefore has obtained good under any stress test Good characteristic.In addition, their mobility is 6cm2/ more than Vs high (result of mobility is not illustrated in table).
On the other hand, when some of above-mentioned condition during gate insulating film film forming is unsatisfactory for the optimum condition of the present invention, All desired characteristics (stress tolerance) (No.5,7~9,14,16,17,22~24,29~31) can not be had concurrently.
Embodiment 2
The TFT (gate insulating film 3 is two layers) shown in Fig. 1 is made in the following manner, and evaluates stress tolerance etc..But It is, in the present embodiment, Fig. 1 non-film forming of nesa coating 8.
First, similarly to Example 1, on glass substrate 1,100nm Mo forming thin films are regard as gate electrode 2.
On the gate electrode 2, first using SiN film film forming as lower floor gate electrode side gate insulating film 3, then, at it On by SiO2Film film forming as upper strata oxide semiconductor layer side gate insulating film 3.
The gate insulating film 3 on lower floor and upper strata utilizes plasma CVD method, uses 8 inches of circular electrode (area 314cm2) it is used as the electrode progress film forming of CVD device.Specifically, during the gate insulating film 3 of lower floor is formed, make Use carrier gas：SiH4、N2And NH3Mixed gas, set SiH4/N2Gas flow：304sccm、NH3Gas flow：100sccm、 N2Gas flow：48sccm, with film forming power density：100W(0.32W/cm2) film forming.On the other hand, the grid on upper strata is being formed During dielectric film 3, carrier gas is used：SiH4And N2O mixed gas, sets SiH4/N2Gas (uses N2Gas is by SiH4Gas It is diluted to 10 volume % gas) flow：22sccm(SiH4The flow of gas be 2sccm), N2O gas flows：100sccm, with Film forming power density：300W(0.96W/cm2) film forming.During any film forming in lower floor and upper strata, temperature be set to 320 DEG C it is (permanent It is fixed), air pressure is set to 200Pa (constant).Hydrogen amount and thickness in the gate insulating film of formation are shown in Table 2.
Then, using the sputtering target after being adjusted in the way of it can form the sull, following conditions are passed through Sputtering method, on the gate insulating film 3 on upper strata, by oxide semiconductor layer (thickness 40nm) film forming of the composition shown in table 2.
Sputter equipment：" CS-200 " of ULVAC companies of Co., Ltd. manufacture
Substrate temperature：Room temperature
Air pressure：1mTorr
Partial pressure of oxygen：100×O2/(Ar+O2The volume % of)=4
Film forming power density：2.55W/cm2
In a manner described by after the film forming of oxide semiconductor layer 4, similarly to Example 1, entered by photoetching and wet etching Row patterning, then, in order to improve the film quality of oxide semiconductor layer, carries out pre-anneal treatment.
Then, similarly to Example 1, in order to protect the surface of oxide semiconductor layer 4, formed and include SiO2Etching Barrier layer 9 (thickness 100nm), sequentially for the etch stop layer 9 of formation, in order to connect oxide semiconductor layer 4 and source-electric leakage Pole 5, after photoetching is carried out, the patterning of electrode formation is carried out by reactive ion etching method (RIE).
Then, similarly to Example 1, using pure Mo, by DC sputtering methods formation source-drain electrode 5, then, in order to protect Protect oxide semiconductor layer 4 and form diaphragm 6.
Then, similarly to Example 1, by photoetching and dry ecthing, formed and commented for transistor characteristic in diaphragm 6 The contact hole of valency test, so as to obtain Fig. 1 TFT.
For each TFT obtained in such a way, stress tolerance is evaluated similarly to Example 1.
[table 2]
It can be analyzed as follows by table 2.
Show gate insulating film 3 being set to SiN film layer and SiO in table 22Two layers of film layer, and when changing two layers of ratio Result.
Generally, SiO2Film is fine and close and embodies good characteristic, but film forming speed is slowly and with infringement productivity ratio Tendency, on the other hand, SiN film has compactness poor but the fast property of film forming speed.According to table 2, confirm SiN film relative to SiO2Even if the thickness thickness of film arrives SiO2Film: SiN film=1: 24 ratio (No.2), it can also obtain good under stress test Characteristic.
Symbol description
1 substrate
2 gate electrodes
3 gate insulating films
4 oxide semiconductor layers
5 sources-drain electrode
6 diaphragms (dielectric film)
7 contact holes
8 nesa coatings
9 etch stop layers

Claims (3)

1. a kind of thin film transistor (TFT), it is characterised in that be possess gate electrode, for channel layer individual layer oxide semiconductor Layer, the etch stop layer on surface for protecting oxide semiconductor layer, source-drain electrode and be configured at gate electrode and channel layer it Between gate insulating film thin film transistor (TFT), wherein,
The metallic element for constituting the oxide semiconductor layer is made up of In, Zn and Sn, and
The gate insulating film directly contacted with the oxide semiconductor layer is silicon oxide layer, and hydrogen concentration therein is controlled In below the atom % of more than 0.667 atom % 4,
By each metallic element relative to all metallic elements except oxygen content respectively with atom % be set to [In], [Zn] and When [Sn], the oxide semiconductor layer meets following relation：
15≤[In]≤35、50≤[Zn]≤60、18.3≤[Sn]≤30。
2. thin film transistor (TFT) as claimed in claim 1, wherein,
The gate insulating film has the stepped construction of single layer structure or more than two layers,
In the case of with the stepped construction, the hydrogen concentration in the layer directly contacted with the oxide semiconductor layer is controlled System is in below 4 atom %.
3. a kind of display device, it possesses the thin film transistor (TFT) described in claim 1 or 2.
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