CN104601147A - Fixed-cycle random tiny negative pulse generation circuit - Google Patents
Fixed-cycle random tiny negative pulse generation circuit Download PDFInfo
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- CN104601147A CN104601147A CN201510064531.1A CN201510064531A CN104601147A CN 104601147 A CN104601147 A CN 104601147A CN 201510064531 A CN201510064531 A CN 201510064531A CN 104601147 A CN104601147 A CN 104601147A
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- random
- negative pulse
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/01—Shaping pulses
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Abstract
The invention relates to a fixed-cycle random tiny negative pulse generation circuit mainly comprising a timing module, a random number module, a shaping filtering module and a numerical control attenuation module connected in sequence. The timing module is used for outputting a clock signal; the random number module receives the clock signal and outputs a fixed-cycle random sequence; the shaping filtering module outputs a negative pulse signal after the random sequence passes through a multi-stage capacitance shaping and clamping diode circuit; the negative pulse signal is subjected to amplitude control via the numerical control attenuation module, and a fixed-cycle random tiny negative pulse signal is outputted. The circuit is simple in design, high in sampling sensitivity, massively integratable and capable of generating multichannel signals.
Description
Technical field
The invention belongs to tiny signal source circuit design field, be specifically related to the random small negative pulse of a kind of fixed cycle and produce circuit.
Background technology
Pulse signal is as a kind of conventional test and excitation signal, be widely used in the fields such as communication, medical treatment, Industry Control, electronic measurements, power control and conversion, such as, in the system such as radar detection, electronic countermeasures, to need with the rising edge of pulse signal and trailing edge, as triggering signal, to be applied to the system testing of acquisition system.
Recent years, the technical fields such as photon-electron input, Radar Signal Detection are fast-developing, the signal of telecommunication that detector in this type of event produces generally all has that amplitude is weak, frequency is high, the cycle is fixed but the common trait such as signal is random, the detector detected for completing this type of generally forms by much organizing probe unit, and detector is difficult to work long hours at normal temperatures and pressures, omnidistancely cannot participate in system integration test, therefore to complete the demarcation of rear end acquisition channel, the pulse generating equipment identical with detector output signal must be designed.
For the simulation of this type of signal, way comparatively conventional at present has:
1. adopt AWG (Arbitrary Waveform Generator) to export, mostly price is high for this kind of pulse generator, and function is complicated, and volume is comparatively large and be not suitable for the application scenario of hand-held, portable equipment or limited space, can not possess tens generators and carry out test system and test;
2. use programmable logic device and high speed D/A to export, this type of DA complex circuit designs, the signal of generation is narrower, and requires that DA operating frequency is higher, and power consumption is very large, realize difficulty, and cost is high, is not easy to a large amount of use;
3. adopt the mode of special DDS integrated chip design: the mode that its and high speed D/A design is similar, the signal period and amplitude sensitivity higher, but high to device speed characteristic requirements, device purchase and use cost high, be not easy to a large amount of use.
Summary of the invention
The object of the invention is the random small negative pulse of a kind of fixed cycle that is complicated for said method design, the proposition of high in cost of production technical problem and produce circuit, this circuit design is simple, sampling sensitivity is high, circuit area is little, can be integrated in a large number, and the generation of multiple signals can be realized.
In order to achieve the above object, the present invention proposes the random small negative pulse of a kind of fixed cycle and produces circuit, mainly comprise time block, random number module, shaping filter module and numerical control attenuation module, each module connects in turn: time block is for generation of stable clock signal, and transfer to random number module, clock signal is carried out randomization by random number module, export the random sequence of fixed cycle, shaping filter module by random sequence by multistage electric capacity shaping, after high speed diode clamp circuit, export undersuing, numerical control attenuation module carries out amplitude control to undersuing, export the random small undersuing of fixed cycle.
Preferably, described time block comprises two-way clock signal generating circuit, wherein a road comprises SE555 timer generation circuit, another road comprises high steady clock input, after the time threshold control end of described timer is connected with trigger end, be connected to current input terminal (DISC) by resistance (R2), current input terminal (DISC) is connected with power supply by slide rheostat (R1), and trigger end is by the first storage capacitor (C1) ground connection.
Preferably, the power end (VCC) of described timer be connected the first decoupling capacitor (C6) between ground, timer voltage-regulation end (CV) is by the second storage capacitor (C2) ground connection.
Preferably, described random number module comprises random number chips W NG-8, its output enable end (OE) is by the first pull down resistor (R3) ground connection, chip power end (Vdd) connects power supply by the first pull-up resistor (R4), and output pin (DATA) is connected with the input of shaping filter module.
Preferably, described shaping filter module comprises first order capacitance (C3), second level capacitance (C4), second pull-up resistor (R5), second pull down resistor (R6) and clamp diode (V1), one end of first order capacitance is connected with the output pin (DATA) of random number module, the other end connects power supply respectively by the second pull-up resistor (R5), by the second pull down resistor (R6) ground connection, by clamp diode (V1) ground connection, and be connected with the second capacitance (C4), the other end of the second capacitance (C4) connects power supply by the 3rd pull-up resistor (R7), and be connected with the input of numerical control attenuation module.
Preferably, described numerical control attenuation module comprises HMC472LP4 numerical-control attenuator (D3), the 3rd capacitance (C5), 4th capacitance (C7), undersuing is after the 3rd capacitance (C5), the input pin (RF1) of input numerical-control attenuator (D3), the amplitude control pin (V1 ~ V6) of numerical-control attenuator (D3) connects power supply, 6 line toggle switch ground connection respectively by the 8 line row groups (RN1) of 4.7K Ω.
Preferably, described one end of 4th capacitance (C7) is connected with the output (RF2) of attenuator (D3), and the other end is connected to by the resistance (R8) of 49.9 Ω and exports SMA connector (X3), exports the random small undersuing of fixed cycle.
Compared with prior art, advantage of the present invention and good effect are:
This circuit is in order to the generation of analog pulse signal, adopt timer clock signal, through random number module, export the random sequence of fixed cycle, random sequence is through the process such as multistage electric capacity shaping, high speed diode be clamped, be shaped as the random undersuing of fixed cycle, the random small undersuing of the controllable fixed cycle of undersuing numerical-control attenuator amplitude output signal, circuit design is simple, cost is low, sampling sensitivity is high, circuit area is little, can be integrated in a large number, and the generation of multiple signals can be realized.
Accompanying drawing explanation
Fig. 1 is that the random small negative pulse of a kind of fixed cycle produces each model calling block diagram of circuit;
Fig. 2 is circuit each point signal waveform;
Fig. 3 is that the random small undersuing of a kind of fixed cycle produces circuit theory diagrams.
Embodiment
The invention provides the random small negative pulse of a kind of fixed cycle and produce circuit, below in conjunction with accompanying drawing, the present invention is described further.
As shown in Figure 1, for circuit module provided by the present invention connects block diagram, mainly comprise: time block, random number module, shaping filter module and numerical control attenuation module, the clock signal A of time block stable output; Clock signal A is by exporting the random sequence B of fixed cycle after random number module; Random sequence B exports the random undersuing C of fixed cycle by shaping filter module; Undersuing C carries out amplitude control through numerical control attenuation module, and export the random small undersuing D of fixed cycle, wherein, the signal waveform of each main point of circuit as shown in Figure 2.
Fig. 3 is the principle design figure that the random small negative pulse of a kind of fixed cycle produces circuit, time block wherein comprises two-way clock signal generating circuit, wherein a road comprises SE555 timer generation circuit, another road comprises high steady clock input, when the no requirement (NR) of multichannel synchronousness, select SE555 timer clocking, when multichannel require signal complete synchronous time, select outer for high steady clock, the present embodiment selects the high steady clock of GS20, by the input of input SMA connector, function admirable, reliability are high, in order to ensure the synchronousness exporting pulse.
Timer internal (D1) SE555 is typical timing chip, and timer current input terminal (DISC) is connected with+5V power supply by slide rheostat (R1); 5.1K resistance (R2) is connected between current input terminal (DISC) with Timer Threshold end (TH); Short circuit between Timer Threshold end (TH) and trigger end (TR), and by the first storage capacitor (C1) ground connection.The timing cycle of timer is determined by the size of slide rheostat (R1), resistance (R2) and the first storage capacitor (C1), the capacitance of the first storage capacitor (C1) is 0.1uF, the cycle of clock signal is only regulated by slide rheostat (R1) to be determined, clock cycle calculated relationship is: ((R1+2*R2) * C1)/1.49.
For ensureing that chip normally exports, make output clock more stable, timer power supply end (VCC) and output reset terminal (RST) connect+5V power supply, and timer ground end (GND) connects signal ground, the decoupling capacitor (C6) of the indirect 0.1uF on supply pin and ground; Timer voltage-regulation end (CV) is by the second storage capacitor (C2) the ground connection energy storage of 0.01uF, and the steady clock of height of clock and outside input that timer exports (OUT) is connected on 1,3 pin of wire jumper (X2) respectively; When internal clocking selected by needs, emit 1,2 pin of tie jumper with wire jumper; When external clock selected by needs, with 2,3 pin of jumper cap tie jumper, complete inside and outside clock selecting.
The clock end (CLK) of clock signal input random number chip (D2) after selection carries out randomization, randomization chip selection WNG-8 chip, this chip is a digital physical noise source chip, for generation of true random number sequence, it is indispensable device in information security and password product.Random number chip output enable end (OE) is by the first pull down resistor (R3) ground connection of 4.7K, ensure that chip normally exports, chip power end (Vdd) connects+5V power supply by first pull-up resistor (R4) of 100 Ω, chip dormancy control end (INH) and two NC pins (2 pin, 3 pin) unsettled, random sequence exports shaping filter module to by the output pin (DATA) of random number chip.
Random sequence is after first capacitance (C3) of 100pF, and be shaped as the pulse signal corresponding with random sequence hopping edge, occur positive pulse at the rising edge of Serial No., negative pulse appears in trailing edge.Pulse signal connects+5V power supply by second pull-up resistor (R5) of 1K Ω, by the second pull down resistor (R6) ground connection of 1K Ω, two resistance adds 2.5V direct current biasing to the pulse signal after straight, this bias voltage is greater than the conducting voltage of catching diode (V1), be in conducting state with making diode pair, by pulse signal maximum level clamper at about 0.7V, the high level of pulse signal, bottom positive pulse and negative pulse, wider portion is by all by filtering, output take 0.7V as the undersuing of benchmark, this signal is after second capacitance (C4) of 150pF, power supply is connect again by the 3rd pull-up resistor (R7) of 2K, the edge steep of further raising undersuing, the input (RF1) that signal after pull-up sends into numerical-control attenuator (D3) after the 3rd capacitance (C5) of 22pF carries out signal amplitude control.
The present embodiment numerical-control attenuator (D3) selects HMC472LP4 numerical-control attenuator to carry out control signal amplitude, and this attenuator conducting bandwidth is 0 ~ 3G, can meet high speed tiny signal conducting requirement, attenuator can realize the numerical control attenuation of 0.5dB ~ 31.5dB, attenuation amplitude is by amplitude control pin (V1 ~ V6 pin) Automatic level control of attenuator, when control level is low, this grade of decay is enable, wherein, V1 decays 16dB, V2 decays 8dB, V3 decays 4dB, V4 decays 2dB, V5 decays 1dB, V6 decays 0.5dB, overall attenuation is enable attenuation sum, the amplitude control pin (V1 ~ V6) of attenuator connects+5V power supply respectively by the 8 line row groups (RN1) of 4.7K Ω, by 6 line toggle switch ground connection, when the amplitude control bit that toggle switch is corresponding pushes ground, corresponding decay position is enable, when toggle switch disconnects with ground, lost efficacy in corresponding decay position, the amplitude therefore outputed signal can be controlled by toggle switch flexibly, and it is convenient to implement.
By 330pF electric capacity (C9) ground connection after pin ACG1 ~ ACG4 short circuit of attenuator electric capacity, capacitor pin ACG5, ACG6, ACG7 is respectively by a 330pF electric capacity (C10, C11, C12) ground connection, attenuator power end (VDD) connects+5V power supply, ground end (GND) ground connection, hot weld dish (NC1 ~ NC8) ground connection, between power end (VDD) and lower margin, cross-over connection 1000pF's removes lotus root electric capacity (C8), signal after numerical-control attenuator is exported by output (RF2), undertaken every directly by the 4th capacitance (C7) of 1000pF after signal exports, signal after straight is connected in series 49.9 Ω resistance (R8) and is connected to and exports SMA connector (X3), ensure that circuit output impedance is 50 Ω.
Circuit in the present embodiment is through demonstration, principle design and circuit simulation, simulation results show circuit design is feasible, finally produce circuit board, carry out circuit design verification, circuit is through carefully debugging, debug results shows: the pulse signal frequency that circuit produces can be established, pulse duration 2ns, signal trailing edge is less than 1ns, and rising edge is less than 2ns, and signal amplitude 5 ~ 200mV can establish, circuit noise controls good, good in signal output waveform, circuit noise level is lower than 2mV, and debug results proves that circuit design thinking is reasonable, method is feasible.
The above; it is only preferred embodiment of the present invention; it is not restriction the present invention being made to other form; the Equivalent embodiments that any those skilled in the art may utilize the technology contents of above-mentioned announcement to be changed or be modified as equivalent variations is applied to other field; but everyly do not depart from technical solution of the present invention content; according to any simple modification, equivalent variations and remodeling that technical spirit of the present invention is done above embodiment, still belong to the protection range of technical solution of the present invention.
Claims (7)
1. the random small negative pulse of fixed cycle produces a circuit, it is characterized in that, comprising:
Time block, for generation of stable clock signal;
Random number module, carries out randomization by above-mentioned clock signal, exports the random sequence of fixed cycle;
Shaping filter module, receives above-mentioned random sequence and carries out shaping filter process, exports undersuing;
Numerical control attenuation module, carries out amplitude control by above-mentioned undersuing, exports the random small undersuing of fixed cycle.
2. the random small negative pulse of a kind of fixed cycle according to claim 1 produces circuit, it is characterized in that: described time block comprises two-way clock signal generating circuit, wherein a road comprises SE555 timer generation circuit, another road comprises high steady clock input, after the time threshold control end of described timer is connected with trigger end, current input terminal (DISC) is connected to by resistance (R2), current input terminal (DISC) is connected with power supply by slide rheostat (R1), and trigger end is by the first storage capacitor (C1) ground connection.
3. the random small negative pulse of a kind of fixed cycle according to claim 2 produces circuit, it is characterized in that: the power end (VCC) of described timer be connected the first decoupling capacitor (C6) between ground, timer voltage-regulation end (CV) is by the second storage capacitor (C2) ground connection.
4. the random small negative pulse of a kind of fixed cycle according to claim 1 produces circuit, it is characterized in that: described random number module comprises random number chips W NG-8, its output enable end (OE) is by the first pull down resistor (R3) ground connection, chip power end (Vdd) connects power supply by the first pull-up resistor (R4), and output pin (DATA) is connected with the input of shaping filter module.
5. the random small negative pulse of a kind of fixed cycle according to claim 1 produces circuit, it is characterized in that: described shaping filter module comprises first order capacitance (C3), second level capacitance (C4), second pull-up resistor (R5), second pull down resistor (R6) and clamp diode (V1), one end of first order capacitance is connected with the output pin (DATA) of random number module, the other end connects power supply respectively by the second pull-up resistor (R5), by the second pull down resistor (R6) ground connection, by clamp diode (V1) ground connection, and be connected with the second capacitance (C4), the other end of the second capacitance (C4) connects power supply by the 3rd pull-up resistor (R7), and be connected with the input of numerical control attenuation module.
6. the random small negative pulse of a kind of fixed cycle according to claim 1 produces circuit, it is characterized in that: described numerical control attenuation module comprises HMC472LP4 numerical-control attenuator (D3), the 3rd capacitance (C5), 4th capacitance (C7), undersuing is after the 3rd capacitance (C5), the input pin (RF1) of input numerical-control attenuator (D3), the amplitude control pin (V1 ~ V6) of numerical-control attenuator (D3) connects power supply, 6 line toggle switch ground connection respectively by the 8 line row groups (RN1) of 4.7K Ω.
7. the random small negative pulse of a kind of fixed cycle according to claim 6 produces circuit, it is characterized in that: described one end of 4th capacitance (C7) is connected with the output (RF2) of attenuator (D3), the other end is connected to by the resistance (R8) of 49.9 Ω and exports SMA connector (X3), exports the random small undersuing of fixed cycle.
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| CN201510064531.1A CN104601147B (en) | 2015-02-09 | 2015-02-09 | A kind of random small negative pulse of fixed cycle produces circuit |
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| CN201510064531.1A CN104601147B (en) | 2015-02-09 | 2015-02-09 | A kind of random small negative pulse of fixed cycle produces circuit |
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| CN104601147A true CN104601147A (en) | 2015-05-06 |
| CN104601147B CN104601147B (en) | 2017-04-05 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105929890A (en) * | 2016-04-15 | 2016-09-07 | 福建联迪商用设备有限公司 | Electronic device as well as clock signal generation circuit and method |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4296384A (en) * | 1978-09-20 | 1981-10-20 | Kabushiki Kaisha Kawai Gakki Seisakusho | Noise generator |
| JP3364365B2 (en) * | 1995-07-27 | 2003-01-08 | 池上通信機株式会社 | Probability setting device for random pulse generator |
| CN101308388A (en) * | 2008-06-30 | 2008-11-19 | 中国兵器工业第二〇五研究所 | Self-restoration control circuit for photoelectric tracking instrument pitching device entering spacing zone |
| CN103630943A (en) * | 2013-02-08 | 2014-03-12 | 中国科学院电子学研究所 | Method and system for detecting thickness of lunar soil and subsurface geological structure of moon |
-
2015
- 2015-02-09 CN CN201510064531.1A patent/CN104601147B/en not_active Expired - Fee Related
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4296384A (en) * | 1978-09-20 | 1981-10-20 | Kabushiki Kaisha Kawai Gakki Seisakusho | Noise generator |
| JP3364365B2 (en) * | 1995-07-27 | 2003-01-08 | 池上通信機株式会社 | Probability setting device for random pulse generator |
| CN101308388A (en) * | 2008-06-30 | 2008-11-19 | 中国兵器工业第二〇五研究所 | Self-restoration control circuit for photoelectric tracking instrument pitching device entering spacing zone |
| CN103630943A (en) * | 2013-02-08 | 2014-03-12 | 中国科学院电子学研究所 | Method and system for detecting thickness of lunar soil and subsurface geological structure of moon |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105929890A (en) * | 2016-04-15 | 2016-09-07 | 福建联迪商用设备有限公司 | Electronic device as well as clock signal generation circuit and method |
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| CN104601147B (en) | 2017-04-05 |
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