CN106452423A - Relay driving chip and electric meter - Google Patents
Relay driving chip and electric meter Download PDFInfo
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- CN106452423A CN106452423A CN201611154569.9A CN201611154569A CN106452423A CN 106452423 A CN106452423 A CN 106452423A CN 201611154569 A CN201611154569 A CN 201611154569A CN 106452423 A CN106452423 A CN 106452423A
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- 230000002093 peripheral effect Effects 0.000 description 3
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Classifications
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0175—Coupling arrangements; Interface arrangements
- H03K19/018—Coupling arrangements; Interface arrangements using bipolar transistors only
- H03K19/01806—Interface arrangements
Abstract
The invention discloses a relay driving chip and an electric meter. The relay driving chip comprises an IO input pin, a first relay control output pin and a second relay control output pin; the relay driving chip further comprises a combinational logic circuit; and an input end of the combinational logic circuit is connected with the IO input pin, a first output end of the combinational logic circuit is connected with the first relay control output pin, and a second output end of the combinational logic circuit is connected with the second relay control output pin. According to the relay driving chip disclosed by the invention, relay pull-in control can be realized by using one IO port, thereby saving the IO port resources of an MCU and facilitating the function expansion in the electric meter; and the relay driving chip disclosed by the invention has a higher integration level, replaces the existing relay control circuit, and can reduce elements, reduce the design difficulty, lower the cost and decrease the board layout area.
Description
Technical field
The invention belongs to instrument and meter control field, more particularly to a kind of relay driving chip and ammeter.
Background technology
Current ammeter is in the schematic block diagram using existing control relay circuit control relay as shown in figure 1, MCU
2 I/O ports of (micro-control unit) 11 export two IO control signals IO-1 and IO-2 respectively, two IO control signals IO-1
Two pulse signals OA and OB, two pulse signals OA and OB input is exported with IO-2 through the control relay circuit 12
To relay 13, the control to relay 13 is realized.The I/O port quantity of MCU itself is natively extremely limited, and this relay
Device control circuit must tie up 2 I/O ports of MCU again so that the originally relatively more nervous I/O resource in ammeter Central Plains is more nervous, pole
The earth effect Function Extension of ammeter.
Also, how existing control relay circuit is made up of audion, resistance, electric capacity, the element of employing is more, design
Complex, element cost is higher.And to also result in the area of PCB (printed circuit board) plate fabric swatch element big more, occupies electricity
Limited space in table, increased the difficulty of the arrangement space in design ammeter.
Content of the invention
The technical problem to be solved in the present invention be in order to overcome the control of prior art repeat circuit to need to take 2 of MCU
I/O port causes the I/O resource anxiety in ammeter and control relay circuit element is many, design is complicated, the defect of high cost, provides one
Plant relay driving chip and ammeter.
The present invention is to solve above-mentioned technical problem by the following technical programs：
The present invention provides a kind of relay driving chip, and the relay driving chip includes：IO input pin, first are continued
Electrical equipment control output pin and the second Control output pin；
The relay driving chip also includes：Combinational logic circuit, the combinational logic circuit is preset with IO control letter
Number with the first control signal and the corresponding relation of the second control signal；
The input of the combinational logic circuit is connected with the IO input pin, and the first of the combinational logic circuit is defeated
Go out end to be connected with the first Control output pin, the second outfan of the combinational logic circuit is continued with described second
Electrical equipment control output pin connects；
The IO input pin is used for receiving the IO control signal of outside input, and by the IO control signal of reception transmit to
The input of the combinational logic circuit；
The combinational logic circuit is used for recognizing the IO control signal for receiving, and according to the corresponding relation by the combination
First outfan of logic circuit exports first control signal corresponding with the IO control signal for receiving to first relay
Control output pin, by the second outfan output of the combinational logic circuit second control corresponding with the IO control signal for receiving
Signal processed is to the second Control output pin.
This programme can just complete to control relay drawing only with 1 I/O port, save the I/O port resource of MCU, be easy to
Function Extension in ammeter；Also, relay driving chip integration is higher, replace existing control relay circuit so as to
Element can be reduced, reduce design difficulty, reduces cost, reduction cloth plate suqare.
It is preferred that the combinational logic circuit includes：RC oscillating circuit and logic control circuit, the RC oscillating circuit
Outfan is connected with the first input end of the logic control circuit, the second input of the logic control circuit and the IO
Input pin connects, and the first outfan of the combinational logic circuit is connected with the first Control output pin, institute
The second outfan for stating combinational logic circuit is connected with the second Control output pin；
The RC oscillating circuit is used for producing clock source；
The logic control circuit is used for the IO control signal for receiving using the clock source and intervalometer timing acquisition
Pulsewidth length simultaneously judges by the pulse length whether the IO control signal for receiving is useful signal, to being judged as effective letter
Number IO control signal be combined logical judgment according to the default corresponding relation, by the first of the combinational logic circuit
Outfan exports first control signal corresponding with the IO control signal for being judged as useful signal to first Control
Output pin, by the second outfan output of the combinational logic circuit second control letter corresponding with the IO control signal of identification
Number to the second Control output pin.
It is preferred that the logic control circuit is additionally operable to the pulsewidth length of low and high level in the IO control signal by reception
Ratio come judge receive IO control signal whether be useful signal.
This programme can make up the clock error that may be present of RC oscillating circuit generation, it is ensured that the identification of IO control signal
Accuracy.
It is preferred that the relay driving chip also includes：Power input pin and ground pin；
The power input pin is used for connecting power supply, and the ground pin is used for being grounded.
It is preferred that the relay driving chip also includes：Input protection circuit, the input protection circuit includes：
PMOS, first resistor and second resistance；
The IO input pin is connected with the drain electrode of the PMOS by the first resistor, the source electrode of the PMOS
It is connected with the power input pin, the substrate of the PMOS is connected with the grid of the PMOS；
The IO input pin is grounded also by the second resistance.
This programme increased input protection circuit between IO input pin and combinational logic circuit, can protect ESD, keep away
Exempt from internal circuit damage.
It is preferred that the relay driving chip also includes：Output driving circuit；
The first input end of the output driving circuit is connected with the first outfan of the combinational logic circuit, described defeated
Second outfan of the second input and the combinational logic circuit that go out drive circuit is connected, and the of the output driving circuit
One outfan is connected with the first Control output pin, the second outfan of the output driving circuit and described
Two Control output pins connect.
It is preferred that the output driving circuit includes the first audion, the 11st audion, the 4th audion and the seven or three
Pole pipe；
The relay driving chip also includes：Output protection circuit, the output protection circuit include the first diode,
Second diode, the 3rd diode and the 4th diode；
The positive pole of first diode is connected with the emitter stage of first audion, the negative pole of first diode
It is connected with the colelctor electrode of first audion；
The positive pole of second diode is connected with the emitter stage of the 4th audion, the negative pole of second diode
It is connected with the colelctor electrode of the 4th audion；
The positive pole of the 3rd diode is connected with the emitter stage of the 7th audion, the negative pole of the 3rd diode
It is connected with the colelctor electrode of the 7th audion；
The positive pole of the 4th diode is connected with the emitter stage of the 11st audion, the 4th diode negative
Pole is connected with the colelctor electrode of the 11st audion.
The output protection circuit of the present invention has clamper backward voltage function, and when can prevent the actuating of relay, coil is anti-
To voltage damages internal circuit, while ESD defencive function again.
It is preferred that the output driving circuit also includes：Second audion, the 3rd audion, the 5th audion, the six or three
Pole pipe, the 8th audion, the 9th audion, the tenth audion, 3rd resistor, the 4th resistance, the 5th resistance, the 6th resistance,
Seven resistance, the 8th resistance, the 9th resistance, the tenth resistance, the 11st resistance, the 12nd resistance, the 13rd resistance, the 14th electricity
Resistance, the 15th resistance and the 16th resistance；
The colelctor electrode of first audion is connected with the power input pin, the base stage of first audion and institute
The colelctor electrode connection of the second audion is stated, the base stage of first audion is also by the 6th resistance and the one or three pole
The emitter stage connection of pipe, the emitter stage of first audion is also connected with the colelctor electrode of the 5th audion；
The emitter stage of second audion is connected with the power input pin, and the base stage of second audion passes through
7th resistance is connected with the power input pin, the base stage of second audion also by the 8th resistance respectively with institute
State the emitter stage of the 9th audion and the colelctor electrode connection of the tenth audion；
The colelctor electrode of the 4th audion is connected with the power input pin, the base stage of the 4th audion and institute
The colelctor electrode connection of the 3rd audion is stated, the base stage of the 4th audion is also by the 9th resistance and the four or three pole
The emitter stage connection of pipe, the emitter stage of the 4th audion is also connected with the colelctor electrode of the 9th audion；
The emitter stage of the 3rd audion is connected with the power input pin, and the base stage of the 3rd audion passes through
Tenth resistance is connected with the power input pin, the base stage of the 3rd audion also by the 11st resistance respectively with
The colelctor electrode connection of the emitter stage of the 5th audion and the 6th audion；
First outfan of the base stage of the 6th audion by the 3rd resistor with the combinational logic circuit connects
Connect, the first outfan of the combinational logic circuit is also by the 4th resistance and the 5th resistance and the ground pin
Connection, the base stage of the 6th audion is also connected with the colelctor electrode of the 8th audion, the transmitting of the 6th audion
Pole is connected with the base stage of the 7th audion, the emitter stage of the 6th audion also by the 12nd resistance with described
Ground pin connection；
The base stage of the 5th audion colelctor electrode respectively with the 5th audion, the first relay outlet tube
The colelctor electrode connection of foot and the 7th audion；
The emitter stage of the 7th audion and the ground pin connection；
The emitter stage of the 8th audion and the ground pin connection, the base stage of the 8th audion is by described
16th resistance and the ground pin connection, the base stage of the 8th audion is also by the 15th resistance and described
14 resistance are connected with the base stage of the tenth audion；
The colelctor electrode of the 11st audion also respectively with the second Control output pin and the described 9th
The colelctor electrode connection of audion, the base stage of the 11st audion is connected with the emitter stage of the tenth audion, and described the
The base stage of 11 audions is also by the 13rd resistance and the ground pin connection；
The base stage of the 9th audion is connected with the colelctor electrode of the 9th audion；
The base stage of the tenth audion is also by the 14th resistance and the second Control output pin
Connection, the base stage of the tenth audion is also connected with the colelctor electrode of the 12nd audion；
The base stage of the 12nd audion is by the 5th resistance and the ground pin connection.
The present invention also provides a kind of ammeter, and the ammeter includes that a kind of relay of above-mentioned each optimum condition combination in any drives
Dynamic chip, also includes MCU and relay；
The outfan of the MCU is connected with the IO input pin of the relay driving chip, and the first of the relay
Input is connected with the first Control output pin of the relay driving chip, the second input of the relay
It is connected with the second Control output pin of the relay driving chip.
On the basis of common sense in the field is met, above-mentioned each optimum condition, can combination in any, obtain final product each preferable reality of the present invention
Example.
The positive effect of the present invention is：The present invention can just complete to control relay drawing only with 1 I/O port,
Save the I/O port resource of MCU, the Function Extension being easy in ammeter；Repeat circuit driving chip integrated level of the present invention is higher, takes
For existing control relay circuit so as to element can be reduced, reduce design difficulty, reduces cost, reduction cloth plate suqare.
Description of the drawings
Fig. 1 is the schematic block diagram of existing control relay circuit in background technology.
Fig. 2 is the schematic block diagram of the relay driving chip of the embodiment of the present invention.
Fig. 3 is the circuit diagram of the relay driving chip of the embodiment of the present invention.
Fig. 4 is the use schematic diagram of the relay driving chip of the embodiment of the present invention.
Specific embodiment
The present invention is further illustrated below by the mode of embodiment, but therefore do not limit the present invention to described reality
Apply among a scope.
Embodiment
As Figure 2-3, a kind of relay driving chip includes 5 pins, respectively：IO input pin IO, first are continued
Electrical equipment control output pin OA, the second Control output pin OB, power input pin VCC and ground pin GND.Its
In, the IO input pin IO is used for being connected with MCU；The first Control output pin OA is used for the with relay
One input connects；The second Control output pin OB is used for being connected with the second outfan of relay；The electricity
Source input pin VCC is used for connecting power supply；Ground pin GND is used for being grounded.
The inside of the relay driving chip includes：Input protection circuit 21, combinational logic circuit 22, output driving electricity
Road 23 and output protection circuit 24.Wherein,
The input protection circuit 21 includes：PMOS M1, first resistor R1 and second resistance R2.The IO input pin
IO is connected with the drain electrode of PMOS M1 by first resistor R1, the source electrode of PMOS M1 and the power input
Pin VCC connects, and the substrate of PMOS M1 is connected with the grid of PMOS M1；The IO input pin IO also by
The second resistance R2 ground connection.The input protection circuit 21 of the present embodiment achieves ESD (Electro-static Driven Comb) protection, to being controlled by IO
The ESD of signal input processed is protected, and will not produce damage to internal circuit, while second resistance R2 is drop-down keeps fixing electricity
Flat, improve reliability.
The combinational logic circuit 22 is preset with the corresponding of IO control signal and the first control signal and the second control signal
Relation, i.e., corresponding first control signal of different IO control signals and the second control signal.The combinational logic circuit 22 is wrapped
Include：RC oscillating circuit and logic control circuit, the outfan of the RC oscillating circuit is defeated with the first of the logic control circuit
Enter end connection, the second input of the logic control circuit is connected with the IO input pin IO, the logic control circuit
The first outfan be connected with the first input end of the output driving circuit 23, the output driving circuit 23 first output
End is connected with the first Control output pin OA, and the second outfan of the logic control circuit is driven with the output
The second input connection on galvanic electricity road 23, the second outfan of the output driving circuit 23 is defeated with second Control
Go out pin OB connection.
Specifically, the RC oscillating circuit is used for producing clock source.
The IO input pin IO receives the IO control signal of outside input, will receive IO control signal and export and patrol to described
The second input of control circuit is collected, and the logic control circuit is used for reception being obtained using the clock source and intervalometer timing
IO control signal pulsewidth length and by the pulse length or by receive IO control signal in low and high level arteries and veins
The ratio of wide length come judge receive IO control signal whether be useful signal, wherein, useful signal is referred to default right
The IO control signal of the first corresponding control signal and the second control signal should be set with being related to, conversely, invalid
Signal refers to not be set with the IO control of the first corresponding control signal and the second control signal in default corresponding relation
Signal processed.
The logic control circuit is additionally operable to the IO control signal for being judged as useful signal according to the default correspondence
Relation is combined logical judgment, by the output of the first outfan and the IO for being judged as useful signal of the combinational logic circuit 22
Corresponding first control signal A of control signal is to the output driving circuit 23, defeated by the second of the combinational logic circuit 22
Go out end output second control signal B corresponding with the IO control signal of identification to the output driving circuit 23.
The combinational logic circuit 22 of the present embodiment can accurately recognize IO control signal, filter interference signal.Therein
Logic control circuit can be realized by a digital module.
The output driving circuit 23 includes the first audion Q1, the second audion Q2, the 3rd audion Q3, the four or three pole
Pipe Q4, the 5th audion Q5, the 6th audion Q6, the 7th audion Q7, the 8th audion Q8, the 9th audion Q9, the 13rd
Pole pipe Q10, the 11st audion Q11,3rd resistor R3, the 4th resistance R4, the 5th resistance R5, the 6th resistance R6, the 7th resistance
R7, the 8th resistance R8, the 9th resistance R9, the tenth resistance R10, the 11st resistance R11, the 12nd resistance R12, the 13rd resistance
R13, the 14th resistance R14, the 15th resistance R15 and the 16th resistance R16.
The colelctor electrode of the first audion Q1 is connected with the power input pin VCC, the first audion Q1's
Base stage is connected with the colelctor electrode of the second audion Q2, and the base stage of the first audion Q1 is also by the 6th resistance R6
It is connected with the emitter stage of the first audion Q1, the emitter stage of the first audion Q1 is also with the 5th audion Q5's
Colelctor electrode connects；
The emitter stage of the second audion Q2 is connected with the power input pin VCC, the second audion Q2's
Base stage is connected with the power input pin VCC by the 7th resistance R7, the base stage of the second audion Q2 also by
8th resistance R8 is connected with the emitter stage of the 9th audion Q9 and the colelctor electrode of the tenth audion Q10 respectively；
The colelctor electrode of the 4th audion Q4 is connected with the power input pin VCC, the 4th audion Q4's
Base stage is connected with the colelctor electrode of the 3rd audion Q3, and the base stage of the 4th audion Q4 is also by the 9th resistance R9
It is connected with the emitter stage of the 4th audion Q4, the emitter stage of the 4th audion Q4 is also with the 9th audion Q9's
Colelctor electrode connects；
The emitter stage of the 3rd audion Q3 is connected with the power input pin VCC, the 3rd audion Q3's
Base stage is connected with the power input pin VCC by the tenth resistance R10, the base stage of the 3rd audion Q3 also by
11st resistance R11 is connected with the emitter stage of the 5th audion Q5 and the colelctor electrode of the 6th audion Q6 respectively；
The base stage of the 6th audion Q6 is defeated with the first of the combinational logic circuit 22 by 3rd resistor R3
Go out end connection, the first outfan of the combinational logic circuit 22 also by the 4th resistance R4 and the 5th resistance R5 with
The ground pin GND connection, the base stage of the 6th audion Q6 is also connected with the colelctor electrode of the 8th audion Q8, institute
The emitter stage for stating the 6th audion Q6 is connected with the base stage of the 7th audion Q7, and the emitter stage of the 6th audion Q6 is also
It is connected with ground pin GND by the 12nd resistance R12；
The base stage of the 5th audion Q5 colelctor electrode respectively with the 5th audion Q5, first relay are defeated
Go out the colelctor electrode connection of pin and the 7th audion Q7；
The emitter stage of the 7th audion Q7 is connected with ground pin GND；
The emitter stage of the 8th audion Q8 is connected with ground pin GND, the base stage of the 8th audion Q8
It is connected with ground pin GND by the 16th resistance R16, the base stage of the 8th audion Q8 is also by described
15 resistance R15 and the 14th resistance R14 are connected with the base stage of the tenth audion Q10；
The colelctor electrode of the 11st audion Q11 also respectively with the second Control output pin OB and described
The colelctor electrode connection of the 9th audion Q9, the base stage of the 11st audion Q11 and the emitter stage of the tenth audion Q10
Connection, the base stage of the 11st audion Q11 is connected with ground pin GND also by the 13rd resistance R13；
The base stage of the 9th audion Q9 is connected with the colelctor electrode of the 9th audion Q9；
The base stage of the tenth audion Q10 is defeated with second Control also by the 14th resistance R14
Go out pin OB connection, the base stage of the tenth audion Q10 is also connected with the colelctor electrode of the 12nd audion；
The base stage of the 12nd audion is connected with ground pin GND by the 5th resistance R5.
The first audion Q1 in the output driving circuit 23 of the present embodiment, the 11st audion Q11, the 4th audion Q4
It is large power triode with the 7th audion Q7；Second audion Q2, the 5th audion Q5, the 3rd audion Q3 and the 9th 3 pole
The parameter configuration of pipe Q9 and its peripheral circuit causes above-mentioned 4 audions internal resistance in conducting state relatively low so that the drive of output
Galvanic electricity road is larger, and typical drive current is 400mA, maximum drive current 800mA, the relay that all kinds of intelligent electric meters can be driven to use
Device and DC stepper motor；And the 6th audion Q6, the 8th audion Q8, the tenth audion Q10 and the 12nd audion Q12
And its cooperation of peripheral circuit causes to drive the switching voltage of audion very low, it is only necessary to 1.5V or so, can compatible all kinds of lists
Piece machine.
The output protection circuit 24 includes the first diode, the second diode, the 3rd diode and the 4th diode.
The positive pole of first diode is connected with the emitter stage of the first audion Q1, first diode negative
Pole is connected with the colelctor electrode of the first audion Q1；
The positive pole of second diode is connected with the emitter stage of the 4th audion Q4, second diode negative
Pole is connected with the colelctor electrode of the 4th audion Q4；
The positive pole of the 3rd diode is connected with the emitter stage of the 7th audion Q7, the 3rd diode negative
Pole is connected with the colelctor electrode of the 7th audion Q7；
The positive pole of the 4th diode is connected with the emitter stage of the 11st audion Q11, the 4th diode
Negative pole be connected with the colelctor electrode of the 11st audion Q11.
In the output protection circuit 24 of the present embodiment, the first diode, the second diode, the 3rd diode and the four or two pole
Manage as high speed fly-wheel diode, with clamper backward voltage function, the backward voltage for being prevented from coil during the actuating of relay breaks
Bad internal circuit, adds peripheral circuit and coordinates while there is ESD defencive function.
In the relay driving chip using the present embodiment, it is only necessary to which 1 I/O port of MCU is controlled, and saves MCU
I/O port resource.The combinational logic circuit 22 of wherein relay driving chip can preset following 4 kinds of IO control signals, with control
The state of Control, as shown in Figure 4：
1st, when relay driving built-in chip type pull down resistor keeps normality low level, during normality or when MCU sends out 0, relay
Device driving chip hold mode, is failure to actuate, the first Control output pin OA and the second Control output pin OB
High-impedance state is all exported.
2nd, when MCU sends out 1, i.e., high level, needs to keep high level at least more than 200ms, filters general impulse disturbances, continue
First Control output pin OA of electrical equipment drive chip is often high, and the second Control output pin OB is often low, is used for
Non- magnetic latching relay class is driven to need the device that level type drives, such as power switch relay.
3rd, when MCU sends continuous pulsewidth tms high level, 3tms low level, the assembled pulse signal of 2tms high level, t
Persistent period at least more than 2ms, filtering interference signals.First Control output pin OA of relay driving chip is defeated
Go out the high level of 10 times of tms, the second Control output pin OB exports the low level of 10 times of tms, for driving magnetic to keep
The device of relay class pulsed drive, such as on-load switch relay, or stepper motor etc..
4th, when MCU sends continuous pulsewidth 2tms high level, 3tms low level, the assembled pulse signal of 1tms high level, t
Persistent period at least more than 2ms, filtering interference signals.First Control output pin OA of relay driving chip is defeated
Go out the low level of 10 times of tms, the second Control output pin OB exports the high level of 10 times of tms, for driving magnetic to keep
The device of relay class pulsed drive, such as on-load switch relay, or stepper motor etc..
5th, when other kinds of signal is input into, relay driving chip hold mode, it is failure to actuate, the first Control
Output pin OA and the second Control output pin OB all export high-impedance state.
The relay driving chip of the present embodiment realizes the control of above-mentioned 4 kinds of states using single IO.Due to a numeral
IO only has 0 or 1 two states, and during identification IO control signal, the present embodiment produces clock using RC oscillating circuit
For intervalometer, timing/counting is carried out to pulsewidth, with simple, the advantage of low cost.Due to RC oscillating circuit produce when
Clock is it is possible that the big deficiency of range of error, and the present embodiment need to be only measured in a continuous IO control signal when pulsewidth is surveyed
Low and high level pulsewidth ratio can identify whether IO control signal is useful signal, the such as high level+3tm's of one group of tms
Low level+2tms high level is a useful signal, how many as tms deviation itself, can't affect IO control signal
Identification, it is to avoid clocking error, it is ensured that the accuracy of identification IO control signal.Simultaneously drive the tms that output time is 10 times
Time, as long as the persistent period of t is more than 2ms, drives output time programmable in more than 20ms, all impulse types can be driven
Load relay or stepper motor, or the power switch relay of level-type.
A kind of ammeter of the present embodiment, relay driving chip including the present embodiment, MCU and relay.
The outfan of the MCU is connected with the IO input pin IO of the relay driving chip, and the of the relay
One input is connected with the first Control output pin OA of the relay driving chip, and the second of the relay is defeated
Enter end to be connected with the second Control output pin OB of the relay driving chip.
The outfan output IO control signal of the MCU is to the IO input pin IO, and first Control is defeated
Go out the first input end that pin OA exports corresponding level to the relay, the second Control output pin OB is defeated
Go out the second input of corresponding level to the relay, to drive the relay.
Although the specific embodiment of the present invention is the foregoing described, it will be appreciated by those of skill in the art that these
It is merely illustrative of, protection scope of the present invention is defined by the appended claims.Those skilled in the art is not carrying on the back
On the premise of the principle and essence of the present invention, various changes or modifications can be made to these embodiments, but these change
Protection scope of the present invention is each fallen within modification.
Claims (9)
1. a kind of relay driving chip, it is characterised in that the relay driving chip includes：IO input pin, first are continued
Electrical equipment control output pin and the second Control output pin；
The relay driving chip also includes：Combinational logic circuit, the combinational logic circuit be preset with IO control signal with
First control signal and the corresponding relation of the second control signal；
The input of the combinational logic circuit is connected with the IO input pin, the first outfan of the combinational logic circuit
It is connected with the first Control output pin, the second outfan of the combinational logic circuit and second relay
Control output pin connection；
The IO input pin is used for receiving the IO control signal of outside input, and the IO control signal of reception is transmitted to described
The input of combinational logic circuit；
The combinational logic circuit is used for recognizing the IO control signal for receiving, and according to the corresponding relation by the combination logic
First outfan of circuit exports first control signal corresponding with the IO control signal for receiving to first Control
Output pin, by the second outfan output of the combinational logic circuit second control letter corresponding with the IO control signal for receiving
Number to the second Control output pin.
2. relay driving chip as claimed in claim 1, it is characterised in that the combinational logic circuit includes：RC vibrates
Circuit and logic control circuit, the outfan of the RC oscillating circuit is connected with the first input end of the logic control circuit,
Second input of the logic control circuit is connected with the IO input pin, the first outfan of the combinational logic circuit
It is connected with the first Control output pin, the second outfan of the combinational logic circuit and second relay
Control output pin connection；
The RC oscillating circuit is used for producing clock source；
The logic control circuit is used for obtaining the pulsewidth of the IO control signal for receiving using the clock source and intervalometer timing
Length simultaneously judges by the pulse length whether the IO control signal for receiving is useful signal, to being judged as useful signal
IO control signal is combined logical judgment according to the default corresponding relation, is exported by the first of the combinational logic circuit
Output first control signal corresponding with the IO control signal for being judged as useful signal in end is exported to first Control
Pin, by the second outfan output of the combinational logic circuit second control signal corresponding with the IO control signal of identification extremely
The second Control output pin.
3. relay driving chip as claimed in claim 2, it is characterised in that the logic control circuit is additionally operable to by connecing
In the IO control signal of receipts the ratio of the pulsewidth length of low and high level come judge receive IO control signal whether be useful signal.
4. relay driving chip as claimed in claim 1, it is characterised in that the relay driving chip also includes：Electricity
Source input pin and ground pin；
The power input pin is used for connecting power supply, and the ground pin is used for being grounded.
5. relay driving chip as claimed in claim 4, it is characterised in that the relay driving chip also includes：Defeated
Enter protection circuit, the input protection circuit includes：PMOS, first resistor and second resistance；
The IO input pin is connected with the drain electrode of the PMOS by the first resistor, the source electrode of the PMOS and institute
The connection of power input pin is stated, the substrate of the PMOS is connected with the grid of the PMOS；
The IO input pin is grounded also by the second resistance.
6. relay driving chip as claimed in claim 1, it is characterised in that the relay driving chip also includes：Defeated
Go out drive circuit；
The first input end of the output driving circuit is connected with the first outfan of the combinational logic circuit, and the output is driven
Second input on galvanic electricity road is connected with the second outfan of the combinational logic circuit, and the first of the output driving circuit is defeated
Go out end to be connected with the first Control output pin, the second outfan of the output driving circuit is continued with described second
Electrical equipment control output pin connects.
7. relay driving chip as claimed in claim 6, it is characterised in that the output driving circuit includes the one or three pole
Pipe, the 11st audion, the 4th audion and the 7th audion；
The relay driving chip also includes：Output protection circuit, the output protection circuit include the first diode, second
Diode, the 3rd diode and the 4th diode；
The positive pole of first diode is connected with the emitter stage of first audion, the negative pole of first diode and institute
State the colelctor electrode connection of the first audion；
The positive pole of second diode is connected with the emitter stage of the 4th audion, the negative pole of second diode and institute
State the colelctor electrode connection of the 4th audion；
The positive pole of the 3rd diode is connected with the emitter stage of the 7th audion, the negative pole of the 3rd diode and institute
State the colelctor electrode connection of the 7th audion；
The positive pole of the 4th diode is connected with the emitter stage of the 11st audion, the negative pole of the 4th diode with
The colelctor electrode connection of the 11st audion.
8. relay driving chip as claimed in claim 7, it is characterised in that the output driving circuit also includes：Second
Audion, the 3rd audion, the 5th audion, the 6th audion, the 8th audion, the 9th audion, the tenth audion, the 3rd
Resistance, the 4th resistance, the 5th resistance, the 6th resistance, the 7th resistance, the 8th resistance, the 9th resistance, the tenth resistance, the 11st electricity
Resistance, the 12nd resistance, the 13rd resistance, the 14th resistance, the 15th resistance and the 16th resistance；
The colelctor electrode of first audion is connected with the power input pin, the base stage of first audion and described
The colelctor electrode connection of two audions, the base stage of first audion is also by the 6th resistance and first audion
Emitter stage connects, and the emitter stage of first audion is also connected with the colelctor electrode of the 5th audion；
The emitter stage of second audion is connected with the power input pin, and the base stage of second audion is by described
7th resistance is connected with the power input pin, and the base stage of second audion is also by the 8th resistance respectively with described
The colelctor electrode connection of the emitter stage of nine audions and the tenth audion；
The colelctor electrode of the 4th audion is connected with the power input pin, the base stage of the 4th audion and described
The colelctor electrode connection of three audions, the base stage of the 4th audion is also by the 9th resistance and the 4th audion
Emitter stage connects, and the emitter stage of the 4th audion is also connected with the colelctor electrode of the 9th audion；
The emitter stage of the 3rd audion is connected with the power input pin, and the base stage of the 3rd audion is by described
Tenth resistance is connected with the power input pin, the base stage of the 3rd audion also by the 11st resistance respectively with described
The colelctor electrode connection of the emitter stage of the 5th audion and the 6th audion；
The base stage of the 6th audion is connected with the first outfan of the combinational logic circuit by the 3rd resistor, institute
The first outfan of combinational logic circuit is stated also by the 4th resistance and the 5th resistance and the ground pin connection,
The base stage of the 6th audion is also connected with the colelctor electrode of the 8th audion, the emitter stage of the 6th audion and institute
The base stage connection of the 7th audion is stated, the emitter stage of the 6th audion is also by the 12nd resistance and the ground pipe
Foot connects；
The base stage of the 5th audion colelctor electrode respectively with the 5th audion, the first relay output pin and
The colelctor electrode connection of the 7th audion；
The emitter stage of the 7th audion and the ground pin connection；
The emitter stage of the 8th audion and the ground pin connection, the base stage of the 8th audion passes through the described tenth
Six resistance and the ground pin connection, the base stage of the 8th audion is also by the 15th resistance and the described 14th
Resistance is connected with the base stage of the tenth audion；
The colelctor electrode of the 11st audion also respectively with the second Control output pin and the 9th 3 pole
The colelctor electrode connection of pipe, the base stage of the 11st audion is connected with the emitter stage of the tenth audion, and the described 11st
The base stage of audion is also by the 13rd resistance and the ground pin connection；
The base stage of the 9th audion is connected with the colelctor electrode of the 9th audion；
The base stage of the tenth audion is connected with the second Control output pin also by the 14th resistance,
The base stage of the tenth audion is also connected with the colelctor electrode of the 12nd audion；
The base stage of the 12nd audion is by the 5th resistance and the ground pin connection.
9. a kind of ammeter, it is characterised in that the ammeter includes the relay driving core in claim 1-8 described in any one
Piece, also includes MCU and relay；
The outfan of the MCU is connected with the IO input pin of the relay driving chip, the first input of the relay
End is connected with the first Control output pin of the relay driving chip, the second input of the relay and institute
State the second Control output pin connection of relay driving chip.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201611154569.9A CN106452423B (en) | 2016-12-14 | 2016-12-14 | Relay driving chip and ammeter |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201611154569.9A CN106452423B (en) | 2016-12-14 | 2016-12-14 | Relay driving chip and ammeter |
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| CN106452423B CN106452423B (en) | 2024-03-08 |
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| CN110504955A (en) * | 2019-08-30 | 2019-11-26 | 长虹美菱股份有限公司 | A kind of electric flap driving circuit |
| CN108170054B (en) * | 2017-12-27 | 2023-12-08 | 上海辰竹仪表有限公司 | Intelligent safety relay and application circuit thereof |
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|---|---|
| CN106452423B (en) | 2024-03-08 |
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