CN104600126A - Super-barrier self-bias rectifying diode - Google Patents
Super-barrier self-bias rectifying diode Download PDFInfo
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- CN104600126A CN104600126A CN201310537560.6A CN201310537560A CN104600126A CN 104600126 A CN104600126 A CN 104600126A CN 201310537560 A CN201310537560 A CN 201310537560A CN 104600126 A CN104600126 A CN 104600126A
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- rectifier diode
- super barrier
- automatic biasing
- super
- vertical dmos
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- 230000004888 barrier function Effects 0.000 claims description 85
- 239000002019 doping agent Substances 0.000 claims description 12
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 4
- 229920005591 polysilicon Polymers 0.000 claims description 4
- 239000004065 semiconductor Substances 0.000 abstract description 6
- 229910044991 metal oxide Inorganic materials 0.000 abstract description 5
- 150000004706 metal oxides Chemical class 0.000 abstract description 5
- 230000000694 effects Effects 0.000 abstract description 2
- 238000009792 diffusion process Methods 0.000 abstract 4
- 230000015572 biosynthetic process Effects 0.000 description 6
- 238000010586 diagram Methods 0.000 description 6
- 230000008901 benefit Effects 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 230000003071 parasitic effect Effects 0.000 description 2
- 230000001105 regulatory effect Effects 0.000 description 2
- 230000003412 degenerative effect Effects 0.000 description 1
- 238000000605 extraction Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 230000035945 sensitivity Effects 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
The invention discloses a super-barrier self-bias rectifying diode; the super-barrier self-bias rectifying diode comprises a vertical double diffusion metal oxide semiconductor device and a polycrystalline resistor, wherein the grid electrode and the source electrode of the vertical double diffusion metal oxide semiconductor device are connected by the polycrystalline resistor. The grid electrode and the source electrode of the vertical diffusion metal oxide semiconductor device which forms the super-barrier self-bias rectifying diode are connected by the polycrystalline resistor, the negative feedback effect of the polycrystalline resistor is used for increasing the control of the grid electrode of the vertical double diffusion metal oxide semiconductor device to the channel conducting ability, thereby being able to achieve a smaller reverse leakage.
Description
Technical field
The present invention relates to technical field of semiconductors, be specifically related to power rectifier device technical field, particularly relate to a kind of super barrier automatic biasing rectifier diode.
Background technology
Super barrier Schottky barrier diodes (Super Barrier Rectifier, be called for short SBR) be rectification diode relatively more conventional at present, and the super barrier Schottky barrier diodes formed with N-type vertical DMOS (VerticalDouble-diffused Metal Oxide Semiconductor is called for short VDMOS) device is again main.Fig. 1 is the basic circuit diagram of the super barrier Schottky barrier diodes formed by N-type vertical DMOS device according to prior art.See Fig. 1, grid 102 and source electrode 103 short circuit of N-type VDMOS device 101, the source electrode 103 of N-type VDMOS device 101 is connected with drain electrode 104 by the parasitic diode 105 of N-type VDMOS device 101, and, the anode PP of super barrier Schottky barrier diodes is drawn, by the negative electrode NP of the extraction super barrier Schottky barrier diodes of the drain electrode 104 of N-type VDMOS device 101 by the grid 102 of N-type VDMOS device 101.
Owing to forming the grid 102 of the N-type VDMOS device of super barrier Schottky barrier diodes and source electrode 103 directly short circuit in prior art, so the ducting capacity of the raceway groove of grid 102 pairs of VDMOS device controls limited, thus cause the reverse leakage of super barrier Schottky barrier diodes relatively large.
Summary of the invention
In view of this, the embodiment of the present invention provides a kind of super barrier automatic biasing rectifier diode, solves the technical problem that the reverse leakage of the super barrier Schottky barrier diodes of prior art is larger.
Embodiments provide a kind of super barrier automatic biasing rectifier diode, comprising:
Vertical DMOS device and polycrystalline resistor, wherein, the grid of described vertical DMOS device is connected by described polycrystalline resistor with source electrode.
Further, the magnitude of the channel dopant concentration of described vertical DMOS device is for being more than or equal to 10
13/ cm
3.
Further, described super barrier automatic biasing rectifier diode also comprises the first pole and the second pole, wherein, described first pole is connected with the grid of described vertical DMOS device, and described second pole is connected with the drain electrode of described vertical DMOS device.
Further, described vertical DMOS device is N-type vertical DMOS device, the anode of the described first very described super barrier automatic biasing rectifier diode, the negative electrode of the described second very described super barrier automatic biasing rectifier diode.
Further, described vertical DMOS device is P type vertical DMOS device, the negative electrode of the described first very described super barrier automatic biasing rectifier diode, the anode of the described second very described super barrier automatic biasing rectifier diode.
Further, described polycrystalline resistor is polysilicon resistance.
The super barrier automatic biasing rectifier diode that the embodiment of the present invention proposes, by the grid of the VDMOS device forming super barrier automatic biasing rectifier diode is connected through polycrystalline resistor with source electrode, utilize the negative feedback of polycrystalline resistor, strengthen the grid of VDMOS device to the control of raceway groove ducting capacity, thus realize less reverse leakage.
Accompanying drawing explanation
By reading the detailed description done non-limiting example done with reference to the following drawings, other features, objects and advantages of the present invention will become more obvious:
Fig. 1 is the basic circuit diagram of the super barrier Schottky barrier diodes formed by N-type vertical DMOS device according to prior art;
Fig. 2 is the basic circuit diagram of the super barrier automatic biasing rectifier diode formed by N-type vertical DMOS device according to a first embodiment of the present invention;
Fig. 3 is the domain schematic diagram of the super barrier automatic biasing rectifier diode formed by N-type vertical DMOS device according to a first embodiment of the present invention.
Embodiment
Below in conjunction with drawings and Examples, the present invention is described in further detail.Be understandable that, specific embodiment described herein is only for explaining the present invention, but not limitation of the invention.It also should be noted that, for convenience of description, illustrate only part related to the present invention in accompanying drawing but not full content.
At present, in VDMOS device, most widely usedly belong to N-type VDMOS device.Herein just using the super barrier automatic biasing rectifier diode of N-type VDMOS device formation as specific embodiment, explain the present invention.It should be noted that, the invention is not restricted to the super barrier automatic biasing rectifier diode that N-type VDMOS device is formed, for the super barrier automatic biasing rectifier diode that P type VDMOS device is formed, the present invention is applicable equally.
Show the first embodiment of the present invention in figs. 2 and 3.
Fig. 2 is the basic circuit diagram of the super barrier automatic biasing rectifier diode formed by N-type vertical DMOS device according to a first embodiment of the present invention.As shown in Figure 2, described super barrier automatic biasing rectifier diode (Super Barrier Rectifier Self Bias, be called for short SBRSB) comprising: N-type vertical DMOS device 201 and polycrystalline resistor 202, wherein, the grid 203 of described N-type vertical DMOS device 201 is connected by described polycrystalline resistor 202 with source electrode 204.
In the present embodiment, described super barrier automatic biasing rectifier diode also comprises the first pole and the second pole, wherein, described first very anode PP, described anode PP is connected with the grid 203 of described N-type vertical DMOS device, described second pole NP is negative electrode NP, and described negative electrode NP is connected with the drain electrode 205 of described N-type vertical DMOS device.
In addition, with reference to figure 2, the source electrode 204 of described N-type vertical DMOS device 201 couples together with drain electrode 205 by the parasitic diode 206 being positioned at described N-type vertical DMOS device 201.
Fig. 3 is the domain schematic diagram of the super barrier automatic biasing rectifier diode formed by N-type vertical DMOS device according to a first embodiment of the present invention.With reference to Fig. 3, the grid 302 of N-type VDMOS device couples together with source electrode 301 by the polycrystalline resistor 303 being produced on grid 302 side of N-type VDMOS device, and draws the anode 304 of pin as super barrier automatic biasing rectifier diode from grid 302; The drain electrode of N-type VDMOS device, at the back side of Fig. 3 place paper, so there is no show, and draws the negative electrode of pin as super barrier automatic biasing rectifier diode from this drain electrode.
The present embodiment one preferred embodiment in, described polycrystalline resistor 202 is polysilicon resistance.Make polycrystalline resistor with polysilicon, manufacture craft is simple, and cost is very low, can realize again the technique effect that the present embodiment will reach simultaneously.See Fig. 2, the grid 203 of N-type VDMOS couples together with source electrode 204 by polycrystalline resistor 202, due to polycrystalline resistor along with temperature increases, its resistance value has and increases significantly, therefore, in use, when polycrystalline resistor 202 changes with its resistance of variations in temperature of chip, by the negative feedback of polycrystalline resistor 202, the magnitude of voltage on grid 203 can be regulated, thus strengthen the control of grid 203 pairs of raceway groove ducting capacity, make super barrier automatic biasing rectifier diode compared with the super barrier Schottky barrier diodes of prior art, there is less reverse leakage.In addition, as required, appropriate doping can be carried out to polycrystalline resistor, improve the sensitivity of polycrystalline resistor negative feedback.
When making super barrier automatic biasing rectifier diode, integrated circuit (Integrated Circuit is called for short IC) can be used to replace polycrystalline resistor to realize degenerative function.But the device comprised due to integrated circuit is more, design is got up more complicated, and manufacture difficulty is comparatively large, and cost is higher, so select polycrystalline resistor to make super barrier automatic biasing rectifier diode, is more preferably embodiment.
The super barrier automatic biasing rectifier diode that first embodiment of the invention proposes, by the grid of the N-type VDMOS device forming super barrier automatic biasing rectifier diode is connected through polycrystalline resistor with source electrode, utilize the negative feedback of polycrystalline resistor, strengthen the grid of N-type VDMOS device to the control of raceway groove ducting capacity, thus realize less reverse leakage.
Second embodiment of the invention.
Second embodiment of the invention is on the basis of the super barrier automatic biasing rectifier diode formed by N-type VDMOS device of first embodiment of the invention, further, when making the N-type VDMOS device forming super barrier automatic biasing rectifier diode, add channel dopant concentration.Wherein, add channel dopant concentration can be understood as: compared with the channel dopant concentration of the N-type VDMOS device of the formation super barrier Schottky barrier diodes of prior art, add the channel dopant concentration of the N-type VDMOS device forming super barrier automatic biasing rectifier diode, be specially: the magnitude of the channel dopant concentration of the N-type VDMOS device of the formation super barrier Schottky barrier diodes of prior art is 10
12/ cm
3, and the magnitude of the channel dopant concentration of the N-type VDMOS device of the formation super barrier automatic biasing rectifier diode of the present embodiment is for being more than or equal to 10
13/ cm
3.Be not difficult to find from Data Comparison above, the channel dopant concentration of the N-type VDMOS device of the formation super barrier automatic biasing rectifier diode of the present embodiment at least adds an order of magnitude than the channel dopant concentration of the N-type VDMOS device of the formation super barrier Schottky barrier diodes of prior art in magnitude.The benefit done like this makes formed super barrier automatic biasing rectifier diode On current when equal forward voltage drop become large, and ducting capacity strengthens.Therefore, producing in identical On current situation, the forward voltage drop needed for super barrier automatic biasing rectifier diode than prior art super barrier Schottky barrier diodes needed for forward voltage drop low.
Due to the above-mentioned doping content adding the raceway groove of N-type VDMOS device, make super barrier automatic biasing rectifier diode have lower forward voltage drop, but its reverse leakage also can be made to increase simultaneously.Form the negative feedback introducing polycrystalline resistor between the grid of the N-type VDMOS device of super barrier automatic biasing rectifier diode and source electrode according to a first embodiment of the present invention, the reverse leakage of formed super barrier automatic biasing rectifier diode is reduced.Because the present embodiment is based on first embodiment of the invention, add the channel dopant concentration of the N-type VDMOS device forming super barrier automatic biasing rectifier diode, therefore, can by regulating the resistance value of polycrystalline resistor, increase the negative feedback of polycrystalline resistor, thus make the reverse leakage of super barrier automatic biasing rectifier diode in the present embodiment less than the reverse leakage of the super barrier Schottky barrier diodes of prior art.
The super barrier automatic biasing rectifier diode that second embodiment of the invention proposes, by increasing the channel dopant concentration of the N-type VDMOS device forming super barrier automatic biasing rectifier diode, can realize lower forward voltage drop; By the grid of the N-type VDMOS device forming super barrier automatic biasing rectifier diode is connected through polycrystalline resistor with source electrode, utilize the negative feedback of polycrystalline resistor, strengthen the grid of N-type VDMOS device to the control of raceway groove ducting capacity, thus realize less reverse leakage.
Note, above are only preferred embodiment of the present invention and institute's application technology principle.Skilled person in the art will appreciate that and the invention is not restricted to specific embodiment described here, various obvious change can be carried out for a person skilled in the art, readjust and substitute and can not protection scope of the present invention be departed from.Therefore, although be described in further detail invention has been by above embodiment, the present invention is not limited only to above embodiment, when not departing from the present invention's design, can also comprise other Equivalent embodiments more, and scope of the present invention is determined by appended right.
Claims (6)
1. a super barrier automatic biasing rectifier diode, is characterized in that, comprising:
Vertical DMOS device and polycrystalline resistor, wherein, the grid of described vertical DMOS device is connected by described polycrystalline resistor with source electrode.
2. super barrier automatic biasing rectifier diode according to claim 1, is characterized in that, the magnitude of the channel dopant concentration of described vertical DMOS device is for being more than or equal to 10
13/ cm
3.
3. super barrier automatic biasing rectifier diode according to claim 1, it is characterized in that, described super barrier automatic biasing rectifier diode also comprises the first pole and the second pole, wherein, described first pole is connected with the grid of described vertical DMOS device, and described second pole is connected with the drain electrode of described vertical DMOS device.
4. super barrier automatic biasing rectifier diode according to claim 3, it is characterized in that, described vertical DMOS device is N-type vertical DMOS device, the anode of the described first very described super barrier automatic biasing rectifier diode, the negative electrode of the described second very described super barrier automatic biasing rectifier diode.
5. super barrier automatic biasing rectifier diode according to claim 3, it is characterized in that, described vertical DMOS device is P type vertical DMOS device, the negative electrode of the described first very described super barrier automatic biasing rectifier diode, the anode of the described second very described super barrier automatic biasing rectifier diode.
6. super barrier automatic biasing rectifier diode according to claim 1, is characterized in that, described polycrystalline resistor is polysilicon resistance.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310537560.6A CN104600126B (en) | 2013-10-31 | 2013-10-31 | A kind of super barrier automatic biasing commutation diode |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310537560.6A CN104600126B (en) | 2013-10-31 | 2013-10-31 | A kind of super barrier automatic biasing commutation diode |
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| CN104600126A true CN104600126A (en) | 2015-05-06 |
| CN104600126B CN104600126B (en) | 2017-10-24 |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1353863A (en) * | 1999-04-22 | 2002-06-12 | 理查德·K·威廉斯 | Super-self-aligned trench-gate DMOS with reduced on-resistance |
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| CN103325839A (en) * | 2013-06-26 | 2013-09-25 | 张家港凯思半导体有限公司 | MOS super barrier rectifier device and manufacturing method thereof |
| CN103337523A (en) * | 2013-06-19 | 2013-10-02 | 张家港凯思半导体有限公司 | Super potential barrier rectification device with inclined grooves, and manufacturing method thereof |
-
2013
- 2013-10-31 CN CN201310537560.6A patent/CN104600126B/en active Active
Patent Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1353863A (en) * | 1999-04-22 | 2002-06-12 | 理查德·K·威廉斯 | Super-self-aligned trench-gate DMOS with reduced on-resistance |
| CN101409444A (en) * | 2007-10-11 | 2009-04-15 | 和舰科技(苏州)有限公司 | Method for improving ESD protection device uniform conduction |
| CN102110687A (en) * | 2009-12-24 | 2011-06-29 | 上海华虹Nec电子有限公司 | Trench MOS (metal-oxide semiconductor) device |
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| CN102254944A (en) * | 2010-05-21 | 2011-11-23 | 上海新进半导体制造有限公司 | Power metal oxide semiconductor field effect transistor (MOSFET) power rectification device and manufacturing method |
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| CN102709331A (en) * | 2011-05-30 | 2012-10-03 | 朱江 | Channel metal-oxide semiconductor (MOS) structural semiconductor device and preparation method thereof |
| CN103325780A (en) * | 2012-03-19 | 2013-09-25 | 无锡华润华晶微电子有限公司 | Power integrated circuit |
| CN103337523A (en) * | 2013-06-19 | 2013-10-02 | 张家港凯思半导体有限公司 | Super potential barrier rectification device with inclined grooves, and manufacturing method thereof |
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| CN104600126B (en) | 2017-10-24 |
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