CN104570530A - Double-gate line array substrate and display device - Google Patents
Double-gate line array substrate and display device Download PDFInfo
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- CN104570530A CN104570530A CN201510053859.3A CN201510053859A CN104570530A CN 104570530 A CN104570530 A CN 104570530A CN 201510053859 A CN201510053859 A CN 201510053859A CN 104570530 A CN104570530 A CN 104570530A
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136286—Wiring, e.g. gate line, drain line
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1343—Electrodes
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1345—Conductors connecting electrodes to cell terminals
Abstract
An embodiment of the invention provides a double-gate line array substrate and a display device, relates to the technical field of display and aims to improve storage capacitance of the display device so as to reduce leaping voltage and improve display quality. The double-gate line array substrate comprises a plurality of gate line groups, a plurality of data lines and a plurality of pixel units. The gate line groups are crossed. The pixel units are arrayed. The gate line groups comprise first gate lines and second gate lines. The array substrate further comprises a first public electrode wire in the pixel units and a second public electrode wire corresponding to clearances between the first gate lines and the second gate lines; a pixel electrode in the pixel units and an auxiliary electrode electrically connected with the pixel electrode; an overlapping area 1 is formed between the first public electrode wire and the pixel electrode, and an overlapping area 2 is formed between the second public electrode wire and the auxiliary electrode. The double-gate line array substrate is applicable to display device production.
Description
Technical field
The present invention relates to display technique field, particularly relate to a kind of double grid linear array substrate and display device.
Background technology
TFT-LCD (Thin Film Transistor-Liquid Crystal Display, Thin Film Transistor-LCD), as the display device of current main flow, is widely used in the display products such as mobile phone, watch-dog, televisor.
The dot structure of TFT-LCD itself makes its inevitable leaping voltage existed because grid voltage causes from high to low, and the generation of leaping voltage can produce the display quality of TFT-LCD and directly affect.
Based on this, by reducing leaping voltage to obtain the TFT-LCD of high-quality, most important for improving the market competitiveness and obtaining good Consumer's Experience.
Summary of the invention
Embodiments of the invention provide a kind of double grid linear array substrate and display device, can increase the memory capacitance of display device, thus reduce leaping voltage, improve display quality.
For achieving the above object, embodiments of the invention adopt following technical scheme:
On the one hand, provide a kind of double grid linear array substrate, comprise the staggered multiple grid line group of transverse and longitudinal and a plurality of data lines, and multiple pixel cells of array arrangement; Described grid line group comprises the first grid line and the second grid line; Described array base palte also comprises: the first public electrode wire being positioned at described pixel cell inside, and second public electrode wire corresponding with the gap between described first grid line and described second grid line; Be positioned at the pixel electrode of described pixel cell inside, and the auxiliary electrode be electrically connected with described pixel electrode; Wherein, between described first public electrode wire and described pixel electrode, there is overlapping region, between described second public electrode wire and described auxiliary electrode, there is overlapping region.
Preferably, described pixel electrode and described auxiliary electrode have integral structure.
Preferred further, the connecting portion that described auxiliary electrode comprises the stripes mutually overlapping with described second public electrode wire and is connected with described pixel electrode; Wherein, along the direction being parallel to described grid line group, the size of described connecting portion is less than the size of described stripes.
Preferably, described first public electrode wire is electrically connected with described second public electrode wire.
Optionally, described first public electrode wire is electrically connected by connecting bridge with described second public electrode wire; Wherein, described connecting bridge and described pixel electrode are formed with layer.
Preferably, described first public electrode wire and described grid line group are formed with layer; Described second public electrode wire and described data line are formed with layer, and and mutually insulated between described data line.
Optionally, described pixel cell inside is also provided with thin film transistor (TFT); Wherein, the thin film transistor (TFT) of adjacent two pixel cells is connected with described second grid line with described first grid line respectively.
On the other hand, provide a kind of display device, comprise above-mentioned array base palte.
Embodiments of the invention provide a kind of double grid linear array substrate and display device.
In prior art, there is overlapping region between described first public electrode wire and described pixel electrode, therefore can form memory capacitance between; But this memory capacitance is formed in the inside of pixel cell, to increase memory capacitance, then need to increase the relative area between described first public electrode wire and described pixel electrode, the aperture opening ratio of pixel cell must be caused like this to decline to some extent.
In embodiments of the invention, by the outside at described pixel cell (namely, between described first grid line and described second grid line) the second mutually overlapping public electrode wire and auxiliary electrode are set, so, under the prerequisite not affecting pixel cell aperture opening ratio, additional storage capacitance can be formed between described second public electrode wire and described auxiliary electrode.
Compared to prior art, embodiments of the invention can under the prerequisite not affecting aperture opening ratio, the effective size improving memory capacitance.
On this basis, the theoretical formula of leaping voltage is as follows:
Wherein, △ Vp is leaping voltage, and Vgh, Vgl are respectively grid high level voltage and the grid low level voltage of drive TFT, and Cgs, Clc, Cst are respectively stray capacitance, liquid crystal capacitance, memory capacitance.
Based on this, embodiments of the invention, by increasing memory capacitance, can effectively reduce leaping voltage, thus improve the display quality of TFT-LCD.
Accompanying drawing explanation
In order to be illustrated more clearly in the embodiment of the present invention or technical scheme of the prior art, be briefly described to the accompanying drawing used required in embodiment or description of the prior art below, apparently, accompanying drawing in the following describes is only some embodiments of the present invention, for those of ordinary skill in the art, under the prerequisite not paying creative work, other accompanying drawing can also be obtained according to these accompanying drawings.
The structural representation one of a kind of array base palte that Fig. 1 provides for embodiments of the invention;
Fig. 2 is the A-A schematic cross-section of Fig. 1;
The structural representation one of a kind of pixel electrode that Fig. 3 provides for embodiments of the invention and auxiliary electrode;
The structural representation two of a kind of pixel electrode that Fig. 4 provides for embodiments of the invention and auxiliary electrode.
Accompanying drawing illustrates:
10-array base palte; 101-grid line group; 102-data line; 103-first public electrode wire; 104-second public electrode wire; 105-pixel electrode; 106-auxiliary electrode; 107-connecting bridge.
Embodiment
Below in conjunction with the accompanying drawing in the embodiment of the present invention, be clearly and completely described the technical scheme in the embodiment of the present invention, obviously, described embodiment is only the present invention's part embodiment, instead of whole embodiments.Based on the embodiment in the present invention, those of ordinary skill in the art, not making the every other embodiment obtained under creative work prerequisite, belong to the scope of protection of the invention.
Embodiments of the invention provide a kind of double grid linear array substrate 10, as shown in Figure 1, comprise the staggered multiple grid line group 101 of transverse and longitudinal and a plurality of data lines 102, and multiple pixel cells of array arrangement; Wherein, described grid line group 101 comprises the first grid line 1011 and the second grid line 1012 be parallel to each other, and preset pitch of being separated by between described first grid line 1011 and described second grid line 1012.
On this basis, described array base palte 10 also comprises: the first public electrode wire 103 being positioned at described pixel cell inside, and second public electrode wire 104 corresponding with the gap between described first grid line 1011 and described second grid line 1012; Be positioned at the pixel electrode 105 of described pixel cell inside, and the auxiliary electrode 106 be electrically connected with described pixel electrode 105; Wherein, between described first public electrode wire 103 and described pixel electrode 105, there is overlapping region, between described second public electrode wire 104 and described auxiliary electrode 106, there is overlapping region.
It should be noted that, the first, in an embodiment of the present invention, described pixel cell refers to the region limited by described grid line group 101 and described data line 102.In this region, except pixel electrode 105, be also provided with other structure such as thin film transistor (TFT) and public electrode wire.
The second, described first public electrode wire 103 forms bending structure in the inside of pixel cell, and described pixel electrode 105 is positioned at the central space place of this bending structure; That is, described first public electrode wire 103 arranges along the edge of described pixel electrode 105.
On this basis, in order to ensure to form memory capacitance between described first public electrode wire 103 and described pixel electrode 105, need make to form relative area between two electrodes, therefore between described first public electrode wire 103 and described pixel electrode 105, there is overlapping region.Certainly, formed here overlapping region need be as the criterion can obtain rational aperture opening ratio.
3rd, described second public electrode wire 104 can be formed with layer with described first public electrode wire 103, certainly also can be formed with layer with other conductive layer, as long as can ensure that the setting position of described second public electrode wire 104 is corresponding with the gap between described first grid line 1011 and described second grid line 1012 here, thus not affect the aperture opening ratio of pixel cell.
4th, described auxiliary electrode 106 can be formed with layer with described pixel electrode 105, certainly also can independently be formed, as long as can ensure here to be electrically connected to each other therebetween and between described auxiliary electrode 106 and described second public electrode wire 104, there is overlapping region.
Embodiments of the invention provide a kind of double grid linear array substrate 10, comprise the staggered multiple grid line group 101 of transverse and longitudinal and a plurality of data lines 102, and multiple pixel cells of array arrangement; Wherein, described grid line group 101 comprises the first grid line 1011 and the second grid line 1012 be parallel to each other, and preset pitch of being separated by between described first grid line 1011 and described second grid line 1012.
Described array base palte 10 also comprises: the first public electrode wire 103 being positioned at described pixel cell inside, and second public electrode wire 104 corresponding with the gap between described first grid line 1011 and described second grid line 1012; Be positioned at the pixel electrode 105 of described pixel cell inside, and the auxiliary electrode 106 be electrically connected with described pixel electrode 105; Wherein, between described first public electrode wire 103 and described pixel electrode 105, there is overlapping region, between described second public electrode wire 104 and described auxiliary electrode 106, there is overlapping region.
In prior art, there is overlapping region between described first public electrode wire 103 and described pixel electrode 105, therefore can form memory capacitance between; But this memory capacitance is formed in the inside of pixel cell, to increase memory capacitance, then need to increase the relative area between described first public electrode wire 103 and described pixel electrode 105, the aperture opening ratio of pixel cell must be caused like this to decline to some extent.
In embodiments of the invention, as shown in Figure 2, by the outside at described pixel cell (namely, between described first grid line 1011 and described second grid line 1012) the second mutually overlapping public electrode wire 104 and auxiliary electrode 106 are set, so, under the prerequisite not affecting pixel cell aperture opening ratio, additional storage capacitance can be formed between described second public electrode wire 104 and described auxiliary electrode 106.
Compared to prior art, embodiments of the invention can under the prerequisite not affecting aperture opening ratio, the effective size improving memory capacitance.
On this basis, the theoretical formula of leaping voltage is as follows:
Wherein, △ Vp is leaping voltage, and Vgh, Vgl are respectively grid high level voltage and the grid low level voltage of drive TFT, and Cgs, Clc, Cst are respectively stray capacitance, liquid crystal capacitance, memory capacitance.
Based on this, embodiments of the invention, by increasing memory capacitance, can effectively reduce leaping voltage, thus improve the display quality of TFT-LCD.
Known based on foregoing description, embodiments of the invention by outer setting second public electrode wire of pixel cell and auxiliary electrode, thus increase the relative area of electrode, and then reach the object increasing memory capacitance.Based on this, it should be noted that, in described array base palte, by the way and increase electrode relative area be limited, in order to obtain better display effect, embodiments of the invention are more suitable for undersized display device, can ensure that increased electrode relative area accounts for the ratio of the pixel total area so relatively large, just can obtain better display effect thus.
Preferably, as shown in Figure 3, described pixel electrode 105 has integral structure with described auxiliary electrode 106.
In the case, described pixel electrode 105 and described auxiliary electrode 106 have identical material, and by being formed with a patterning processes.A same patterning processes described here refers to same one-pass film-forming and exposure technology; That is, described pixel electrode 105 and described auxiliary electrode 106 are by the integral structure of identical rete through being formed with single exposure.
Embodiments of the invention can form pixel electrode 105 and the auxiliary electrode 106 of integrative-structure by patterning processes, effectively can simplify the processing procedure of array base palte like this, thus reduce costs.
On this basis, described auxiliary electrode 106 connecting portion that can comprise the stripes mutually overlapping with described second public electrode wire 104 and be connected with described pixel electrode 105.
Concrete, described stripes is used for forming overlapping region with described second public electrode wire 104, so that produce memory capacitance; Described connecting portion is used for being electrically connected with described pixel electrode 105.
In order to obtain relatively large memory capacitance in limited region, described stripes along data line 102 direction size preferably with the consistent size of described second public electrode wire 104, described stripes along grid line group 101 direction size preferably with the consistent size of described pixel electrode 105, larger relative area can be obtained like this, thus produce larger memory capacitance.
Further, because described auxiliary electrode 106 is when being connected with described pixel electrode 105, the connecting portion of described auxiliary electrode 106 needs the top across a grid line wherein; That is, can overlapping region be formed between a grid line in the connecting portion of described auxiliary electrode 106 and described grid line group 101, so just can produce stray capacitance between this grid line and described connecting portion.Consider above factor, described connecting portion is preferably less than the size of described stripes along the size in grid line group 101 direction.Here, ensureing that under the prerequisite that described pixel electrode 105 is electrically connected with described auxiliary electrode 106, described connecting portion is the smaller the better along the size in grid line group 101 direction.
Certainly, in an embodiment of the present invention, as shown in Figure 4, described pixel electrode 105 and described auxiliary electrode 106 also can be separate structure.Such as, described pixel electrode 105 can be identical with structure of the prior art, and described auxiliary electrode 106 can be prepared with layer with other conductive layer and keep being electrically connected with described pixel electrode 105 by via hole; So, described pixel electrode 105 and described auxiliary electrode 106 just can form separate structure, and do not affect between described auxiliary electrode 106 and described second public electrode wire 104 and form memory capacitance.
Optionally, shown in figure 1, described first public electrode wire 103 is electrically connected to each other with described second public electrode wire 104.
Concrete, can be electrically connected by connecting bridge 107 between described first public electrode wire 103 with described second public electrode wire 104.
Example, described first public electrode wire 103 can be prepared with layer with described grid line group 101, and described second public electrode wire 104 can be prepared with layer with described data line 102.In the case, described connecting bridge 107 can be prepared with layer with described pixel electrode 105, and is electrically connected with described first public electrode wire 103 and described second public electrode wire 104 respectively by via hole; Or described connecting bridge 107 also can be prepared with layer with described second public electrode wire 104, now described connecting bridge 107 has integrative-structure with described second public electrode wire 104, and is electrically connected with described first public electrode wire 103 by via hole.
So, described first public electrode wire 103 just can have identical voltage with described second public electrode wire 104, when it forms overlapping region with described pixel electrode 105 and described auxiliary electrode 106 respectively, effectively can increase memory capacitance.
On this basis, described first public electrode wire 103 is electrically connected to each other with described second public electrode wire 104, and this can be equivalent to the global sections adding public electrode wire and amass, thus its resistance is minimized.
Optionally, described first public electrode wire 103 and described second public electrode wire 104 all can be formed with layer with described grid line group 101.
Concrete, layer of metal film can be deposited on substrate, and by a patterning processes, composition be carried out to this metallic film, thus form the first grid line and the second grid line and the first public electrode wire 103 and the second public electrode wire 104.
In the case, described second public electrode wire 104 just can be formed between described first grid line and described second grid line; But, because the spacing between described first grid line and described second grid line is very little, and described second public electrode wire 104 to be ensured and mutually insulated between described first grid line and described second grid line, therefore the live width of the second public electrode wire 104 be filled in therebetween just can be caused very narrow, thus make the relative area that formed between itself and described auxiliary electrode 106 very little, the memory capacitance of formation so just can be caused very limited.
Based on this, preferably, described first public electrode wire 103 can be formed with layer with described grid line group 101; Described second public electrode wire 104 can be formed with layer with described data line 102, and and mutually insulated between described data line 102.
So, compared to the situation that described second public electrode wire 104 is prepared with layer with described first grid line and described second grid line, the area of described second public electrode wire 104 can increase to some extent, so that and form relatively large overlapping region between described auxiliary electrode 106, thus improve the size of memory capacitance.
It should be noted that, the setting of described second public electrode wire 104 should ensure that under the prerequisite with described data line 102 mutually insulated, the longer the better, now, described auxiliary electrode 106 with under other conductive layer prerequisite that such as connecting bridge 107 contacts with each other should not be the bigger the better in guarantee along the size in described second public electrode wire 104 direction.
Optionally, shown in figure 1, described pixel cell inside is also provided with thin film transistor (TFT) 108.
Concrete, described thin film transistor (TFT) 108 comprises grid, active layer, source electrode and drain electrode; Described grid is connected with described first grid line or described second grid line, and described source electrode is connected with described data line 102, and described drain electrode is connected with described pixel electrode 105.
Wherein, the thin film transistor (TFT) 108 of adjacent two pixel cells is connected with described second grid line with described first grid line respectively.
Embodiments of the invention also provide a kind of display device, comprise the shaping array base palte of box and color membrane substrates, and liquid crystal layer therebetween; Wherein, described array base palte is above-mentioned array base palte.
Here it should be noted that, described display device goes for TN (TwistNematic, twisted nematic) pattern or ADS (Advanced-super DimensionalSwitching, senior super dimension field conversion hysteria) any one in pattern or IPS (In-Plane Switch, copline switch type) pattern.
On this basis, described display device can be product or the parts that liquid crystal display, LCD TV, digital album (digital photo frame), mobile phone, panel computer etc. have any Presentation Function.
Based on this, prepare described display device by the array base palte adopting embodiments of the invention to provide, memory capacitance can be increased under the prerequisite not affecting aperture opening ratio.Thus effectively reduce leaping voltage, improve the display quality of TFT-LCD.
The above; be only the specific embodiment of the present invention, but protection scope of the present invention is not limited thereto, is anyly familiar with those skilled in the art in the technical scope that the present invention discloses; change can be expected easily or replace, all should be encompassed within protection scope of the present invention.Therefore, protection scope of the present invention should be as the criterion with the protection domain of described claim.
Claims (8)
1. a double grid linear array substrate, comprises the staggered multiple grid line group of transverse and longitudinal and a plurality of data lines, and multiple pixel cells of array arrangement; Described grid line group comprises the first grid line and the second grid line; It is characterized in that,
Described array base palte also comprises:
Be positioned at the first public electrode wire of described pixel cell inside, and second public electrode wire corresponding with the gap between described first grid line and described second grid line;
Be positioned at the pixel electrode of described pixel cell inside, and the auxiliary electrode be electrically connected with described pixel electrode;
Wherein, between described first public electrode wire and described pixel electrode, there is overlapping region, between described second public electrode wire and described auxiliary electrode, there is overlapping region.
2. array base palte according to claim 1, is characterized in that, described pixel electrode and described auxiliary electrode have integral structure.
3. array base palte according to claim 2, is characterized in that, the connecting portion that described auxiliary electrode comprises the stripes mutually overlapping with described second public electrode wire and is connected with described pixel electrode;
Wherein, along the direction being parallel to described grid line group, the size of described connecting portion is less than the size of described stripes.
4. array base palte according to claim 1, is characterized in that, described first public electrode wire is electrically connected with described second public electrode wire.
5. array base palte according to claim 4, is characterized in that, described first public electrode wire is electrically connected by connecting bridge with described second public electrode wire;
Wherein, described connecting bridge and described pixel electrode are formed with layer.
6. array base palte according to claim 1, is characterized in that, described first public electrode wire and described grid line group are formed with layer;
Described second public electrode wire and described data line are formed with layer, and and mutually insulated between described data line.
7. the array base palte according to any one of claim 1 to 6, is characterized in that, described pixel cell inside is also provided with thin film transistor (TFT);
Wherein, the thin film transistor (TFT) of adjacent two pixel cells is connected with described second grid line with described first grid line respectively.
8. a display device, is characterized in that, comprises the array base palte described in any one of claim 1-7.
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| CN201510053859.3A CN104570530A (en) | 2015-02-02 | 2015-02-02 | Double-gate line array substrate and display device |
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