CN104517816B - 具有弛豫减少衬垫的半导体器件及其相关方法 - Google Patents

具有弛豫减少衬垫的半导体器件及其相关方法 Download PDF

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CN104517816B
CN104517816B CN201410476591.XA CN201410476591A CN104517816B CN 104517816 B CN104517816 B CN 104517816B CN 201410476591 A CN201410476591 A CN 201410476591A CN 104517816 B CN104517816 B CN 104517816B
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P·莫兰
柳青
N·劳贝特
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Abstract

一种用于形成半导体器件的方法包括在应变的绝缘体上半导体晶片的应变半导体层上形成掩模层。形成约束了应变半导体层的隔离沟槽。隔离沟槽延伸穿过掩模层并且进入SOI晶片中而越过其氧化物层。电介质本体形成在隔离沟槽中。弛豫减少衬垫形成在电介质本体上以及在应变半导体层的相邻侧壁上。移除了在应变半导体层上的掩模层。

Description

具有弛豫减少衬垫的半导体器件及其相关方法
技术领域
本发明涉及电子器件领域，并且更具体地涉及半导体器件及其相关方法。
背景技术
一些半导体器件利用了绝缘体上半导体(SOI)技术，其中诸如硅之类的半导体薄层通过相对厚的电绝缘层与半导体衬底或晶片分离。该厚的电绝缘层也称作掩埋氧化物(BOX)层。半导体层通常具有几纳米的厚度，而半导体衬底通常具有几十纳米的厚度。
SOI技术与用于互补金属氧化物半导体(CMOS)器件的传统厚体技术相比提供某些优点。CMOS器件包括均形成在叠置在掩埋氧化物(BOX)层上薄硅层中的nMOSFET晶体管和pMOSFET晶体管。SOI技术允许CMOS器件工作在较低功耗下而同时提供了相同的性能水平。
有助于允许CMOS持续等比例缩减的一个特定类型SOI技术是全耗尽SOI(FDSOI)。与部分耗尽SOI(PDSOI)器件相反，在FDSOI器件其中相对薄的半导体沟道层位于掩埋氧化物(BOX)层之上，使得器件的耗尽区域覆盖了整个层。与例如PDSOI器件相比，FDSOI器件可以提供诸如更高开关速度以及阈值电压漂移减小的优点。
为了改进CMOS器件性能，可以将应力引入场效应晶体管(FET)的沟道中。当在纵向方向(也即在电流流动方向)上施加时，已知张应力增强了电子迁移率(也即n-沟道MOSFET驱动电流)，而已知压应力增强了空穴迁移率(也即p-沟道MOSFET驱动电流)。因此，张应力的绝缘体上硅(sSOI)对于nMOSFET晶体管是主要性能推动者，而压应力的绝缘体上锗硅(SGOI)对于pMOSFET晶体管是主要性能推动者。
为了防止在应变SOI晶片中相邻的nMOSFET与pMOSFET之间的电流泄漏，浅沟槽隔离(STI)形成在两个晶体管之间。通常在形成晶体管之前在半导体器件制造工艺早期形成STI。为了形成STI，掩模层形成在应变半导体层上，并且隔离沟槽形成穿过掩模层并且进入对应于相邻nMOSFET和pMOSFET晶体管的两个有源区域之间的SOI晶片中。电介质本体形成在隔离沟槽中。
当移除硬掩模时，在电介质本体与隔离沟槽接触的应变半导体层的边缘处发生了应变半导体层的机械弛豫。如图1中半导体器件10所示，机械弛豫是弹性的，并且可以导致在应变半导体层22的侧壁23与STI 16的相邻侧壁17之间形成断层或间隙12。应变半导体层22是应变SOI晶片20的一部分，其包括掩埋氧化物(BOX)层24和半导体衬底或晶片26。应变半导体层22的机械弛豫对载流子迁移率和晶体管阈值电压可变性产生了负面影响。
发明内容
一种用于形成半导体器件的方法，包括在应变的绝缘体上半导体晶片的应变半导体层上形成掩模层，以及形成约束应变半导体层的隔离沟槽。隔离沟槽可以延伸穿过掩模层，并且越过SOI晶片的氧化物层而进入SOI晶片中。该方法可以进一步包括在隔离沟槽中形成电介质本体，在电介质本体上以及在应变半导体层的相邻侧壁上形成弛豫减少衬垫，以及移除在应变半导体层上的掩模层。
当在STI形成之后移除用于形成STI的掩模层时，在电介质本体以及在应变半导体层的相邻侧壁上的弛豫减少衬垫有利地减小应变半导体层的弛豫。弛豫减少衬垫有利地维持应变半导体层的机械连续性。弛豫减少衬垫可以包括具有高杨氏模量的材料，诸如例如氧化铝或氧化铪。杨氏模量的数值可以大于70GPa。
应变半导体层可以包括硅以限定用于n沟道金属氧化物半导体场效应晶体管的有源区域。备选地，应变半导体层可以包括硅和锗以限定用于p沟道金属氧化物半导体场效应晶体管的有源区域。
弛豫减少衬垫的上表面可以形成为与应变半导体层的上表面共面。备选地，在应变半导体层的相邻侧壁上的弛豫减少衬垫的上表面可以形成为在应变半导体层的上表面之上。
电介质本体的上表面可以形成为与氧化层的上表面共面。该方法可以进一步包括在应变半导体层之上形成栅极堆叠，以及在栅极堆叠下方形成限定了在两者之间沟道区的突起的源极和漏极区域。
附图说明
图1是根据现有技术的半导体器件的剖视图。
图2是根据本实施例的半导体器件的剖视图。
图3是示出了用于形成图2的半导体器件的方法的流程图。
图4至图8是示出了图2的方法的一系列剖视图。
图9是根据本实施例的FinFET器件的剖视图。
具体实施方式
以下将参考其中示出了优选实施例的附图更完整描述本发明实施例。然而实施例可以以许多不同形式实施，并且不应构造为限定与在此所述的实施例。相反地，提供这些实施例以使得本公开将是完全和完整的，并且将项本领域技术人员完全传达本公开的范围。全文中相同数字涉及相同元件，并且主要符号用于标识在备选实施例中类似的元件。
初始地，参照附图2，首先描述作为CMOS半导体器件的半导体器件30。在所示实施例中，半导体器件30包括应变SOI晶片40，其包括半导体衬底或晶片46，在半导体衬底上的掩埋氧化物(BOX)层44，以及在掩埋氧化物层上的应变半导体层42。应变半导体层42限定了第一有源区域。
应变SOI晶片40可以是全耗尽SOI(FDSOI)晶片，如本领域技术人员易于知晓的那样。此外，应变SOI晶片40可以是超薄本体和掩埋(UTBB)晶片，如本领域技术人员也易于知晓的那样。例如，半导体衬底46的厚度可以在约10至25nm的范围内，并且应变半导体层42的厚度可以在约5至10nm的范围内。
浅沟槽隔离(STI)50约束了应变半导体层42，其中延伸进入SOI晶片40的STI越过掩埋氧化物层44。弛豫减少衬垫60在STI 50上，以及在应变半导体层42的相邻侧壁43上。
如以下进一步详述的那样，用于形成STI 50的掩模层具有高杨氏模量。因此，当掩模层放置在合适位置时，维持了应变半导体层42的机械连续性。当移除掩模层时，弛豫减少衬垫60有利地减小了应变半导体层42的弛豫。这可以通过维持应变半导体层42的机械连续性而完成。
弛豫减少衬垫60可以包括具有高杨氏模量的材料。杨氏模量的数值需要大于STI50中电介质本体52。在退火之后，电介质本体52(例如氧化硅)通常具有在60至70GPa范围内的杨氏模量。因此，高杨氏模量需要大于70GPa。具有高杨氏模量的示例性材料是氧化铝和氧化铪。氧化铝具有在200至400GPa范围内的杨氏模量，而氧化铪具有70至150GPa范围内的杨氏模量。用于弛豫减少衬垫60的材料的机械特性变化，这继而引起杨氏模量的测量数值类似地变化，如本领域技术人员易于知晓的那样。
选择用于弛豫减少衬垫60的材料的另一因素是需要具有高的刻蚀选择性。高刻蚀选择性是例如相对于氧化物和氮化物。此外，弛豫减少衬垫60需要展现良好的电介质特性。可以使用除了氧化铝和氧化铪之外的材料，只要它们具有高杨氏模量，相对于氧化物和氮化物具有高的刻蚀选择性，并且具有良好的电介质特性。
现在参照图3中的流程图100以及参照图4至图9所示对应的工艺流程而描述用于形成半导体器件30的方法。从开始处(框102)，掩模层70在框104处形成在应变半导体层42上，如图4所示。
在步骤106处形成约束了应变半导体层42的隔离沟槽48，也如图4所示。隔离沟槽48延伸穿过掩模层70，并且越过掩埋氧化物层44进入SOI晶片40中。电介质本体52在框108处形成在隔离沟槽48中以限定STI 50，如图5所示。电介质本体52是氧化物，其是具有低杨氏模量(也即小于70GPa)的软材料。
通常，氧化物填充了越过掩模层70的隔离沟槽48。在该示例性实施例中，选择性移除氧化物，使得剩余的电介质本体52的上表面与氧化物层44的上表面共面。
在框112处在电介质本体52上以及在应变半导体层42的相邻侧壁43上形成弛豫减少衬垫60，如图6所示。在该示例性实施例中，也在掩模层70上形成弛豫减少衬垫60。如上所述，弛豫减少衬垫60可以包括具有高杨氏模量的材料，诸如例如氧化铝或氧化铪。此外，氧化铝和氧化铪均具有良好的电介质特性以及对于氧化物和氮化物的高刻蚀选择性。在该示例性实施例中，掩模层70和掩模层上弛豫减少衬垫60的一部分在步骤114处移除，使得剩余的弛豫减少衬垫60的上表面与应变半导体层42的上表面共面，如图2所示。
在一个备选实施例中，掩模层70和掩模层上弛豫减少衬垫60的一部分在步骤114处移除，使得在应变半导体层42’的相邻侧壁43’上的弛豫减少衬垫60的上表面在应变半导体层的上表面上方，如图7所示。弛豫减少衬垫60’因此包括了接触应变半导体层42’的相邻侧壁43’的边缘部分62’以及非边缘部分64’。边缘部分62’的上表面在应变半导体层42’的上表面上方，并且非边缘部分64’的上表面与应变半导体层42’的上表面共面。弛豫减少衬垫60’的非边缘部分64’的厚度可以在约5至10nm的范围内，也即与应变半导体层42的厚度相同。弛豫减少衬垫60’的边缘部分62’的厚度可以在约10至20nm的范围内。
当移除掩模层70时，在电介质本体52以及在应变半导体层42的相邻侧壁43上的弛豫减少衬垫60有利地减小了应变半导体层的弛豫。弛豫减少衬垫60有利地维持了应变半导体层的机械连续性，而如果电介质本体52替代地位于应变半导体层42的相邻侧壁43上则并非是这种情形。
方法进一步包括在框116处在应变半导体层42之上形成第一栅极堆叠80，其限定了第一有源区域。在图8所示半导体器件的所示实施例中，栅极堆叠80包括栅极电介质层82、栅极电极层84以及侧壁间隔体86。如本领域技术人员易于知晓的那样，半导体器件可以是CMOS半导体器件。在该情形下，方法可以进一步包括在应变半导体层128之上形成第二栅极堆叠130，这限定了第二有源区域。栅极堆叠130包括栅极电解质层132，栅极电极层134，以及侧壁间隔体136。STI 60以及在STI 50中的电介质材料52分隔了第一有源区域42和第二有源区域128。
突起的源极和漏极区域90、92在框118处形成以在第一栅极堆叠80下方第一有源区域中在两者之间限定第一沟道94。在一个实施例中，沟道区域94是用于n沟道金属氧化物半导体场效应晶体管(nMOSFET)98。类似地，突起的源极和漏极区域140、142形成以在第二栅极堆叠130下方第二有源区域中限定在两者之间的第二沟道144。在一个实施例中，沟道区域144是用于p沟道金属氧化物半导体场效应晶体管(pMOSFET)148。方法结束于框120。
鉴于上述内容，可以实施各种不同晶体管结构，包括但不限于：例如，平面CMOS，高k金属栅极CMOS，PD-SOI，FD-SOI，UTBB，垂直双栅，埋栅，FinFET，三栅，多栅，2D，3D，突起的源极/漏极，应变源极/漏极，应变沟道，及其组合/混合。
FinFET器件200”的剖视图示出在图9中。FinFET器件200”包括应变SOI晶片，其包括半导体衬底或晶片46”，半导体衬底上的掩埋氧化物(BOX)层44”，以及掩埋氧化物层上的应变半导体层42”。应变半导体层42”限定了第一有源区域。另一应变半导体层128”在邻近有源区域42”的掩埋氧化物层44”上，并且限定了第二有源区域，如上所述。
浅沟槽隔离(STI)包括约束了应变半导体层42”的电介质本体52”，也如前所述。STI中的电介质本体52”延伸进入SOI晶片中而越过其掩埋氧化物层44”。弛豫减少衬垫60”在电介质本体52”上，并且在应变半导体层42”的相邻侧壁43”上。
限定了第一有源区域的应变半导体层42”是用于nMOSFET，而限定了第二有源区域的第二应变半导体层128”是用于pMOSFET。鳍230”限定了用于nMOSFET的沟道，而鳍260”限定了用于pMOSFET的沟道。栅极270”叠置在鳍230”、260”上，并且包括在电介质层274”上的多晶硅层272”。
FinFET器件200”包括可以外延生长的突起的源极/漏极区域。外延生长SiGe可以用于减小源极/漏极区域的电阻和应力。源极/漏极区域的该特征方面也适用于FD-SOI。
已经受益于前述说明书和附图展示的教导，本领域技术人员将知晓许多修改和其他实施例。因此，应该理解的是，本发明不应限于所述具体实施例，并且修改例和实施例意在包括于所附权利要求的范围之内。

Claims (23)

1.一种用于形成半导体器件的方法，包括：
在应变的、绝缘体上半导体晶片的应变半导体层上形成掩模层，所述晶片包括衬底、在所述衬底上的氧化物层、以及在所述氧化物层上的应变半导体层；
形成穿过所述应变半导体层、穿过所述掩模层以及进入所述衬底的隔离沟槽，所述隔离沟槽暴露在所述隔离沟槽内的所述应变半导体的第一侧表面和第二侧表面；
在所述隔离沟槽中形成电介质本体，所述电介质本体直接接触所述氧化物层和所述衬底；
在所述电介质本体上形成弛豫减少衬垫，所述弛豫减少衬垫在所述隔离沟槽内在所述应变半导体层的所述第一侧表面和所述第二侧表面之间延伸，并且邻接所述第一侧表面和所述第二侧表面，所述弛豫减少衬垫的一部分在所述掩模层上，并且所述弛豫减少衬垫的下表面与所述应变半导体层的下表面共面；
从所述应变半导体层移除所述掩模层和在所述掩模层上的所述弛豫减少衬垫的所述部分，所述弛豫减少衬垫的第一上表面在移除所述掩模层之后与所述应变半导体层的上表面共面；
在所述应变半导体层中形成源极区域和漏极区域中的至少一项，所述源极区域和所述漏极区域中的所述至少一项在所述氧化物层上并与所述氧化物层直接接触，并且邻接所述弛豫减少衬垫；以及
在去除所述掩模层和所述弛豫减少衬垫的所述部分之后，在所述应变半导体层之上形成栅极堆叠。
2.根据权利要求1所述的方法，其中所述弛豫减少衬垫包括氧化铝。
3.根据权利要求1所述的方法，其中所述弛豫减少衬垫包括氧化铪。
4.根据权利要求1所述的方法，其中所述弛豫减少衬垫具有大于70GPa的杨氏模量。
5.根据权利要求1所述的方法，其中所述应变半导体层包括硅。
6.根据权利要求1所述的方法，其中所述应变半导体层包括硅和锗。
7.根据权利要求1所述的方法，其中所述弛豫减少衬垫的第二表面邻接所述应变半导体层的所述第一侧表面并且被形成为在所述应变半导体层的所述上表面上方。
8.根据权利要求1所述的方法，其中形成源极区域和漏极区域中的所述至少一项包括：
形成突起的源极和漏极区域，所述突起的源极和漏极区域在所述栅极堆叠下方限定在两者之间的沟道。
9.根据权利要求8所述的方法，其中所述沟道用于具有FinFET结构的金属氧化物半导体场效应晶体管(MOSFET)。
10.一种用于形成半导体器件的方法，包括：
在应变的、绝缘体上硅晶片的应变硅层上形成掩模层，所述晶片包括衬底、在所述衬底上的氧化物层、以及在所述氧化物层上的应变半导体层；
形成穿过所述应变硅层、穿过所述掩模层并且进入所述衬底的隔离沟槽，所述隔离沟槽暴露在所述隔离沟槽内的所述应变硅层的第一侧表面和第二侧表面；
在所述隔离沟槽中形成电介质本体，所述电介质本体直接接触所述氧化物层和所述衬底；
在所述电介质本体上形成包括氧化铝和氧化铪中的至少一种的衬垫，所述衬垫在所述隔离沟槽内在所述应变硅层的所述第一侧表面和所述第二侧表面之间延伸，并且邻接所述第一侧表面和所述第二侧表面，所述衬垫的一部分在所述掩模层上，并且所述衬垫的下表面与所述应变硅层的下表面共面；
从所述应变硅层移除掩模层和在所述掩模层上的所述衬垫的所述部分，所述衬垫的第一上表面在移除所述掩模层之后与所述应变硅层的上表面共面；
在所述应变半导体层中形成源极区域和漏极区域中的至少一项，所述源极区域和所述漏极区域中的所述至少一项在所述氧化物层上并与所述氧化物层直接接触，并且与所述衬垫直接接触；以及
在去除所述掩模层和所述衬垫的所述部分之后，在所述应变半导体层之上形成栅极堆叠。
11.根据权利要求10所述的方法，其中所述应变硅层包括硅和锗。
12.根据权利要求10所述的方法，其中在所述应变硅层的相邻侧壁上的所述衬垫的第二表面被形成为在所述应变硅层的上表面上方。
13.根据权利要求10所述的方法，其中形成源极区域和漏极区域中的所述至少一项包括：
形成突起的源极和漏极区域，所述突起的源极和漏极区域在所述栅极堆叠下方限定在两者之间的沟道。
14.根据权利要求13所述的方法，其中所述沟道用于具有FinFET结构的金属氧化物半导体场效应晶体管(MOSFET)。
15.一种半导体器件，包括：
应变的、绝缘体上半导体SOI衬底，其包括衬底、在所述衬底上的氧化物层、以及在所述氧化物层上的应变半导体层；
浅沟槽隔离STI，与在所述SOI衬底中的所述应变半导体层相邻，其中所述STI延伸越过氧化物层进入所述SOI衬底中，其中所述STI直接接触所述氧化物层和所述衬底；
弛豫减少衬垫，在所述STI上以及在所述应变半导体层的第一侧表面和第二侧表面之间延伸，并且邻接所述第一侧表面和所述第二侧表面，所述弛豫减少衬底的第一上表面与所述应变半导体层的上表面共面，并且所述弛豫减少衬垫的下表面与所述应变半导体层的下表面共面；
形成在所述应变半导体层中的源极区域和漏极区域，所述源极区域和所述漏极区域中的每一个在所述氧化物层上并与所述氧化物层直接接触，并且邻接所述弛豫减少衬垫；以及
在所述应变半导体层上的栅极堆叠，所述栅极堆叠在所述源极区域和所述漏极区域的部分之上。
16.根据权利要求15所述的半导体器件，其中所述弛豫减少衬垫包括氧化铝。
17.根据权利要求15所述的半导体器件，其中所述弛豫减少衬垫包括氧化铪。
18.根据权利要求15所述的半导体器件，其中所述弛豫减少衬垫具有大于70GPa的杨氏模量。
19.根据权利要求15所述的半导体器件，其中所述应变半导体层包括硅。
20.根据权利要求15所述的半导体器件，其中所述应变半导体层包括硅和锗。
21.根据权利要求15所述的半导体器件，其中所述弛豫减少衬垫的邻接所述应变半导体层的第一侧表面的第二上表面在所述应变半导体层的所述上表面上方。
22.根据权利要求15所述的半导体器件，
其中所述源极区域和所述漏极区域包括突起的源极和漏极区域，在所述栅极堆叠下方限定在两者之间的沟道。
23.根据权利要求22所述的半导体器件，其中所述沟道用于具有FinFET结构的金属氧化物半导体场效应晶体管(MOSFET)。
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