CN104517802A - Semiconductor device production method - Google Patents
Semiconductor device production method Download PDFInfo
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- CN104517802A CN104517802A CN201310459990.0A CN201310459990A CN104517802A CN 104517802 A CN104517802 A CN 104517802A CN 201310459990 A CN201310459990 A CN 201310459990A CN 104517802 A CN104517802 A CN 104517802A
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Abstract
The invention discloses a semiconductor device production method. The semiconductor device production method includes: providing a design mask comprising multiple designed main line patterns; lengthening the designed main line patterns or adding auxiliary virtual strip patterns to end points of the designed main line patterns to further obtain a revised deign mask; producing a photoetching mask according to the revised design mask; using the photoetching mask for performing photoetching and etching on a chip; finally, using a cutting mask to cut off unnecessary auxiliary lines according to design requirements. According to the semiconductor device production method, the problem that the lines are easy to break during micropattern processing of a silicon semiconductor substrate is solved, the patterns on the mask are ensured to be completely transferred to the silicon semiconductor substrate, and further reliability and production efficiency of the produced semiconductor device structure are improved.
Description
Technical field
The present invention relates to semiconductor fabrication process, particularly a kind of method making semiconductor device.
Background technology
Along with semiconductor integrated circuit (IC) industrial technology maturation day by day, developing rapidly of ultra-large integrated circuit, component size is more and more less, and the integrated level of chip is more and more higher.Because of the high density of device, undersized requirement also becomes increasingly conspicuous on semiconductor technology impact.In existing advanced technologies (as in the following technology generations of 28 nanometer), along with the critical size of pattern, namely the size of pattern reduces, the raising of the speed of semiconductor device, the integrated level of semiconductor device strengthens, in the process of micro-patterning technique (micro-patterning process), be easy to produce lines to break the problem of (Poly line pinch), the performance of this problems affect semiconductor device and rate of finished products.
Micro-patterning technique is that the figure after photoetching development on light shield appears on silicon chip the figure on light shield by exposing multiple copies on the silicon chip scribbling photoresist.A light shield contains the figure needed for one or more chip, silicon chip surface is coated with photoresist, exposure process is the ultraviolet light that sends of LASER Light Source or the light shield of deep UV (ultraviolet light) by aiming at, and the object of exposure is the final graphics that the figure on light shield accurately will be copied on photoresist.Finally adopt suitable lithographic method etching silicon wafer according to the final graphics on photoresist, to form the silicon chip with targeted graphical, then, remove photoresist layer.
Usually the micro-patterning technique adopted in the prior art has the silicon chip of targeted graphical to be formed, concrete step is, step a, provides silicon semiconductor substrate, and this silicon semiconductor substrate can comprise some device architectures; Step b, applies photoresist on a semiconductor substrate; Step c, is placed in above photoresist by the mask plate (as Fig. 2 A) comprising circuit pattern; Steps d, is formed should the photoetching agent pattern of circuit pattern after the techniques such as exposure imaging; Step e, detect (ADI) critical size (CD) (as Fig. 2 B) after adopting development, the size of ADI critical size directly affects the critical size of subsequent step; Step f, according to the photoresist layer etch silicon Semiconductor substrate of patterning, to form circuit in silicon semiconductor substrate; Step g, detects the circuit (as Fig. 2 C) that (AEI) silicon semiconductor substrate is formed after adopting etching.
But certain problem can be there is in the method for prior art, the circuit that silicon semiconductor substrate is formed has the problem that lines break, causing the factor of this problem to be not only poor lithographic process window, can also be the tensile stress (tensile stress) produced in etching process.Because will produce extra power to the tensile stress of lines, this will cause the narrower problem (as Fig. 2 C) producing lines simultaneously and break become at lines.
At present, solve the lines problem of breaking and propose to allow and adopt optics to close on the size that correction (OPC) increases lines.In order to compensate for optical faces Ji effect, the designer of light shield can utilize computerized algorithm, and generate optics to small-feature-size on light shield and close on correction, carry out the figure of optics correction, its size increases.But mainly use in a photolithographic process because current optics closes on correction model (OPC model), optics closes on correction model and combines optical model (optical model) and photoresist model (resist model), so can not reach required requirement guaranteeing in the integrality of design transfer that optics closes on to revise.
Therefore, need a kind of new method, to solve the problem that the lines that produce when carrying out micro-pattern process of silicon semiconductor substrate easily break.
Summary of the invention
In summary of the invention part, introduce the concept of a series of reduced form, this will further describe in embodiment part.Summary of the invention part of the present invention does not also mean that the key feature and essential features that will attempt to limit technical scheme required for protection, does not more mean that the protection range attempting to determine technical scheme required for protection.
In order to effectively solve the problem, the present invention proposes a kind of method making semiconductor device structure, comprise the following steps: to provide designed mask version, described designed mask version comprises multiple Design theme bar pattern; By extending the length of described Design theme bar pattern or adding auxiliary virtual strip pattern at the end points place of described Design theme bar pattern, and then obtain revised designed mask version; Lithography mask version is made according to described revised designed mask version; Described lithography mask version is used to carry out chemical etching to wafer.
Preferably, the length extending described Design theme bar pattern can not affect other contiguous layout.
Preferably, the length of prolongation is less than or equal to 1 micron.
Preferably, be also included in and use after described lithography mask version carries out chemical etching to wafer, use cutting mask plate described wafer to be carried out to the step of chemical etching.
Preferably, need to use described cutting mask plate to cut unwanted auxiliary line according to design.
Preferably, the length of remaining described auxiliary virtual strip pattern is less than or equal to 0.2 micron.
According to the method preparing semiconductor device of the present invention, the problem that the lines solving the generation when silicon semiconductor substrate carries out micro-patterning break, to guarantee complete the transferring in silicon semiconductor substrate of pattern on mask plate, and then improve the reliability of semiconductor device structure and the production efficiency of preparation.
Accompanying drawing explanation
Following accompanying drawing of the present invention in this as a part of the present invention for understanding the present invention.Shown in the drawings of embodiments of the invention and description thereof, be used for explaining principle of the present invention.In the accompanying drawings,
Fig. 1 is to the process chart carrying out silicon semiconductor substrate and carry out micro-patterning technique according to prior art;
Fig. 2 A-2C is to the schematic diagram carrying out silicon semiconductor substrate and carry out micro-patterning technique according to prior art;
Fig. 3 A-3D is to the schematic diagram carrying out silicon semiconductor substrate and carry out micro-patterning technique according to an embodiment of the invention;
Fig. 4 is be to the process chart carrying out silicon semiconductor substrate and carry out micro-patterning technique according to an embodiment of the invention.
Embodiment
In the following description, a large amount of concrete details is given to provide more thorough understanding of the invention.But, it will be apparent to one skilled in the art that the present invention can be implemented without the need to these details one or more.In other example, in order to avoid obscuring with the present invention, technical characteristics more well known in the art are not described.
In order to thoroughly understand the present invention, by following description, detailed step is proposed, to illustrate how the present invention improves the technique making semiconductor device structure to solve the problems of the prior art.Obviously, the specific details that the technical staff that execution of the present invention is not limited to semiconductor applications has the knack of.Preferred embodiment of the present invention is described in detail as follows, but except these are described in detail, the present invention can also have other execution modes.
Should be understood that, " comprise " when using term in this manual and/or " comprising " time, it indicates exists described feature, entirety, step, operation, element and/or assembly, but does not get rid of existence or additional other features one or more, entirety, step, operation, element, assembly and/or their combination.
In order to solve the problems of the prior art, the present invention proposes a kind of manufacture method of semiconductor device.With reference to Fig. 3 A to Fig. 3 D, the schematic diagram of the correlation step of the embodiment according to one aspect of the invention is shown.
Below in conjunction with accompanying drawing 3A-3D, the specific embodiment of the present invention is described in detail.With reference to Fig. 3 A to Fig. 3 D, the schematic diagram of the correlation step of the embodiment according to one aspect of the invention is shown.
As shown in Figure 3A, need to relate to the designed mask version 300 with circuit pattern according to technique, concrete, mask plate for forming Design theme bar in silicon semiconductor substrate or wafer.Described designed mask version comprises multiple Design theme bar pattern.Due to the equal factor of circuit that the Design theme bar pattern in manufacturing process node difference or designed mask version is corresponding, the length of Design theme bar pattern and width need need setting according to actual process.Wherein, Design theme bar pattern connects for the main circuit formed in semiconductor device or forms main device architecture.
As shown in Figure 3 B, extend the length of Design theme bar (main line) pattern in designed mask version 300 or add auxiliary virtual strip pattern at the end points place of described Design theme bar pattern, and then obtaining revised designed mask version 301;
In an embodiment of the present invention, the end points place A of the described Design theme bar pattern in designed mask version 300 adds auxiliary virtual strip pattern 301a, concrete, the end points place A of the described Design theme bar pattern of designed mask version 300 adds the auxiliary virtual strip pattern 301a of compression stress to form revised designed mask version 301, virtual strip pattern 301a extends the length of Design theme bar pattern in designed mask version 300, to avoid when forming design lines according to designed mask version etched wafer or Semiconductor substrate, due to the final pattern formed in silicon semiconductor substrate of tensile stress impact that lines are subject to, to realize the effect of removing the tensile stress that lines are subject to.
In another embodiment of the present invention, extend the length of the Design theme bar pattern in designed mask version to obtain the Design theme bar pattern after extending, and then obtain revised designed mask version 301, on extending design mask plate 300 Design theme bar pattern length technical process in, the length extended is less than or equal to 1 micron, and, the length extending described Design theme bar pattern can not affect other layout closed on, such as, if the long design of pattern that will affect around it of the length of Design theme bar pattern extended, change or inaccuracy to make other layouts around the Design theme bar pattern of prolongation, the final design affecting device pattern.The length of the auxiliary dummy pattern 301a added at the end points place of described Design theme bar pattern is less than or equal to 0.2 micron.
As shown in Figure 3 C, by the design transfer of revised designed mask version 301 on mask plate, to form the mask plate 302 of patterning.
By photoetching process by the design transfer of the mask of described patterning on the mask layer on wafer, usual described mask layer can comprise any one of several mask materials, includes but not limited to: hard mask material and photoresist mask material.Preferably, mask layer comprises photoresist mask material.Photoresist mask material can comprise the Other substrate materials be selected from the group comprising positive-tone photo glue material, negative photo glue material and mixing Other substrate materials.Usually, mask layer comprises and has thickness from about 500 to the positive-tone photo glue material of about 5000 dusts or negative photo glue material.In an embodiment of the present invention, make lithography mask version according to revised designed mask version, use described lithography mask version to etch wafer or Semiconductor substrate.
In an embodiment of the present invention, silicon semiconductor substrate forms bottom antireflective coating and photoresist layer, after the techniques such as exposure imaging, form the photoetching agent pattern of corresponding revised reticle pattern according to the lithography mask version designed.
Then, according to mask layer, Semiconductor substrate or wafer are etched, with by the design transfer on lithography mask version in Semiconductor substrate.
Semiconductor substrate can comprise any semi-conducting material, and this semi-conducting material can include but not limited to: Si, SiC, SiGe, SiGeC, Ge alloy, GeAs, InAs, InP, and other III-V or group Ⅱ-Ⅵ compound semiconductor.
As preferably, described Semiconductor substrate is the thickness of Si material layer is 10-100nm, is preferably 30-50nm.
In an embodiment of the present invention, according to lithography mask version, Semiconductor substrate or wafer are etched, to form polysilicon lines.
Dry etching Semiconductor substrate can be adopted, conventional dry etching technics, such as the combination in any of reactive ion etching, ion beam etching, plasma etching, laser ablation or these methods.Single lithographic method can be used, or also can use more than one lithographic method.
Use after described lithography mask version carries out chemical etching to wafer or Semiconductor substrate, also comprise the step using cutting mask plate described wafer or Semiconductor substrate to be carried out to chemical etching.
The end points place of the Design theme bar pattern in described designed mask version 300 adds the length of assisting virtual strip pattern or extending the main line image of polysilicon in designed mask version 300 and forms revised designed mask version 301, again by the design transfer of revised designed mask version 301 to lithography mask version 302, then according to after lithography mask version 302 chemical etching wafer, use the auxiliary virtual strip pattern of cutting mask plate 303 removal part to obtain described Design theme bar layout.
The length of last remaining auxiliary virtual strip pattern is less than or equal to 0.2 micron.Concrete, need to use cutting mask plate 303 to cut unwanted auxiliary line and the polysilicon lines below it according to design.
Rear detection is etched to the final polysilicon lines 304 formed, after detection, does not find that having live width in polysilicon lines narrows or occur the problem that lines break.
As shown in Figure 4, according to an embodiment of the invention to the process chart carrying out silicon semiconductor substrate and carry out micro-patterning technique
Step 401: designed mask version is provided;
Step 402: by extending the length of described Design theme bar pattern or adding auxiliary virtual strip pattern at the end points place of described Design theme bar pattern, and then obtain revised designed mask version;
Step 403: by the design transfer of revised designed mask version on lithography mask version, according to lithography mask version chemical etching wafer;
Step 403: use cutting mask to cut unwanted auxiliary line and the polysilicon lines below it;
Step 405: detect after performing etching.
The present invention is illustrated by above-described embodiment, but should be understood that, above-described embodiment just for the object of illustrating and illustrate, and is not intended to the present invention to be limited in described scope of embodiments.In addition it will be appreciated by persons skilled in the art that the present invention is not limited to above-described embodiment, more kinds of variants and modifications can also be made according to instruction of the present invention, within these variants and modifications all drop on the present invention's scope required for protection.
Claims (6)
1. make a method for semiconductor device, comprising:
There is provided designed mask version, described designed mask version comprises multiple Design theme bar pattern;
By extending the length of described Design theme bar pattern or adding auxiliary virtual strip pattern at the end points place of described Design theme bar pattern, and then obtain revised designed mask version;
Lithography mask version is made according to described revised designed mask version;
Described lithography mask version is used to carry out chemical etching to wafer.
2. the method for claim 1, is characterized in that, the length extending described Design theme bar pattern can not affect other contiguous layout.
3. the method for claim 1, is characterized in that, the length of prolongation is less than or equal to 1 micron.
4. the method for claim 1, is characterized in that, is also included in and uses after described lithography mask version carries out chemical etching to wafer, use cutting mask plate described wafer to be carried out to the step of chemical etching.
5. method as claimed in claim 4, is characterized in that, need to use described cutting mask plate to cut unwanted auxiliary line according to design.
6. method as claimed in claim 5, is characterized in that, the length of remaining described auxiliary virtual strip pattern is less than or equal to 0.2 micron.
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| CN201310459990.0A CN104517802B (en) | 2013-09-27 | 2013-09-27 | A kind of method for making semiconductor devices |
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| CN201310459990.0A CN104517802B (en) | 2013-09-27 | 2013-09-27 | A kind of method for making semiconductor devices |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN108231793A (en) * | 2018-01-02 | 2018-06-29 | 京东方科技集团股份有限公司 | Method, display base plate and production method, the display device being patterned to conductive film layer |
| CN110658696A (en) * | 2019-09-30 | 2020-01-07 | 上海华力集成电路制造有限公司 | Photoetching friendliness design checking method for disconnection hot spot |
| CN110687746A (en) * | 2019-11-12 | 2020-01-14 | 武汉新芯集成电路制造有限公司 | Exposure auxiliary graph, mask plate and manufacturing method of semiconductor device |
| CN112038239A (en) * | 2020-08-27 | 2020-12-04 | 上海华力集成电路制造有限公司 | Segmented trench formation in integrated circuit processes |
| CN113075866A (en) * | 2021-03-23 | 2021-07-06 | 广东省大湾区集成电路与系统应用研究院 | Method for manufacturing semiconductor device |
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| CN108231793A (en) * | 2018-01-02 | 2018-06-29 | 京东方科技集团股份有限公司 | Method, display base plate and production method, the display device being patterned to conductive film layer |
| CN108231793B (en) * | 2018-01-02 | 2021-01-26 | 京东方科技集团股份有限公司 | Method for patterning conductive film layer, display substrate, manufacturing method and display device |
| CN110658696A (en) * | 2019-09-30 | 2020-01-07 | 上海华力集成电路制造有限公司 | Photoetching friendliness design checking method for disconnection hot spot |
| CN110658696B (en) * | 2019-09-30 | 2021-04-13 | 上海华力集成电路制造有限公司 | Photoetching friendliness design checking method for disconnection hot spot |
| CN110687746A (en) * | 2019-11-12 | 2020-01-14 | 武汉新芯集成电路制造有限公司 | Exposure auxiliary graph, mask plate and manufacturing method of semiconductor device |
| CN110687746B (en) * | 2019-11-12 | 2022-11-18 | 武汉新芯集成电路制造有限公司 | Exposure auxiliary graph, mask plate and manufacturing method of semiconductor device |
| CN112038239A (en) * | 2020-08-27 | 2020-12-04 | 上海华力集成电路制造有限公司 | Segmented trench formation in integrated circuit processes |
| CN112038239B (en) * | 2020-08-27 | 2022-11-29 | 上海华力集成电路制造有限公司 | Segmented trench formation in integrated circuit processes |
| CN113075866A (en) * | 2021-03-23 | 2021-07-06 | 广东省大湾区集成电路与系统应用研究院 | Method for manufacturing semiconductor device |
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