JP2008153373A - Method for manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method for manufacturing a semiconductor device which can obtain desired characteristics without requiring an additional complicated process in a twice development process at a semiconductor lithography step. <P>SOLUTION: The method for manufacturing the semiconductor device includes: a step of forming a processing film on a semiconductor substrate; a step of forming a resist film on the processing film; a first exposure step of irradiating exposure beams on the resist film to expose a first pattern; a first development step of developing either a negative type or positive type in the resist film after the first exposure step; a second exposure step of irradiating the exposure beams on the resist film after the first development step to expose a second pattern; and a second development step of conducting a development different from the first development step of either the negative type or positive type in the resist film after the second exposure step. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a lithography technique which is one of semiconductor device manufacturing techniques, and more particularly to a semiconductor device manufacturing method according to a pattern forming method of a semiconductor device.

  In recent years, pattern dimensions in the development of semiconductor integrated circuits have been increasingly miniaturized. Up to now, miniaturization has been promoted by optical lithography technology, and it is thought that acceleration of miniaturization will continue for a while.

  With the miniaturization of semiconductor elements, high resolution is demanded in the lithography process, and the wavelength of exposure light to be used is shortened and the NA of projection lenses is increased. In optical lithography, an ArF excimer laser (wavelength: 193 nm) has been widely used as an exposure light source, but an F2 laser (wavelength: 157 nm) has been expected as a next-generation exposure light source.

  However, in lithography using an F2 laser, there are many development issues for both the exposure apparatus and the resist material, and recently, immersion exposure technology has gradually attracted attention instead of this. This is a technique for increasing the effective resolution by increasing the effective NA by filling the space between the projection lens and the resist film with liquid (mainly water) instead of conventional air.

  A number of successful examples of using the immersion exposure technique for forming a fine resist pattern have been reported and its usefulness has been shown. However, there are many technical problems, and there is a problem that the total cost of the exposure apparatus and the resist process is significantly increased as compared with the conventional process.

  On the other hand, it is not dependent only on the performance of the exposure apparatus, but a method of obtaining a high dimensional accuracy using a reversal pattern by devising a resist process (see, for example, Patent Document 1 and Patent Document 2). There has been proposed a method of raising the limit resolution by devising the resist characteristics and development process.

  As a method of forming a pattern pitch finer than the pattern pitch that can be formed by normal lithography by devising the resist characteristics and development process, for example, by using a resist having both positive and negative dissolution characteristics, resolution is achieved. Has been proposed (see, for example, Patent Document 3). In addition, by performing a two-time development process consisting of a development process with a developer exhibiting positive development characteristics and a development process with a developer exhibiting negative development characteristics after exposure, the resolution is the same as in the previous example. Has been disclosed (see, for example, Patent Document 4 and Non-Patent Document 1).

  These two-time development (double cycle) processes can repeatedly form patterns of the same size below the limit resolution of the exposure apparatus, so that the cost can be reduced. However, in principle, a closed loop resist pattern is formed, and this closed loop pattern is often unnecessary. Therefore, there is a problem that a process for cutting the closed loop pattern is further required and the process cost is increased.

In general, an integrated circuit pattern is formed not only from the minimum line width but also from patterns having various line widths. That is, the characteristic of repeatedly forming the same size pattern in the two-time development process is a disadvantage in forming a complicated integrated circuit pattern. Accordingly, it is necessary to construct a process for forming a pattern size having a minimum line width by a two-time development process and further forming a pattern other than the minimum line width.
JP 2001-343757 A JP 2002-110510 A JP-A-8-250395 JP 2000-199953 A Japanese Journal of Applied Physics Vol.38 (1999) pp.6999-7003

  The present invention provides a method for manufacturing a semiconductor device in which desired characteristics can be obtained without requiring addition of a complicated process in a double development process in a semiconductor lithography process.

  A method of manufacturing a semiconductor device according to a first aspect of the present invention includes a step of forming a film to be processed on a semiconductor substrate, a step of forming a resist film on the film to be processed, and an exposure beam on the resist film. A first exposure step of exposing the first pattern by irradiating the first pattern, a first development step of performing either negative type or positive type development on the resist film after the first exposure step, A second exposure step of further irradiating the resist film with an exposure beam after the first development step to expose the second pattern; and a negative type or a positive type on the resist film after the second exposure step. A second development step for performing development different from any of the first development steps.

  A method of manufacturing a semiconductor device according to a second aspect of the present invention includes a step of forming a film to be processed on a semiconductor substrate, a step of forming a resist film on the film to be processed, and an exposure beam on the resist film. An exposure step of exposing the pattern by irradiating the resist, a first development step of developing either a negative type or a positive type on the resist film after the exposure step, and the resist after the first development step A second development step in which the film is developed differently from the first development step of either a negative type or a positive type, and the resist film is not present after the second development step. Forming an etching mask material, and etching the film to be processed using the etching mask material as a mask.

  According to a third aspect of the present invention, there is provided a method for manufacturing a semiconductor device, comprising: forming a film to be processed on a semiconductor substrate; forming a first resist film on the film to be processed; A first exposure step of irradiating the resist film with an exposure beam to expose the first pattern, and a first or negative development of the resist film after the first exposure step. A second development step in which, after the first development step, a development different from the first development step of either a negative type or a positive type is performed on the resist film, and the second development step A step of curing the first resist film after the step, a step of forming a second resist film on the first resist film after the step of performing the curing treatment, and the second resist Irradiating the film with an exposure beam to form a second pattern A second exposure step for exposure; a third development step for developing the second resist film after the second exposure step; and the first and second resists after the third development step. A step of forming an etching mask material on the film to be processed on which no film exists, and a step of etching the film to be processed using the etching mask material as a mask.

  According to the present invention, it is possible to provide a method for manufacturing a semiconductor device in which desired characteristics can be obtained without requiring addition of a complicated process in the twice development process in the semiconductor lithography process.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

(First embodiment)
A process flow of the method for manufacturing a semiconductor device according to the first embodiment of the present invention is shown below.

  In this embodiment, a lithography process for forming an element isolation pattern of a NAND flash memory will be described as an example. FIG. 1 shows an element isolation pattern layout of a NAND flash memory created by the semiconductor device manufacturing method according to the present embodiment. 2, 4 and 6 show an exposure mask used in this embodiment. 3, FIG. 5, and FIG. 7 show resist transfer patterns after development after exposure using FIG. 2, FIG. 4, and FIG. 6 as exposure masks, respectively. 8 and 9 are cross-sectional views showing a method for manufacturing a semiconductor device according to this embodiment.

  In this embodiment, the element isolation pattern shown in FIG. 1 is formed by two resist coating processes, three exposure processes, three development processes, and one etching process.

  As shown in FIG. 1, the element isolation pattern of the NAND flash memory has a pattern called the memory cell unit 10 that requires the finest line width and a line width larger than that of the memory cell unit 10 called the peripheral circuit unit 12. Broadly divided into large patterns. In general, the pattern of the memory cell unit 10 is often a simple repetitive pattern such as line and space, and the peripheral circuit unit 12 is an irregular device circuit pattern designed by a device designer.

  First, in order to form a resist pattern of the memory cell portion 10 on the semiconductor processing substrate on which the film to be processed is formed, a first resist coating process and a first exposure process are performed.

  First, as shown in the sectional view of FIG. 8, a film 80 to be processed having an element isolation pattern is formed on the semiconductor processing substrate 1. As the processed film 80 of the element isolation pattern, for example, a silicon oxide film or a silicon nitride film having a thickness of about 100 nm can be considered.

  Next, the semiconductor processing substrate on which the film to be processed is formed is washed, and if necessary, baking before resist coating is performed to improve the adhesion of the resist to the substrate. Thereafter, as shown in FIG. 8, a resist material is applied onto the film 80 to be processed to form the first resist film 30 (first resist application process). Here, a chemically amplified resist (positive type) in which an acid generator contributes to pattern formation is used as the resist material.

  It is important to apply the resist uniformly. Therefore, using a coating device called a spin coater, a resist dissolved in a solvent is dropped while being placed on a rotating table and rotated at a high speed, and spread by centrifugal force to have a uniform thickness. The film thickness of the resist at this time is determined based on the etching resistance of the film to be processed and the required lithography performance (resolution). Therefore, the viscosity of the resist and the rotation speed of the spin coater are adjusted so as to obtain the resist film thickness.

  For example, when a pattern line width of 100 nm or less is formed, the resist film thickness is desirably 300 nm or less, and the rotation speed of the spin coater is set to about 1000 to 4000 rpm. After the resist coating, the pre-exposure baking (pre-baking) is performed at around 100 ° C. in order to volatilize the solvent remaining in the resist film and simultaneously make the film dense.

  Thereafter, in order to form a line and space pattern of the memory cell portion with a resist, the resist is irradiated with a laser beam (exposure beam) through the exposure mask (first pattern) shown in FIG. 2 in which the line and space pattern is formed. (First exposure step). In many cases, an ArF laser (wavelength: 193 nm) is selected as a laser beam for forming a resist pattern of 100 nm or less. As the exposure beam, other light sources such as ultraviolet rays and far ultraviolet rays, or electron beams may be used.

  In this embodiment, a bright field (BF) halftone phase shift mask (HT mask) is used as an exposure mask. The bright field mask is a mask in which a design pattern made of a semi-transparent film or a light shielding film is formed on a quartz (Qz) substrate 20. Here, a bright field (BF) halftone phase shift mask (HT mask) is used as an exposure mask, but a COG (Chromium on Glass) mask or a Levenson type phase shift mask is used depending on the required resolution performance. May be.

  Also, the line and space pattern 22 of the exposure mask of FIG. 2 is formed at a pitch twice that of the line and space pattern required for the integrated circuit. The exposure mask used in this exposure process is preferably a mask obtained by correcting an optical proximity effect (OPE) or a process proximity effect (PPE) with a mask pattern. After the exposure, the treated substrate is subjected to post-exposure baking (post exposure baking: PEB) at around 100 ° C. to diffuse the acid generated in the resist.

  After the first exposure process, a first development process is performed. This developing step is a developing step for forming a negative pattern, and dissolves a dark portion where light does not transmit in the resist. That is, if the exposure amount at the position x is E (x), the resist in the region where E (x) is smaller than a certain exposure threshold E2 (E (x) <E2) is dissolved.

  For example, an organic developer is used as the developer at this time. Examples of the organic developer include a mixed solvent of anisole and methyl isobutyl ketone (MIBK). An example of the rinse solution after development is anisole.

  A pattern after development with this organic developer is shown in FIG. Since the darker region (E (x) <E2) in the region not exposed to light is dissolved by the pattern surface of the exposure mask shown in FIG. 2, the region thinner than the pattern surface is dissolved and the dissolved region 301 is dissolved. A closed loop of the resist pattern 30 is formed.

  After the first development step, exposure for cutting this closed loop, which is an unnecessary pattern, is performed (second exposure step). As shown in FIG. 4, the mask pattern 42 (second pattern) used for cutting the closed loop is translucent so that light is irradiated to the line end portion of the line and space portion formed in the first exposure step. An opening pattern 42 is formed by opening a window in the film.

  In this embodiment, a dark field (DF) halftone phase shift mask (HT mask) is used as an exposure mask. The dark field mask is a mask having a structure in which a quartz (Qz) substrate is entirely covered with a light-shielding film or a semi-transparent film 40, and a design pattern includes an opening through which light is transmitted. Here, a dark field (DF) halftone phase shift mask (HT mask) is used as an exposure mask, but other masks may be used depending on the required resolution performance.

  The exposure mask used in this exposure step is also preferably a mask in which an optical proximity effect (OPE) or a process proximity effect (PPE) is corrected with a mask pattern. As the exposure light, the same laser beam used in the first exposure step may be used. However, since the pattern size of the second exposure process is larger than that of the first exposure process, exposure light having a wavelength longer than that of the first exposure process may be used.

  After the second exposure step, a second development step is performed. This developing process is a developing process for forming a positive pattern, and dissolves a bright portion through which light has passed in the resist. That is, the resist in the region (E (x)> E1) where the exposure amount E (x) is larger than the constant exposure threshold E1 (E1> E2) is dissolved.

  As the developer at this time, for example, an alkali developer is used. For example, tetramethylammonium hydroxide (TMAH) is used as the alkaline developer, and deionized water is used as the rinse after development.

  After the second development step, in the memory cell portion, as shown in FIG. 5, the transmitted light region (E2 <E (x) <E1) between the bright portion and the dark portion corresponding to the edge portion of the mask pattern. Only the resist pattern 30 is formed. The line and space pattern of the memory cell portion at this time has a half pitch of the mask pattern which is below the resolution limit of lithography, and is formed in a form in which each one is separated, not a closed loop pattern.

  In general, a resist pattern formed through the second development step often has a line dimension <a space dimension. This is because it is difficult to form the space width required by the design dimension in the first and second development steps. Therefore, when the resist pattern is required so that the line dimension and the space dimension are equal, a step of thickening the resist pattern 30 is performed after the second development step. In this embodiment, for example, a relaxation process is performed as this process. However, a thermal flow process, a sapphire process, a baking process, addition of a chemical solution, or the like may be used. The resist pattern 30 for the memory cell unit 10 is formed through the steps up to here.

  Thereafter, a resist coating process (second resist coating process) is further performed to form a peripheral circuit pattern. However, if another resist is applied immediately after the formation of the resist pattern 30 for the memory cell portion 10, a phenomenon of mixing in which the line-and-space resist pattern 30 and the resist material to be applied are mixed occurs. Then, the already formed resist pattern 30 is lost.

  In order to prevent such a mixing phenomenon, a line and space resist pattern 30 already formed before the second resist coating process may be cured. As the curing process of the resist film 30, a resist modification process such as a baking process, an ion implantation process, a light ashing process (ashing process), or a UV (ultraviolet) irradiation process is performed. When emphasis is placed on the controllability of resist dimensions, ion implantation is preferable.

  After the first resist film 30 is cured, a second resist coating process (another resist film) 90 is formed thereon by applying a second resist coating process thereon, as shown in FIG. As the resist material applied here, a chemically amplified resist (positive type) in which an acid generator contributes to pattern formation is used.

  Further, since it is important to apply the resist uniformly, a coating apparatus called a spin coater is used as in the first resist coating process. The resist film thickness at this time is also determined from the etching resistance of the film to be processed, the required lithography performance (resolution), and the like, and the resist viscosity and the spin coater rotation speed are adjusted so as to obtain the resist film thickness.

  For example, when a pattern line width of 100 nm or less is formed, the resist film thickness is desirably 300 nm or less, and the rotation speed of the spin coater is set to about 1000 to 4000 rpm. After the resist coating, the pre-exposure baking (pre-baking) is performed at around 100 ° C. in order to volatilize the solvent remaining in the resist film and simultaneously make the film dense.

  Thereafter, a third exposure process for forming a peripheral circuit pattern is performed. The resist is irradiated with a laser beam (exposure beam) through the exposure mask (third pattern) shown in FIG. 6 in which the peripheral circuit pattern is formed. Further, here, a bright field (BF) halftone phase shift mask (HT mask) is used as an exposure mask, but other masks may be used according to the required resolution performance.

  At this time, a pattern is not formed in the region corresponding to the memory cell portion on the transparent substrate so that the exposure light is transmitted through the entire region of the memory cell portion. The exposure mask used in this exposure step is also preferably a mask in which the optical proximity effect (OPE) or the process proximity effect (PPE) is corrected with a mask pattern. As the exposure light, the same laser beam used in the first exposure step may be used. Alternatively, since the pattern size of the third exposure process is larger than that of the first exposure process, exposure light having a wavelength longer than that of the first exposure process may be used. After the third exposure step, the treated substrate is subjected to post-exposure baking (PEB) at around 100 ° C. to diffuse the acid generated in the resist.

  After the third exposure step, a third development step for forming a positive pattern is performed. This development step dissolves the bright part through which light passes in the resist. As this developer, for example, an alkali developer is used. For example, tetramethylammonium hydroxide (TMAH) or the like is used as the alkaline developer, and deionized water or the like is used as the rinse solution after development.

  Through the third development step, the second resist film 90 deposited on the resist pattern 30 in FIG. 9 is not dissolved. As shown in FIG. 7, the resist pattern 30 corresponding to the memory cell portion has a line-and-space pattern below the resolution limit of lithography separated one by one, and the peripheral circuit portion 72 has a peripheral circuit pattern. , Formed as a resist pattern. Thereafter, the film to be processed is selectively removed by etching, the resist is peeled off, and the post-process pattern for element isolation shown in FIG. 1 is completed.

  As shown in FIG. 10, the conventional two-time development process includes one exposure step and subsequent two development steps. In the first development step, for example, when positive development is performed, as shown in FIG. 11, the relationship between the exposure amount and the film thickness after development is such that the resist film remains below the exposure threshold E1, and the exposure threshold E1. As described above, the resist film disappears. In the second development step, for example, when negative development is performed, the relationship between the exposure amount and the film thickness after development is such that the resist film disappears below the exposure threshold E2, as shown in FIG. 12, and the exposure threshold E2 As described above, the resist film remains. Therefore, the relationship between the exposure amount after two development steps and the film thickness after development is such that the resist film remains in a region where the exposure amount is between exposure threshold values E2 and E1, as shown in FIG. It is like this. That is, the resist corresponding to the edge portion of the photomask remains.

  Therefore, when a layout pattern as shown in FIG. 14 is obtained and exposed using a photomask as shown in FIG. 15, a resist pattern having a closed loop as shown in FIG. 16 is formed according to the conventional two-time development process. End up. In this case, there is a problem that a process for cutting the closed loop pattern is further required, and the process cost increases.

  However, according to this embodiment, a finer pattern pitch is formed in the second development process than in the first development process by inserting an exposure process (second exposure process) between the two development processes. At the same time, a closed loop cut is made. Therefore, a new process for cutting the closed loop pattern is not necessary, and an increase in process cost can be prevented.

(Second Embodiment)
The process flow of the method for manufacturing a semiconductor device according to the second embodiment of the present invention is shown below.

  In the present embodiment as well, as in the first embodiment, a lithography process for forming an element isolation pattern of a NAND flash memory will be described as an example. FIG. 17 shows an exposure mask used in this embodiment, and FIG. 18 shows a resist transfer pattern after development after exposure using the same.

  Also in this embodiment, the element isolation pattern shown in FIG. 1 is formed by two resist coating processes, three exposure processes, three development processes, and one etching process.

  In the present embodiment, a dark field (DF) halftone as shown in FIG. 17 is used as an exposure mask (first pattern) on which a line and space pattern used in the first exposure process is formed, instead of a bright field. The difference from the first embodiment is that a type phase shift mask (HT mask) is used. The dark field mask of FIG. 17 is a mask having a structure in which the entire substrate is covered with a light-shielding film or a semi-transparent film, and the pattern is formed of an opening that transmits light. However, a COG (Chromium on Glass) mask or a Levenson type phase shift mask may be used according to the required resolution performance.

  At this time, the pitch of the line and space pattern of the exposure mask is also formed at a pitch twice the pitch of the line and space pattern required in the integrated circuit. The exposure mask used in this exposure step is preferably a mask in which an optical proximity effect (OPE) or a process proximity effect (PPE) is corrected with a mask pattern. After exposure, the treated substrate is subjected to post-exposure baking (PEB) at around 100 ° C. to diffuse the acid generated in the resist.

  After the first exposure step, a first development step for forming a negative pattern is performed as in the first embodiment. The resist pattern after development with an organic developer is as shown in FIG. In the resist pattern 180 of FIG. 18, the center of each line pattern is strongly exposed. Therefore, after that, when positive development is performed using an alkaline developer as the second development step as in the conventional two-time development process, the center of each line pattern is dissolved and a closed loop is formed. Therefore, also in the present embodiment, as in the first embodiment, after the first development process, exposure for cutting the closed loop is performed using the mask pattern (second pattern) shown in FIG. (Second exposure step). The subsequent steps are the same as those in the first embodiment.

  Also in this embodiment, by inserting an exposure process between the two development processes, a fine pattern pitch is formed in the second development process as compared with the first development process, and at the same time, the closed-loop cutting is performed. As a result, a new process for cutting the closed loop pattern becomes unnecessary, and an increase in process cost can be prevented.

(Third embodiment)
The process flow of the semiconductor device manufacturing method according to the third embodiment of the present invention is shown below.

  This embodiment is an advanced version of the second embodiment (a method using a dark field mask in the first exposure process), and is intended to further reduce the cost compared to the first and second embodiments. .

  Also in this embodiment, as in the first and second embodiments, a lithography process for forming an element isolation pattern of a NAND flash memory will be described as an example. 19 and 21 schematically show an exposure mask used in the present embodiment. FIG. 20 is a diagram in which the cross section of the exposure mask shown in FIG. 19, the transmitted light intensity of the exposure beam with respect to the exposure mask (that is, the exposure amount of the resist), and the cross section of the resist remaining after development after exposure are shown. . FIG. 22 is a diagram showing the cross section of the exposure mask shown in FIG. 21 and the cross section of the resist remaining after development after exposure.

  In this embodiment, the element isolation pattern as shown in FIG. 1 is formed by one resist coating process, two exposure processes, two development processes, and one etching process.

  First, a first resist for forming a resist pattern having a line-and-space with a pitch twice that of the memory cell portion 10 and a resist pattern covering the peripheral circuit portion 12 on the semiconductor processing substrate on which the film to be processed is formed. A coating process and a first exposure process are performed.

  A process film of an element isolation pattern is formed on a semiconductor processing substrate, a resist is applied (first resist application process), and a pre-exposure bake (pre-bake) is performed. It is the same.

  Thereafter, in order to form the line and space pattern of the memory cell unit 10 with a resist, the resist is irradiated with a laser beam (exposure beam) through the exposure mask (first pattern) shown in FIG. 19 in which the line and space pattern is formed. (First exposure step). In many cases, an ArF laser (wavelength: 193 nm) is selected as a laser beam for forming a resist pattern of 100 nm or less. As the exposure beam, other light sources such as ultraviolet rays and far ultraviolet rays, or electron beams may be used.

  In the present embodiment, a dark field (DF) halftone phase shift mask (HT mask) is used as an exposure mask. However, a COG mask or a Levenson type phase shift mask may be used according to the required resolution performance.

  Further, the line and space pattern 190 corresponding to the memory cell portion of the exposure mask of FIG. 19 is formed at a pitch twice that of the line and space pattern required in the integrated circuit.

  Further, when the mask pattern 192 on the region where the peripheral circuit of the exposure mask shown in FIG. 19 is formed is a pattern below the resolution limit, that is, a line-and-space pattern with equal intervals, half pitch (HP) < It is formed so as to satisfy (0.25 × λ / NA). Here, λ is the exposure wavelength, and NA is the lens numerical aperture. The coefficient 0.25 is a coefficient indicating the physical resolution limit of the pattern formation dimension by lithography, and if it is smaller than this, pattern formation by lithography becomes difficult. The dimension of the mask pattern 192 in the peripheral circuit region is adjusted so that the transmitted light intensity, that is, the exposure amount E (x) satisfies E2 <E (x) <E1.

  Further, the exposure mask of FIG. 19 is preferably a mask in which an optical proximity effect (OPE) or a process proximity effect (PPE) is corrected with a mask pattern. After exposure, the treated substrate is subjected to post-exposure baking (PEB) at around 100 ° C. to diffuse the acid generated in the resist.

  After the first exposure step, a first development step for forming a negative pattern is performed in the same manner as in the first and second embodiments. The cross section of the resist pattern after development with an organic developer is as shown in FIG.

  In the resist pattern 200 of the memory cell portion formed by the line and space pattern mask, the dark portion which is shielded from light is dissolved. Further, the resist pattern 202 at the boundary between the memory cell serving as the light transmitting portion and the peripheral circuit, and the resist pattern 204 at the peripheral circuit portion formed with a pattern below the resolution limit are transmitted light intensity, that is, exposure amount E. Since (x) is greater than E2, the resist remains after the first development step.

  After the first development step, exposure for cutting the closed loop and formation of the peripheral circuit pattern are performed by one exposure using the exposure mask (second pattern) shown in FIG. 21 (second exposure step). ). The mask pattern 210 corresponding to the memory cell portion used for cutting the closed loop is a pattern in which a window is opened so that light is irradiated to the line end portion of the memory cell portion 200 formed of the line and space formed in the first exposure process. It has become. The peripheral circuit pattern 212 is a peripheral circuit pattern of an element isolation pattern.

  The exposure mask used in this exposure step is preferably a mask in which an optical proximity effect (OPE) or a process proximity effect (PPE) is corrected with a mask pattern. In this embodiment, a bright field (BF) halftone phase shift mask (HT mask) is used as an exposure mask. However, other masks may be used according to necessary resolution performance.

  As the exposure light, the same laser beam used in the first exposure step may be used. However, since the pattern size of the second exposure process is larger than that of the first exposure process, exposure light having a wavelength longer than that of the first exposure process may be used.

  After the second exposure step, a second development step for forming a positive pattern is performed as in the first and second embodiments. After the second development step, as shown in FIG. 22, in the memory cell portion, only the transmitted light region (E2 <E (x) <E1) between the bright portion and the dark portion corresponding to the mask pattern edge portion. Then, a resist pattern 220 is formed. In the resist pattern 222 of the peripheral circuit portion, the resist of the bright portion (E (x)> E1) through which light is transmitted is dissolved. Further, the resist pattern 202 at the boundary between the memory cell and the peripheral circuit existing in FIG. 20 is dissolved and disappears.

  By this development process, the line and space pattern of the resist pattern 220 in the memory cell portion is formed at a half pitch of the mask pattern that is below the resolution limit of lithography and in a form in which each one is separated instead of a closed loop pattern. Is done. Further, a resist pattern 222 in the peripheral circuit portion is formed at the same time.

  In general, the resist pattern formed through the second development step often has a line dimension <space dimension in the pattern 220 of the memory cell portion. This is because it is difficult to form the space width required by the design dimension in the first and second development steps.

  Therefore, when the resist pattern is required to have the same line size and space size, a step of thickening the resist pattern 220 of the memory cell portion is performed after the second development step. In this embodiment, for example, a relaxation process is performed as this process. However, a thermal flow process, a sapphire process, a baking process, addition of a chemical solution, or the like may be used.

  After the second development step, the film to be processed is selectively removed by etching, the resist is peeled off, and a post-process pattern for element isolation as shown in FIG. 1 is completed.

  In this embodiment, each of the resist coating process, the exposure process, and the development process is reduced by one time compared to the first and second embodiments. Furthermore, since the resist coating process is performed once, there is no need to worry about the mixing phenomenon of the resist material as in the first and second embodiments, so that the resist curing process is also unnecessary. Therefore, according to the present embodiment, it is possible to achieve further cost reduction of the process while realizing pattern formation similar to the first and second embodiments.

  In the first to third embodiments, the first developing process is a negative developing process using an organic developer, and the second developing process is a positive developing process using an alkali developer. However, by reversing the pattern of the exposure mask to be used, positive development processing with an alkaline developer is performed in the first development step, and negative development processing with an organic developer is performed in the second development step. It goes without saying that the same effect can be obtained even if it is executed.

(Fourth embodiment)
A process flow of the method for manufacturing a semiconductor device according to the fourth embodiment of the present invention will be described below.

  In the present embodiment, a description will be given of a lithography process for forming a wiring pattern using Al as a wiring material as an example. FIG. 23 is a schematic diagram showing a configuration of a chip to which a resist pattern is transferred. 24, 25, and 28 to 41 are a cross-sectional view and a top view showing the process flow of the present embodiment. 26 and 27 show an exposure mask used in this embodiment.

  In this embodiment, an Al wiring pattern is formed by two resist coating processes, two exposure processes, three development processes, and one etching process.

  FIG. 23 includes two regions, a memory cell portion 101 formed with a periodic pattern and a peripheral circuit portion 102 formed with an irregular pattern group.

  First, the resist pattern formation of the memory cell unit 101 will be described.

  As shown in FIG. 24, an Al film 240 having a thickness of 400 nm is formed on the surface of the semiconductor substrate 1. Further, an organic solution containing a novolak resin as a main component is applied thereon by a spin coating method, and then heat treatment is performed to form a lower layer film 241 having a thickness of 500 nm. A chemical amplification resist is further applied thereon, followed by pre-exposure baking (pre-baking) for volatilizing the solvent in the resist at 120 ° C. for 60 seconds. A first resist film 242 having a thickness of 150 nm is formed on the lower layer film 241. FIG. 25 is a top view at this time.

  After pre-baking, the wafer was cooled to room temperature and then exposed with an exposure apparatus using an ArF excimer laser (wavelength 193 nm) as a light source (first exposure step). The exposure beam used here may be other light sources such as ultraviolet rays and far ultraviolet rays, or an electron beam.

  At this time, a line-and-space pattern with a half pitch of 100 × M nm (Pm = 200 × M nm) disposed on the exposure mask (first pattern) shown in FIG. 27 is formed on the first resist film 242 at a magnification of 1 / M. Is transcribed. In this embodiment, a halftone phase shift mask (HT mask) 260 having an intensity transmittance of 6% and a phase difference of 180 degrees is used as an exposure mask. FIG. 26 shows a cross-sectional view of the exposure mask shown in FIG. 27 and a graph showing the exposure amount when the light source passes through the mask.

  Thereafter, post-exposure baking (PEB) is performed at 130 ° C. for 90 seconds in order to diffuse the acid generated in the resist. Then, a positive development process (first development process) is performed with an alkali developer containing tetramethylammonium hydroxide (TMAH) as a main component.

  Only the region (E (x)> E1) where the exposure dose E (x) shown in the lower part of FIG. 26 is equal to or greater than E1 is selectively removed, and a first view in which FIG. 28 is a sectional view and FIG. 29 is a top view. A positive pattern 242 of the resist film is formed. The pitch of the pattern here is Pm / M. Here, FIG. 28 is a sectional view taken along the broken line A-A ′ of FIG. 29. The subsequent cross-sectional views are all cross sections along the A-A 'broken line.

  Next, a negative development process (second development process) is performed with an organic developer containing methyl isobutyl ketone (MIBK) as a main component, and an area having an exposure amount of E2 or less is selectively removed. As shown in FIG. 31, a resist pattern 242 having a closed loop with a half pitch of 50 nm, which is a double cycle of the mask pattern of FIG. 27, is formed. That is, the pitch Pw here is Pw = Pm / (2M), where Pm is the pitch of the exposure mask used in the first exposure step, and in this case, Pw = 100 nm.

  Here, positive development processing with an alkaline developer is first performed (first development step), and negative development processing with an organic developer is performed thereafter (second development step). The order may be reversed.

  Next, resist pattern formation in the peripheral circuit portion 102 will be described.

  Before forming the second resist film for forming the resist pattern of the peripheral circuit portion 102, the first resist film 242 is cured by UV curing so as not to be mixed with the first resist pattern. As a method for curing the resist film, a resist modification process such as a baking process, an ion implantation process, and an ashing process may be used in addition to the UV curing process.

  In addition, when the dimension of the resist pattern 242 varies by curing the resist film, the variation amount is obtained in advance, and the resist pattern dimension is determined in consideration of the variation amount in at least one of the exposure process and the development process. It is desirable to control.

  Thereafter, as shown in FIGS. 32 and 33, a second resist film 320 (thickness 220 nm, positive resist) is spun on the memory cell portion 101 and the peripheral circuit portion 102 including the closed-loop resist pattern 242. A film is formed by a coating method. In the top view of FIG. 33, the resist pattern 242 is shown through to facilitate understanding.

  Thereafter, exposure was performed using an ArF excimer laser (wavelength 193 nm) as a light source using a halftone phase shift mask (HT mask) having an intensity transmittance of 6% and a phase difference of 180 degrees as an exposure mask (second pattern) (first pattern). 2 exposure step).

  Further, post-exposure baking (PEB) was performed at 140 ° C. for 90 seconds, followed by positive development with an alkali developer containing tetramethylammonium hydroxide (TMAH) as a main component (third development step). Went. As a result, a pattern of the second resist film 320 is formed on the pattern of the first resist film 242 as shown in FIG.

  In FIG. 35, pattern transfer is performed so that the second resist film 320 opens only a necessary region in the memory cell portion 101 and covers an unnecessary end portion forming the closed loop of the first resist film 242. Has been. In the peripheral circuit portion 102, pattern transfer is performed so that the opening pattern becomes a desired pattern. FIG. 34 is a cross section taken along line A-A ′ of FIG.

  Thereafter, water-soluble silicon as an etching mask material is applied by a spin coating method, and further planarized by a CMP method. As a result, as shown in FIGS. 36 and 37, an etching mask pattern 360 is formed in a gap region (concave portion) where the patterns of the first resist film 242 and the second resist film 320 do not exist.

  Furthermore, as shown in FIGS. 38 and 39, the first resist film 242, the second resist film 320, the lower layer film 241 and the Al film 240 are selected by reactive ion etching using the etching mask pattern 360 as a mask. Etch. The etching mask pattern 360 and the lower layer film 241 were removed, and a desired pattern of the Al film 240 as shown in FIGS. 40 and 41 was formed.

  As described above, in this embodiment, a process of forming a fine pattern by a two-time development process using two types of developers (alkaline developer and organic developer) having different characteristics is combined with a reversal process. And execute. As a result, the exposure process for cutting the closed loop pattern generated in the memory cell part and the exposure process for pattern formation of the peripheral circuit part can be performed simultaneously, and the process cost can be greatly reduced. Become.

  The double development process is a damascene process in which, as described above, a resist having a closed loop shape in which line ends are connected is formed, so that a resist pattern is etched and a wiring pattern is formed by embedding a wiring material or the like therein. On the other hand, the application was relatively easy.

  However, if it is intended to be applied to a non-damascene process in which a film to be processed is processed using a resist pattern as an etching mask, conventionally, an etching process for cutting a region connected at the end of the line is necessary. In the present embodiment, by applying a reversal process to the two-time development process, it is possible to implement the two-time development process to a non-damascene process at a low cost.

  In the present embodiment, after the twice development process for the first resist film, a second resist film is formed, exposed and developed, and a reversal mask is formed in a region where neither the first resist film nor the second resist film exists. Then, etching was performed using the reverse mask as a mask. However, if the formation of the peripheral circuit is not considered, after the two development processes for the first resist film (that is, after the second development process), an inversion mask is immediately applied to the area where the first resist film does not exist. It may be formed. Thereafter, etching is performed using the inversion mask as a mask to form wiring only for the memory cell portion.

  In the present embodiment, water-soluble silicon is used as an etching mask material, but a material containing silicon or metal can also be used. In this embodiment, the etching mask pattern is formed in the gap region (concave portion) where no resist pattern exists by CMP. However, it is also possible to form the mask pattern by wet etching, dry etching, or a combination thereof. . In this embodiment, an Al film is used as a film to be processed, but a silicon oxide film, a silicon nitride film, or the like may be used.

  Furthermore, in the first to fourth embodiments, the organic developing solution is used for the negative developing process and the alkaline developing solution is used for the positive developing process. However, the same type of developing solution is used. By controlling the density, it may be switched to a negative or positive development characteristic.

  As described above, the present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the scope of the invention in the implementation stage. Further, the above embodiments include inventions at various stages, and various inventions can be extracted by appropriately combining a plurality of disclosed constituent elements. For example, even if some constituent requirements are deleted from all the constituent requirements shown in the embodiment, the problem described in the column of the problem to be solved by the invention can be solved, and the effect described in the column of the effect of the invention Can be extracted as an invention.

FIG. 3 is a diagram showing an element isolation pattern layout of the NAND flash memory created by the semiconductor device manufacturing method according to the first embodiment. The figure which shows the pattern of the exposure mask used with the manufacturing method of the semiconductor device which concerns on 1st Embodiment. The figure which shows the resist transfer pattern after the image development after the exposure using the exposure mask of FIG. FIG. 5 is another view showing a pattern of an exposure mask used in the method for manufacturing a semiconductor device according to the first embodiment. The figure which shows the resist transfer pattern after the image development after the exposure using the exposure mask of FIG. FIG. 6 is another view showing a pattern of an exposure mask used in the method for manufacturing a semiconductor device according to the first embodiment. The figure which shows the resist transfer pattern after image development after exposure using the exposure mask of FIG. Sectional drawing which shows the manufacturing method of the semiconductor device which concerns on 1st Embodiment. FIG. 6 is another cross-sectional view showing the method for manufacturing the semiconductor device according to the first embodiment. The figure which shows the flow of the process of the conventional 2 times development process. The figure which shows the relationship between an exposure amount and the film thickness after performing positive type development. The figure which shows the relationship between exposure amount and the film thickness after performing negative type development. The figure which shows the relationship between exposure amount and the film thickness after performing positive type and negative type development. The figure which shows a desired layout pattern. The figure which shows a photomask. The figure which shows the closed loop resist pattern obtained by the conventional 2 times development process using the photomask of FIG. The figure which shows the pattern of the exposure mask used with the manufacturing method of the semiconductor device which concerns on 2nd Embodiment. The figure which shows the resist transfer pattern after the development after the exposure using the exposure mask of FIG. The figure which shows the pattern of the exposure mask used with the manufacturing method of the semiconductor device which concerns on 3rd Embodiment. FIG. 20 is a diagram in which the cross section of the exposure mask shown in FIG. 19, the transmitted light intensity of the exposure beam with respect to the exposure mask (that is, the exposure amount of the resist), and the cross section of the resist remaining after development after exposure are arranged. FIG. 10 is another view showing a pattern of an exposure mask used in the method for manufacturing a semiconductor device according to the third embodiment. FIG. 22 is a diagram showing the cross section of the exposure mask shown in FIG. 21 and the cross section of the resist remaining after development after exposure. The figure which shows the layout of the chip | tip produced with the manufacturing method of the semiconductor device which concerns on 4th Embodiment. Sectional drawing which shows 1 process of the manufacturing method of the semiconductor device which concerns on 4th Embodiment. FIG. 25 is a top view of a step of the method for manufacturing the semiconductor device shown in FIG. 24. The figure which put in order the sectional view which shows the exposure mask pattern used with the manufacturing method of the semiconductor device which concerns on 4th Embodiment, and the graph which showed the exposure amount by this mask. The top view of the exposure mask pattern which FIG. 26 shows. FIG. 25 is a cross-sectional view showing a step of the semiconductor device manufacturing method following the step of FIG. 24; FIG. 29 is a top view of a step of the method for manufacturing the semiconductor device shown in FIG. 28. FIG. 29 is a cross-sectional view showing a step of the semiconductor device manufacturing method following the step of FIG. 28; FIG. 31 is a top view of a step of the method for manufacturing the semiconductor device shown in FIG. 30. FIG. 31 is a cross-sectional view showing a step of the semiconductor device manufacturing method following the step of FIG. 30; FIG. 33 is a top view of a step of the method for manufacturing the semiconductor device shown in FIG. 32. FIG. 33 is a cross-sectional view showing a step of the method of manufacturing a semiconductor device, following the step of FIG. FIG. 35 is a top view of a step of the method for manufacturing the semiconductor device shown in FIG. 34. FIG. 35 is a cross-sectional view showing a step of the semiconductor device manufacturing method following the step of FIG. 34; FIG. 37 is a top view of a step of the method for manufacturing the semiconductor device shown in FIG. 36. FIG. 37 is a cross-sectional view showing a step of the method of manufacturing a semiconductor device, following the step in FIG. 36. FIG. 39 is a top view of a step of the method of manufacturing the semiconductor device shown in FIG. 38. FIG. 39 is a cross-sectional view showing a step of the method of manufacturing a semiconductor device, following the step in FIG. 38. FIG. 41 is a top view of a step of the method for manufacturing the semiconductor device shown in FIG. 40.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Semiconductor substrate 10, 101 ... Memory cell part, 12, 102 ... Peripheral circuit part, 20, 42, 172 ... Quartz (Qz), 22, 40, 170, 260 ... HT mask, 30, 180, 200, 220 ... Resist pattern (film) in memory cell portion, 72, 204, 222... Resist pattern in peripheral circuit portion, 80... Processed film, 90 .. another resist film, 190, 210. , 192, 212 ... exposure mask pattern corresponding to the peripheral circuit portion, 202 ... resist pattern at the boundary between the memory cell and the peripheral circuit, 240 ... Al film, 241 ... lower layer film, 242 ... first resist film, 320 ... first 2 resist film, 360... Etching mask pattern, 301, 302.

Claims (5)

Forming a film to be processed on a semiconductor substrate;
Forming a resist film on the film to be processed;
A first exposure step of exposing the first pattern by irradiating the resist film with an exposure beam;
A first development step of performing either negative or positive development on the resist film after the first exposure step;
A second exposure step of exposing the second pattern by further irradiating the resist film with an exposure beam after the first development step;
And a second development step of developing the resist film differently from the first development step of either a negative type or a positive type after the second exposure step. Method. A step of curing the resist film after the second development step;
A step of forming another resist film on the resist film after the step of performing the curing treatment;
A third exposure step of exposing the third pattern by irradiating the other resist film with an exposure beam;
The method for manufacturing a semiconductor device according to claim 1, further comprising a third development step of developing the other resist film after the third exposure step. Forming a film to be processed on a semiconductor substrate;
Forming a resist film on the film to be processed;
An exposure step of exposing the resist film to a pattern by irradiating an exposure beam;
A first development step of performing either negative or positive development on the resist film after the exposure step;
A second development step of performing development different from the first development step of either a negative type or a positive type on the resist film after the first development step;
Forming an etching mask material on the film to be processed on which the resist film does not exist after the second development step;
And a step of etching the film to be processed by using the etching mask material as a mask. Forming a film to be processed on a semiconductor substrate;
Forming a first resist film on the film to be processed;
A first exposure step of exposing the first pattern by irradiating the first resist film with an exposure beam;
A first development step of performing either negative or positive development on the resist film after the first exposure step;
A second development step of performing development different from the first development step of either a negative type or a positive type on the resist film after the first development step;
A step of curing the first resist film after the second development step;
A step of forming a second resist film on the first resist film after the step of performing the curing treatment;
A second exposure step of exposing the second pattern by irradiating the second resist film with an exposure beam;
A third development step of developing the second resist film after the second exposure step;
Forming an etching mask material on the film to be processed on which the first and second resist films do not exist after the third developing step;
And a step of etching the film to be processed by using the etching mask material as a mask. 5. The semiconductor according to claim 1, wherein an organic developer is used as a developer in the negative development, and an alkali developer is used as a developer in the positive development. Device manufacturing method.

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