CN104517802B - A kind of method for making semiconductor devices - Google Patents
A kind of method for making semiconductor devices Download PDFInfo
- Publication number
- CN104517802B CN104517802B CN201310459990.0A CN201310459990A CN104517802B CN 104517802 B CN104517802 B CN 104517802B CN 201310459990 A CN201310459990 A CN 201310459990A CN 104517802 B CN104517802 B CN 104517802B
- Authority
- CN
- China
- Prior art keywords
- pattern
- mask version
- design theme
- design
- designed
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Abstract
The invention discloses a kind of method for making semiconductor devices, including：Designed mask version is provided, the designed mask version includes multiple Design theme bar patterns；By extending the length of the Design theme bar pattern or the virtual strip pattern of addition auxiliary at the end points of the Design theme bar pattern, and then obtain revised designed mask version；Lithography mask version is made according to the revised designed mask version；Photoetching and etching are carried out to chip using the lithography mask version；Cutting mask plate is needed to use to cut unwanted auxiliary line finally according to design.According to the method for preparing semiconductor devices of the present invention, the problem of lines that solution is produced when carrying out micro- pattern process of silicon semiconductor substrate are easily broken, to ensure being transferred in silicon semiconductor substrate completely of the pattern on mask plate, and then improve the reliability and production efficiency of the semiconductor device structure of preparation.
Description
Technical field
The present invention relates to semiconductor fabrication process, more particularly to a kind of method for making semiconductor devices.
Background technology
With the maturation of semiconductor integrated circuit (IC) industrial technology increasingly, the rapid hair of ultra-large integrated circuit
Exhibition, component size is less and less, the integrated level more and more higher of chip.Because of the high density of device, the requirement of small size is half-and-half led
Body technology influence also becomes increasingly conspicuous.In existing advanced technologies（In less than 28 nanometers technology generations）, with the key of pattern
The size of size, i.e. pattern reduces, the raising of the speed of semiconductor devices, the integrated level enhancing of semiconductor devices, in micro- pattern
Chemical industry skill（micro-patterning process）During be easy to produce lines break（Poly line pinch）'s
Problem, the problem influences the performance and yield rate of semiconductor devices.
Micro-patterning technique is that, by exposing multiple copies to the silicon chip for scribbling photoresist, photoetching shows the figure on light shield
Figure on movie queen's light shield is appeared on silicon chip.The figure needed for one or more chips, silicon chip table are contained on one light shield
Photoresist is coated with face, exposure process is that the ultraviolet light or DUV that LASER Light Source is sent pass through the light shield of alignment, exposure
Purpose be the final graphics figure on light shield being accurately copied on photoresist.Finally according to final on photoresist
Figure uses appropriate lithographic method etching silicon wafer, to form the silicon chip with targeted graphical, then, removes photoresist layer.
The micro-patterning technique generally used in the prior art is to form the silicon chip with targeted graphical, specific step
For step a can include some device architectures there is provided silicon semiconductor substrate, the silicon semiconductor substrate；Step b, in semiconductor lining
Photoresist is coated on bottom；Step c, by the mask plate comprising circuit pattern（Such as Fig. 2A）It is placed in above photoresist；Step d, through exposing
Formed after the techniques such as photodevelopment to should circuit pattern photoetching agent pattern；Step e, is detected using after development（ADI）Crucial chi
It is very little（CD）（Such as Fig. 2 B）, the size of ADI critical sizes directly affects the critical size of subsequent step；Step f, according to patterning
Photoresist layer etches silicon semiconductor substrate, to form circuit in silicon semiconductor substrate；Step g, is detected using after etching（AEI）
The circuit formed in silicon semiconductor substrate（Such as Fig. 2 C）.
But the method for prior art is the problem of can have certain, the circuit formed in silicon semiconductor substrate has lines
The problem of breaking, the factor for causing the problem is not only poor lithographic process window, can also be and is produced in etching process
Raw tensile stress（tensile stress）.Because the tensile stress to lines will produce extra power, this will cause online
The relatively narrower that bar becomes produces the problem of lines are broken simultaneously（Such as Fig. 2 C）.
At present, amendment is closed on using optics in order to be proposed the problem of allowing solution lines to break（OPC）Increase the chi of lines
It is very little.Face Ji effect to compensate optics, the designer of light shield can utilize computerized algorithm, small characteristic size on light shield is generated
Optics closes on amendment, carries out the figure of optics amendment, the increase of its size.But it is due to that current optics closes on correction model（OPC
model）It is used primarily in photoetching process, optics closes on correction model and combines optical model（optical model）And photoetching
Rubber moulding type（resist model）, so being closed in the integrality aspect optics for ensuring pattern transfer needed for amendment can not reach
It is required that.
Accordingly, it would be desirable to a kind of new method, to solve the line produced when carrying out micro- pattern process of silicon semiconductor substrate
The problem of bar is easily broken.
The content of the invention
A series of concept of reduced forms is introduced in Summary, this will enter in embodiment part
One step is described in detail.The Summary of the present invention is not meant to attempt to limit technical scheme claimed
Key feature and essential features, the protection domain for attempting to determine technical scheme claimed is not meant that more.
In order to effectively solve the above problems, the present invention proposes a kind of method for making semiconductor device structure, including under
Row step：Designed mask version is provided, the designed mask version includes multiple Design theme bar patterns；By extending the design master
The length of line image or the virtual strip pattern of addition auxiliary at the end points of the Design theme bar pattern, and then corrected
Designed mask version afterwards；Lithography mask version is made according to the revised designed mask version；Use the lithography mask version pair
Chip carries out photoetching and etching.
Preferably, the length for extending the Design theme bar pattern can not influence neighbouring other layouts.
Preferably, the length of extension is less than or equal to 1 micron.
Preferably, it is additionally included in after photoetching is carried out to chip and is etched using the lithography mask version, is covered using cutting
Film version carries out the step of photoetching and etching to the chip.
Preferably, the cutting mask plate is needed to use to cut unwanted auxiliary line according to design.
Preferably, the length of the remaining virtual strip pattern of auxiliary is less than or equal to 0.2 micron.
According to the method for preparing semiconductor devices of the present invention, the generation when silicon semiconductor substrate carries out micro-patterning is solved
Lines the problem of break, to ensure being transferred in silicon semiconductor substrate completely of the pattern on mask plate, and then improve system
The reliability and production efficiency of standby semiconductor device structure.
Brief description of the drawings
The drawings below of the present invention is used to understand the present invention in this as the part of the present invention.Shown in the drawings of this hair
Bright embodiment and its description, for explaining the principle of the present invention.In the accompanying drawings,
Fig. 1 is the process chart for carrying out micro-patterning technique to carrying out silicon semiconductor substrate according to prior art；
Fig. 2A -2C are the schematic diagram for carrying out micro-patterning technique to carrying out silicon semiconductor substrate according to prior art；
Fig. 3 A-3D are to carry out micro-patterning technique to carrying out silicon semiconductor substrate according to an embodiment of the invention
Schematic diagram；
It is the work for carrying out micro-patterning technique to carrying out silicon semiconductor substrate according to an embodiment of the invention that Fig. 4, which is,
Skill flow chart.
Embodiment
In the following description, a large amount of concrete details are given to provide more thorough understanding of the invention.So
And, it will be apparent to one skilled in the art that the present invention can be able to without one or more of these details
Implement.In other examples, in order to avoid obscuring with the present invention, do not enter for some technical characteristics well known in the art
Row description.
In order to thoroughly understand the present invention, detailed step will be proposed in following description, so as to illustrate the present invention be as
What, which is improved, makes the technique of semiconductor device structure to solve the problems of the prior art.Obviously, execution of the invention is not limited
The specific details being familiar with due to the technical staff of semiconductor applications.Presently preferred embodiments of the present invention is described in detail as follows, but
In addition to these detailed descriptions, the present invention can also have other embodiment.
It should be appreciated that when using term "comprising" and/or " comprising " in this manual, it is indicated in the presence of described
Feature, entirety, step, operation, element and/or component, but do not preclude the presence or addition of other one or more features, entirety,
Step, operation, element, component and/or combinations thereof.
In order to solve the problems of the prior art, the present invention proposes a kind of preparation method of semiconductor devices.Reference picture
3A to Fig. 3 D, shows the schematic diagram of the correlation step of embodiment according to one aspect of the invention.
3A-3D is described in detail to the embodiment of the present invention below in conjunction with the accompanying drawings.Reference picture 3A to Fig. 3 D, shows
Go out the schematic diagram of the correlation step of embodiment according to one aspect of the invention.
As shown in Figure 3A, need to be related to the designed mask version 300 with circuit pattern according to technique, specifically, mask plate
For forming Design theme bar in silicon semiconductor substrate or chip.The designed mask version includes multiple Design theme bar figures
Case.Due to the not equal factor of the corresponding circuit of Design theme bar pattern in manufacturing process node difference or designed mask version,
The length and width of Design theme bar pattern need to need setting according to actual process.Wherein, Design theme bar pattern is used for structure
Main device architecture is connected or formed into the main circuit in semiconductor devices.
As shown in Figure 3 B, Design theme bar in extension designed mask version 300（main line）The length of pattern or in institute
The virtual strip pattern of addition auxiliary at the end points of Design theme bar pattern is stated, and then obtains revised designed mask version 301；
In the embodiment of the present invention, the end of the Design theme bar pattern in designed mask version 300
The A additions virtual strip pattern 301a of auxiliary at point, specifically, the end of the Design theme bar pattern in designed mask version 300
The virtual strip pattern 301a of auxiliary of compression stress is added at point on A to form revised designed mask version 301, virtual strip
Pattern 301a extends the length of Design theme bar pattern in designed mask version 300, to avoid losing according to designed mask carving
Chip or Semiconductor substrate formation design lines when, due to lines by tensile stress influence finally in silicon semiconductor substrate
The pattern of upper formation, acting on for the tensile stress that lines are subject to is removed to realize.
In another embodiment of the present invention, extension designed mask version on Design theme bar pattern length with
Design theme bar pattern after being extended, and then revised designed mask version 301 is obtained, in extending design mask plate 300
In the technical process of upper Design theme bar pattern length, the length of extension is less than or equal to 1 micron, also, is set described in extension
Other layouts that the length of main line image can not influence to close on are counted, if for example, the Design theme bar pattern of extension
Length it is long by influence its around pattern design so that extension Design theme bar pattern around other design drawing crimes
It is raw to change or inaccurate, the design of final influence device pattern.That is added at the end points of the Design theme bar pattern is auxiliary
Dummy pattern 301a length is helped to be less than or equal to 0.2 micron.
As shown in Figure 3 C, the pattern of revised designed mask version 301 is transferred on mask plate, to form patterning
Mask plate 302.
The pattern of the mask of the patterning is transferred on the mask layer on chip by photoetching process, it is generally described
Mask layer can include any one of several mask materials, include but is not limited to：Hard mask material and photoresist mask material.
Preferably, mask layer includes photoresist mask material.Photoresist mask material can include selected from include positive-tone photo glue material,
Other substrate materials in the group of negative photo glue material and mixing Other substrate materials.Generally, mask layer includes having thickness from big
About 500 to about 5000 angstroms of positive-tone photo glue material or negative photo glue material.In an embodiment of the present invention, according to amendment
Designed mask version afterwards makes lithography mask version, and chip or Semiconductor substrate are etched using the lithography mask version.
In the embodiment of the present invention, bottom antireflective coating and photoresist are formed in silicon semiconductor substrate
Layer, according to the light that the revised reticle pattern of correspondence is formed after the techniques such as the exposed development of designed lithography mask version
Photoresist pattern.
Then, Semiconductor substrate or chip are performed etching according to mask layer, the pattern on lithography mask version is turned
Move on in Semiconductor substrate.
Semiconductor substrate may include any semi-conducting material, and this semi-conducting material may include but be not limited to：Si、SiC、
SiGe, SiGeC, Ge alloy, GeAs, InAs, InP, and other III-V or group Ⅱ-Ⅵ compound semiconductor.
Preferably, the thickness that the Semiconductor substrate is Si material layers is 10-100nm, preferably 30-50nm.
In the embodiment of the present invention, Semiconductor substrate or chip are carved according to lithography mask version
Erosion, to form polysilicon lines.
Dry etching Semiconductor substrate can be used, traditional deep dry etch process, such as reactive ion etching, ion beam are carved
Erosion, plasma etching, any combination of laser ablation or these methods.Single lithographic method can be used, or also may be used
To use more than one lithographic method.
After carrying out photoetching and etching to chip or Semiconductor substrate using the lithography mask version, also including the use of cutting
Cut the step of mask plate carries out photoetching and etching to the chip or Semiconductor substrate.
At the end points of Design theme bar pattern in designed mask version 300 the addition virtual strip pattern of auxiliary or
The length of the main line image of polysilicon forms revised designed mask version 301 in extension designed mask version 300, then by after amendment
The pattern of designed mask version 301 be transferred to 302 on lithography mask version, it is brilliant then according to the photoetching of lithography mask version 302 and etching
After piece, remove the virtual strip pattern of auxiliary of part to obtain the Design theme bar design drawing using cutting mask plate 303
Case.
The length of the last remaining virtual strip pattern of auxiliary is less than or equal to 0.2 micron.Specifically, according to design need
Cutting mask plate 303 is used to cut unwanted auxiliary line and polysilicon lines below.
Detected after being performed etching to the polysilicon lines 304 ultimately formed, do not find exist in polysilicon lines after detection
Have line width narrow or occur lines break the problem of.
As shown in figure 4, carrying out micro-patterning technique to carrying out silicon semiconductor substrate according to an embodiment of the invention
Process chart
Step 401：Designed mask version is provided；
Step 402：By the length or the end points in the Design theme bar pattern that extend the Design theme bar pattern
The virtual strip pattern of place's addition auxiliary, and then obtain revised designed mask version；
Step 403：The pattern of revised designed mask version is transferred on lithography mask version, according to lithography mask version light
Carve and etching chip；
Step 403：Unwanted auxiliary line and polysilicon lines below are cut using cutting mask；
Step 405：Perform and detected after etching.
The present invention is illustrated by above-described embodiment, but it is to be understood that, above-described embodiment is only intended to
Citing and the purpose of explanation, and be not intended to limit the invention in described scope of embodiments.In addition people in the art
Member according to the teachings of the present invention it is understood that the invention is not limited in above-described embodiment, can also make more kinds of
Variants and modifications, these variants and modifications are all fallen within scope of the present invention.
Claims (6)
1. a kind of method for making semiconductor devices, including：
Designed mask version is provided, the designed mask version includes multiple Design theme bar patterns；
By extending the length of the Design theme bar pattern or the addition auxiliary void at the end points of the Design theme bar pattern
Intend strip pattern, and then obtain revised designed mask version, the tensile stress that Design theme bar pattern is subject to is removed to realize
Effect；
Lithography mask version is made according to the revised designed mask version；
Photoetching and etching are carried out to chip using the lithography mask version, by the Design theme bar pattern of extending length or
The Design theme bar pattern of the virtual strip pattern of auxiliary and the addition virtual strip pattern of auxiliary is transferred to institute
State on chip.
2. the method as described in claim 1, it is characterised in that the length of the extension Design theme bar pattern can not influence neighbour
Near other layouts.
3. the method as described in claim 1, it is characterised in that the length of extension is less than or equal to 1 micron.
4. the method as described in claim 1, it is characterised in that be additionally included in and light is carried out to chip using the lithography mask version
After carving and etching, the step of photoetching and etching is carried out to the chip using cutting mask plate.
5. method as claimed in claim 4, it is characterised in that need to use the cutting mask plate to cut according to design and be not required to
The auxiliary line wanted.
6. method as claimed in claim 5, it is characterised in that the length of the remaining virtual strip pattern of auxiliary be less than or
Equal to 0.2 micron.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310459990.0A CN104517802B (en) | 2013-09-27 | 2013-09-27 | A kind of method for making semiconductor devices |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310459990.0A CN104517802B (en) | 2013-09-27 | 2013-09-27 | A kind of method for making semiconductor devices |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN104517802A CN104517802A (en) | 2015-04-15 |
| CN104517802B true CN104517802B (en) | 2017-09-01 |
Family
ID=52792948
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201310459990.0A Active CN104517802B (en) | 2013-09-27 | 2013-09-27 | A kind of method for making semiconductor devices |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN104517802B (en) |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108231793B (en) * | 2018-01-02 | 2021-01-26 | 京东方科技集团股份有限公司 | Method for patterning conductive film layer, display substrate, manufacturing method and display device |
| CN110658696B (en) * | 2019-09-30 | 2021-04-13 | 上海华力集成电路制造有限公司 | Photoetching friendliness design checking method for disconnection hot spot |
| CN110687746B (en) * | 2019-11-12 | 2022-11-18 | 武汉新芯集成电路制造有限公司 | Exposure auxiliary graph, mask plate and manufacturing method of semiconductor device |
| CN112038239B (en) * | 2020-08-27 | 2022-11-29 | 上海华力集成电路制造有限公司 | Segmented trench formation in integrated circuit processes |
| CN113075866B (en) * | 2021-03-23 | 2022-09-30 | 广东省大湾区集成电路与系统应用研究院 | Method for manufacturing semiconductor device |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103091972A (en) * | 2011-11-03 | 2013-05-08 | 无锡华润上华科技有限公司 | Lithographic mask |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7632610B2 (en) * | 2004-09-02 | 2009-12-15 | Intel Corporation | Sub-resolution assist features |
| US7906271B2 (en) * | 2007-09-28 | 2011-03-15 | Texas Instruments Incorporated | System and method for making photomasks |
| US8598712B2 (en) * | 2011-06-20 | 2013-12-03 | United Microelectronics Corp. | Semiconductor structure formed by double patterning technique |
-
2013
- 2013-09-27 CN CN201310459990.0A patent/CN104517802B/en active Active
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103091972A (en) * | 2011-11-03 | 2013-05-08 | 无锡华润上华科技有限公司 | Lithographic mask |
Also Published As
| Publication number | Publication date |
|---|---|
| CN104517802A (en) | 2015-04-15 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN104517802B (en) | A kind of method for making semiconductor devices | |
| TWI380350B (en) | Double patterning strategy for contact hole and trench in photolithography | |
| US20100273321A1 (en) | Wet soluble lithography | |
| JP2007180489A (en) | Method of manufacturing semiconductor element | |
| CN102122113A (en) | Photoetching method | |
| CN106324998B (en) | The forming method of litho pattern | |
| CN106019849A (en) | Patterning Process of a Semiconductor Structure with a Wet Strippable Middle Layer | |
| CN107799402A (en) | The forming method of secondary figure | |
| CN102841499A (en) | Phase-shift photomask fabrication method | |
| JPH11237745A (en) | Photoresist film and method for forming its pattern | |
| JP2008153373A (en) | Method for manufacturing semiconductor device | |
| JP2009239030A (en) | Method of manufacturing semiconductor device | |
| JP2012023242A (en) | Pattern manufacturing method and pattern formed body formed thereby | |
| JP2008142915A (en) | Imprinting mold and its manufacturing method | |
| US8404409B2 (en) | Method and structure for fabricating dark-periphery mask for the manufacture of semiconductor wafers | |
| TW201312647A (en) | Method of forming an etch mask | |
| EP3454121A1 (en) | Method for manufacturing a mask | |
| JP3061790B1 (en) | Mask manufacturing method and pattern forming method | |
| KR100819647B1 (en) | Method of Manufacturing Semiconductor Device | |
| US8338084B2 (en) | Patterning method | |
| CN104766797A (en) | Aluminum etching method | |
| CN103199016A (en) | Process method for preventing occurrence of defects of photoresist in wet etching | |
| KR100602129B1 (en) | Method for forming pattern using multi-level exposure process | |
| KR100924193B1 (en) | Method for manufacturing the semiconductor device | |
| KR20000004485A (en) | Method for forming fine patterns of semiconductor devices |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |