CN101634806A - Method for forming filament wide silicide barrier layer pattern - Google Patents
Method for forming filament wide silicide barrier layer pattern Download PDFInfo
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- CN101634806A CN101634806A CN200910194582A CN200910194582A CN101634806A CN 101634806 A CN101634806 A CN 101634806A CN 200910194582 A CN200910194582 A CN 200910194582A CN 200910194582 A CN200910194582 A CN 200910194582A CN 101634806 A CN101634806 A CN 101634806A
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Abstract
The invention relates to a method for forming a filament wide silicide barrier layer pattern, which comprises the following steps: after an MUV photoresist figure is formed by MUV photoetching, trimming the MUV photoresist figure by combining dry etching so that a line is attenuated; and adopting the trimmed MUV photoresist figure as a barrier layer to etch so as to form the filament wide silicide barrier layer pattern. The invention breaks through the etching limit of MUV photoresist, and extends the application to the technical field of the line width of smaller than 350 nm.
Description
Technical field
The present invention relates to field of semiconductor technology, be specifically related to a kind of filament wide silicide barrier layer pattern formation method.
Background technology
Along with the integrated level of integrated circuit improves constantly, integrated circuit is to sub-micron, the fast development of deep-submicron direction, and its pattern line-width will be more and more thinner also, and this has higher requirement to semiconductor technology.Therefore, become an instant problem to how realizing that the wide pattern of fine rule is furtherd investigate with the new demand that adapts to semiconductor technology.
Photoetching technique (Lithograph) is to realize the key process technology of integrated circuit patterns.In photoetching technique, photosensitive material (photoresist) is coated on the film of substrate, the light of employing and the corresponding wave band of photoresist sensitometric characteristic sees through the mask plate with specific pattern and exposes to the photoresist surface, the corresponding photoresist figure of pattern after developing on formation and the mask plate.In the subsequent technique of integrated circuit, as the restraining barrier film under it is carried out selective etch with this photoresist figure, just the pattern on the mask plate intactly can be transferred on the film of substrate.The pattern line-width of integrated circuit is thin more, require the imaging resolution of photoresist high more, and the wavelength of the imaging resolution of photoresist and exposure light source is inversely proportional to, and therefore, the wavelength that dwindles exposure light source becomes the main path that realizes the wide pattern of fine rule.
At present, along with development of integrated circuits, photoetching technique has experienced the G linear light and has carved (436nm), I linear light quarter (365nm), KrF deep-UV lithography (248nm) and ArF deep-UV lithography development courses such as (193nm).The kind of exposure light source comprises black light (Near Ultra-Violet, NUV), medium ultraviolet light (Mid Ultra-Violet, MUV), deep UV (ultraviolet light) (Deep Ultra-Violet, DUV), X-light (X-Ray) etc. is multiple, and the photoresist supporting with it also is divided into NUV photoresist, MUV photoresist, DUV photoresist, X-X-ray lithography X glue etc.Wherein, the MUV photoresist can be realized the live width of 350～450nm, has ripe relatively technology, can satisfy the making of most of large scale integrated circuit and VLSI (very large scale integrated circuit), yet be subjected to the restriction of wavelength, the live width of 350nm has become the limit of MUV photoetching.By comparison, the DUV photoresist can be realized the wideer pattern of fine rule, be mainly used in the storer production field at present, but the cost of DUV photoetching process is higher relatively and the DUV photoresist is peeled off easily or outwelled in HF solution, have certain process limitation, and the maturity of DUV photoetching process and the too late far away MUV photoetching process of popularization.In view of this, under the situation of the extensive development of current little live width technology, can utilize the MUV photoetching to realize that the wideer application of fine rule just has Practical significance very much for reducing production costs, enhancing productivity.
Summary of the invention
The object of the present invention is to provide a kind of filament wide silicide barrier layer pattern formation method, break through original photolithography limitation of MUV photoresist, its application is extended to live width technical field below the 350nm.
The invention provides a kind of filament wide silicide barrier layer pattern formation method, comprising: silicon substrate is provided and is positioned at silicide barrier layer to be etched on the described silicon substrate; By gluing, medium ultraviolet photoetching, be developed on the described silicide barrier layer to be etched surface and form medium ultraviolet photoresist figure; Repair the side surface of described medium ultraviolet photoresist figure by dry etch process, make the live width of described medium ultraviolet photoresist figure attenuate; As the restraining barrier described silicide barrier layer to be etched is carried out selective etch to form filament wide silicide barrier layer pattern with the medium ultraviolet photoresist figure after the finishing; Remove described medium ultraviolet photoresist figure.
Preferably, described silicide barrier layer material to be etched be silicon oxide or its composition.
Preferably, described silicide barrier layer material to be etched is silicon rich silicon dioxide, silicon dioxide or both compositions.
Preferably, described dry etching is a plasma etching.
Preferably, described plasma etching adopts and contains oxygen plasma.
Preferably, add nitrogen or carbon tetrafluoride or its combination in the oxygen plasma described containing.
Preferably, described selective etch is a wet etching.
Preferably, described wet etching uses the HF dilute solution.
Preferably, the live width of described filament wide silicide barrier layer pattern is smaller or equal to 350nm.
Compared with prior art, the filament wide silicide barrier layer pattern formation method that the present invention proposes, behind MUV photoetching formation MUV photoresist figure, in conjunction with dry etching MUV photoresist figure is repaired so that its live width attenuates, adopt the MUV photoresist figure after repairing to carry out etching to form filament wide silicide barrier layer pattern as the restraining barrier, broken through the photolithography limitation of MUV photoresist, its application has been extended to live width technical field below the 350nm.
Description of drawings
Fig. 1 is the process chart of filament wide silicide barrier layer pattern formation method of the present invention.
Fig. 2 A～Fig. 2 E is the diagrammatic cross-section of each step corresponding construction of the filament wide silicide barrier layer pattern formation method that proposes of one embodiment of the present of invention;
Embodiment
For purpose of the present invention, feature are become apparent, the specific embodiment of the present invention is further described below in conjunction with accompanying drawing.
Mention that in background technology the application of MUV photoresist is subject to its photolithography limitation, and the cost of DUV photoetching process is higher relatively and the DUV photoresist is peeled off easily or outwell in HF solution, has certain process limitation.
Core concept of the present invention is, repairs to form the wideer MUV photoresist figure of fine rule in conjunction with dry etching by the MUV photoetching, forms filament wide silicide barrier layer pattern thereby utilize this MUV photoresist figure to carry out follow-up etching technics as the restraining barrier.
Fig. 1 is the process chart of filament wide silicide barrier layer pattern of the present invention (SAB pattern) formation method, specifically comprises:
Step S10: silicon substrate is provided and is positioned at silicide barrier layer to be etched (SAB layer) on the described silicon substrate;
Step S11: by gluing, MUV photoetching, be developed on the described SAB laminar surface to be etched and form MUV photoresist figure;
Step S12: repair the side surface of described MUV photoresist figure by dry etch process, make the live width of described MUV photoresist figure attenuate;
Step S13: as the restraining barrier described SAB layer to be etched is carried out selective etch to form the wide SAB pattern of fine rule with the MUV photoresist figure after the finishing;
Step S14: remove described MUV photoresist figure.
Diagrammatic cross-section below in conjunction with each step is described in more detail the wide pattern formation of fine rule provided by the invention method, the preferred embodiments of the present invention have wherein been represented, should be appreciated that those skilled in the art can revise the present invention described here, and still realize advantageous effects of the present invention.Therefore following description is not as limitation of the present invention.
Fig. 2 A～Fig. 2 E is the diagrammatic cross-section of each step corresponding construction of the wide pattern of the fine rule formation method that proposes of one embodiment of the present of invention.
At first, silicon substrate 11 is provided and is positioned at SAB layer 12 to be etched on the silicon substrate 11, shown in Fig. 2 A.Silicon substrate 11 can comprise one deck or more multi-layered material and/or pattern, for example raceway groove, doped region, interconnection line etc., and can further comprise device, for example transistor, electric capacity, resistance, diode etc.The material of SAB layer 12 to be etched is oxide or its composition of silicon, further, is silicon rich silicon dioxide, silicon dioxide or both compositions.
Then, coating one deck MUV photoresist on described SAB layer to be etched 12 surface, make described MUV resist exposure and development by mask plate (not shown), on described SAB layer to be etched 12 surface, form MUV photoresist figure 13, shown in Fig. 2 B with predetermined pattern.This with prior art in ripe MUV photoresist process compatible mutually, thereby can reduce production costs.
Next, repair described MUV photoresist figure 13 side surfaces by dry etch process, make the live width of described MUV photoresist figure 13 attenuate, its top also can be trimmed simultaneously, shown in Fig. 2 C.The live width of the MUV photoresist figure 13 after the finishing is smaller or equal to 350nm.In the present embodiment, described dry etch process is a plasma etch process, adopts to contain oxygen plasma, can add nitrogen or carbon tetrafluoride or its combination.Though its top also can be trimmed in the side surface of the described MUV photoresist figure 13 of finishing,, therefore technique effect of the present invention is not had substantial influence because the MUV photoresist is relatively stable in follow-up wet etching step.
Then, as the restraining barrier described SAB layer 12 to be etched is carried out selective etch to form the wide SAB pattern of fine rule 12A, shown in Fig. 2 D with the MUV photoresist figure 13 after the finishing.Preferable, described selective etch is a wet etching, described wet etching uses the HF dilute solution.The live width of the wide SAB pattern of described fine rule 12A is corresponding with the live width of MUV photoresist figure 13 after the finishing, smaller or equal to 350nm.
At last, remove described MUV photoresist figure 13, shown in Fig. 2 E.
Just can on described silicon substrate 11, carry out follow-up silicide formation technology after finishing above-mentioned steps, form silicide, then do not formed silicide by the silicon substrate area of SAB pattern covers in the silicon substrate area that does not have the SAB pattern covers.It is the known technology of those skilled in the art that silicide forms technology, does not repeat them here.
In sum, the filament wide silicide barrier layer pattern formation method that the present invention proposes, behind MUV photoetching formation MUV photoresist figure, in conjunction with dry etching MUV photoresist figure is repaired so that its live width attenuates, adopt the MUV photoresist figure after repairing to carry out etching to form filament wide silicide barrier layer pattern as the restraining barrier, broken through the photolithography limitation of MUV photoresist, its application has been extended to live width technical field below the 350nm.
Obviously, those skilled in the art can carry out various changes and modification to the present invention and not break away from the spirit and scope of the present invention.Like this, if of the present invention these are revised and modification belongs within the scope of claim of the present invention and equivalent technologies thereof, then the present invention also is intended to comprise these changes and modification interior.
Claims (9)
1, a kind of filament wide silicide barrier layer pattern formation method is characterized in that, comprising:
Silicon substrate is provided and is positioned at silicide barrier layer to be etched on the described silicon substrate;
By gluing, medium ultraviolet photoetching, be developed on the described silicide barrier layer to be etched surface and form medium ultraviolet photoresist figure;
Repair the side surface of described medium ultraviolet photoresist figure by dry etch process, make the live width of described medium ultraviolet photoresist figure attenuate;
As the restraining barrier described silicide barrier layer to be etched is carried out selective etch to form filament wide silicide barrier layer pattern with the medium ultraviolet photoresist figure after the finishing;
Remove described medium ultraviolet photoresist figure.
2, the method for claim 1 is characterized in that, oxide or its composition that described silicide barrier layer material to be etched is a silicon.
3, method as claimed in claim 2 is characterized in that, described silicide barrier layer material to be etched is silicon rich silicon dioxide, silicon dioxide or both compositions.
4, the method for claim 1 is characterized in that, described dry etching is a plasma etching.
5, method as claimed in claim 4 is characterized in that, described plasma etching adopts and contains oxygen plasma.
6, method as claimed in claim 5 is characterized in that, add nitrogen or carbon tetrafluoride or its combination described containing in the oxygen plasma.
7, the method for claim 1 is characterized in that, described selective etch is a wet etching.
8, method as claimed in claim 7 is characterized in that, described wet etching uses the HF dilute solution.
9, the method for claim 1 is characterized in that, the live width of described filament wide silicide barrier layer pattern is smaller or equal to 350nm.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200910194582A CN101634806A (en) | 2009-08-25 | 2009-08-25 | Method for forming filament wide silicide barrier layer pattern |
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| CN200910194582A CN101634806A (en) | 2009-08-25 | 2009-08-25 | Method for forming filament wide silicide barrier layer pattern |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102064096A (en) * | 2010-12-03 | 2011-05-18 | 北京大学 | Preparation method of hair line |
| CN102298259A (en) * | 2010-06-22 | 2011-12-28 | 无锡华润上华半导体有限公司 | Photoetching method |
| CN105719955A (en) * | 2016-02-16 | 2016-06-29 | 山东浪潮华光光电子股份有限公司 | Preparation method of GaN-based light-emitting diode chip |
| CN115903401A (en) * | 2022-12-22 | 2023-04-04 | 上海铭锟半导体有限公司 | Super-resolution pattern implementation method and device based on etching and double photoetching |
-
2009
- 2009-08-25 CN CN200910194582A patent/CN101634806A/en active Pending
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102298259A (en) * | 2010-06-22 | 2011-12-28 | 无锡华润上华半导体有限公司 | Photoetching method |
| CN102064096A (en) * | 2010-12-03 | 2011-05-18 | 北京大学 | Preparation method of hair line |
| CN102064096B (en) * | 2010-12-03 | 2012-07-25 | 北京大学 | Preparation method of hair line |
| CN105719955A (en) * | 2016-02-16 | 2016-06-29 | 山东浪潮华光光电子股份有限公司 | Preparation method of GaN-based light-emitting diode chip |
| CN105719955B (en) * | 2016-02-16 | 2018-09-25 | 山东浪潮华光光电子股份有限公司 | A kind of preparation method of GaN base light emitting chip |
| CN115903401A (en) * | 2022-12-22 | 2023-04-04 | 上海铭锟半导体有限公司 | Super-resolution pattern implementation method and device based on etching and double photoetching |
| CN115903401B (en) * | 2022-12-22 | 2024-03-12 | 上海铭锟半导体有限公司 | Super-resolution pattern implementation method and device based on etching and double lithography |
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Application publication date: 20100127 |