CN104506197B - A kind of method for positioning high-speed parallel data stream trigger point position - Google Patents
A kind of method for positioning high-speed parallel data stream trigger point position Download PDFInfo
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- CN104506197B CN104506197B CN201410782032.1A CN201410782032A CN104506197B CN 104506197 B CN104506197 B CN 104506197B CN 201410782032 A CN201410782032 A CN 201410782032A CN 104506197 B CN104506197 B CN 104506197B
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Abstract
The present invention provides a kind of method for positioning high-speed parallel data stream trigger point position, the trigger point position can be directly used, for realizing digital three-dimensional oscillograph.Step 1: be compared parallel data and triggering lower limit with the upper limit simultaneously, the parallel comparative result of two-way is obtained；Step 2: LData is divided into some groups, first by first order grouped data step-by-step "or", the bit whether group has value to be 1 is determined, while determining position of first value for 1 bit；It is grouped again Step 3: the first order to be grouped to the data obtained after step-by-step "or", uses the method for step 2 to find position of first value for 1 bit, the position until the bit that first value is 1 in LData can be determined；Step 4: after finding in LData first value for 1 bit, generating corresponding data mask LDataMask；Step 5: the data mask LDataMask and HData carries out with operation, data mask HDataMask is obtained；It is the position of trigger point in the data flow Step 6: finding the position for the bit that first value is 1 according to the method for step 2 and step 3 to data mask HDataMask.
Description
Technical field
Field, more particularly to a kind of positioning high-speed parallel data are triggered the present invention relates to digital storage oscilloscope data sampling
The method of trigger point position is flowed, for improving waveform exhibit stabilization.
Background technology
High speed digital oscilloscope carries out quantization sampling by high-speed AD converter (ADC) to analog signal, and data are sent
Enter after field programmable gate array (FPGA) is handled and store in memory, read data during display from memory
Feeding display is shown.With continuing to develop for electronic technology, the sample rate requirement of oscillograph reaches several GHz to tens of GHz, but
It is that FPGA does not reach so high processing speed far, it is therefore desirable to which parallel processing is carried out to the data after sampling.Multidiameter delay number
Brought challenges according to stream to high-speed data acquisition triggering system, particularly with digital three-dimensional oscillograph, the realization requirement of high capture rate
Find quickly and accurately trigger position.
One of traditional triggering independent positioning method is based on time interval measurement.As notification number is
CN101719768B, entitled " a kind of pinpoint method in trigger point in multi-ADC parallel high-speed data acquisition system " measurement
The time interval of first synchronised clock rising edge after trigger signal rising edge and triggering, and then determine the position of trigger point.
Test module outside this method needs is aided in, and adds the complexity and cost of circuit, and time required when surveying
The requirement of the digital three-dimensional oscillograph of current high capture rate can not be met.
Others triggering independent positioning method includes the position by trigger point is determined after parallel trigger signal and data syn-chronization.
Such as notification number is CN103199870A, and entitled " a kind of trigger point fast-positioning device " divides after being nursed one's health by analogue data
Two-way is sent to ADC and trigger port, and obtained parallel sampling data and parallel trigger signal send into FPGA and synchronize place simultaneously
Reason, and then determine the position of trigger point.This method needs trigger port circuit, adds the complexity and cost of circuit, and need
Synchronization process is carried out to data flow and triggering stream, increase FPGA design complexity, and there is the probability of error.Notification number is
CN103558434A, entitled " a kind of quick positioning digital oscilloscope trigger point system ", the parallel processing of trigger signal is put
Realized inside FPGA, resynchronisation parallel sampling data flow and parallel trigger signal, and then determine trigger point position.Such a method
Although simplifying trigger port circuit, extra voltage comparator circuit is stilled need, and without the synchronization process for simplifying complexity
, still there is error in logic.
To sum up, finding one kind, can quick and precisely to position high-speed parallel data stream trigger point position particularly important.
The content of the invention
A kind of method for positioning high-speed parallel data stream trigger point position is provided for the problem above present invention, can be direct
Using the trigger point position, for realizing digital three-dimensional oscillograph.
The present invention is realized by following technical scheme：
A kind of method for positioning high-speed parallel data stream trigger point position, comprises the following steps：
Step 1: be compared parallel data and triggering lower limit with the upper limit simultaneously, the comparison knot of two-way parallel is obtained
Really, LData and HData are designated as, result of the comparison bit wide is 20；Wherein LData each represent sample point data stream and touch
Hair band lower limit result of the comparison, puts 1 during less than triggering lower limit, otherwise sets to 0；HData each represent sample point data stream and
Triggering band upper limit result of the comparison, takes more than triggering and puts 1 in limited time, otherwise set to 0；
Step 2: described LData is divided into 10 groups, and every group 2, first by step-by-step "or" inside first order grouped data,
Determine whether the group has value to be 1 bit, while determining the position of the bit that first value is 1 in the group；
Step 3: the first order is grouped into obtained data after step-by-step "or" is divided into 5 groups, and every group 2, using the side of step 2
Method finds the position for the bit that first value is 1；
Find after second level packet step-by-step "or" in obtained data whether promising 1 position, while recording in the group the
The position for the bit that one value is 1；
Step 4: after finding in the LData first value for 1 bit, generating corresponding data mask
LDataMask；
Step 5: the data mask LDataMask carries out with operation with above-mentioned HData, data mask is obtained
HDataMask；
Step 6: finding the ratio that first value is 1 according to the method for step 2 and step 3 to data mask HDataMask
The position of special position, is the position of trigger point in the data flow.
Every group of data in every grade of series being classified in step 3 are no more than 5bit.
Beneficial effects of the present invention：
The method that the present invention quick and precisely positions high-speed parallel data trigger point position solves conventional trigger point location flower
The problem of taking the plenty of time when surveying is, it is necessary to which the problem of trigger port analog circuit, synchronous data flow and Trig control signal are introduced
The problem of error.Digital storage oscilloscope data sampling triggers field, especially needs to realize digital three-dimensional by high capture rate
It is very useful in the field of oscillograph, and cost is low.
Brief description of the drawings
Fig. 1 is the quick structured flowchart for positioning high-speed parallel data stream trigger point position of the present invention；
Fig. 2 is the quick triggering band schematic diagram for positioning high-speed parallel data stream trigger point position of the present invention；
Fig. 3 is the quick streamline schematic diagram for positioning high-speed parallel data stream trigger point position of the present invention.
Embodiment
The invention will be described further below in conjunction with the accompanying drawings.
A kind of method of positioning high-speed parallel data stream trigger point position of the present invention, is implemented including digitized voltage
Comparator, streamline triggering addressed module, are completed inside FPGA.
As shown in figure 1, analog signal is gone here and there simultaneously after being changed into data signal, data signal feeding FPGA after ADC is converted
Conversion, is changed into parallel data stream, under digital dock, and each cycle has some sampled points to need processing, quick and precisely finds tactile
Sending out position includes two aspects, and one is to determine that the data point triggered is located at some cycle of parallel data stream, another
It is which of parallel data stream point under the cycle to be to determine the data point triggered.
Digitized voltage comparator is to judge to meet triggering level by digitized voltage comparator by parallel data stream
It is required that parallel trigger signal.To reduce triggering shake, using the triggering form of triggering band, i.e., the triggering level set user
It is changing into triggering band, including the triggering upper limit and triggering lower limit.Parallel data stream will compare with the triggering upper limit and triggering lower limit respectively
Obtain two groups of trigger signals.As shown in Figure 2.When data are more than the triggering upper limit, 1 is designated as, 0 (HData) is otherwise designated as；Work as data
During less than triggering lower limit, 1 is designated as, otherwise be designated as 0 (LData).
Two-way trigger signal is respectively divided into N groups by streamline triggering addressed module, as shown in figure 3, first being found with N grades of flowing water
The point that first is 1 in LData, i.e., current point is less than triggering lower limit；Then by obtained result generate mask with
HData carries out with operation, obtains HData_Mask, then it is 1 point to find first of HData_Mask with N grades of flowing water, i.e.,
Current point is more than the triggering upper limit, and the point is trigger point.If not having to meet what is required in the HData_Mask data of current period
Point, then directly carry out looking for 1 operation in the next cycle to HData.
After sampled data delay and pipeline series identical beat, sampled data and trigger position can be with one a pair
Should, the high capture rate operation follow-up for realizing.
The ADC of one 5GHz sample rate is sampled (each sampled point 8) to an analog signal, and sampled data is sent
Enter FPGA processing, FPGA can not directly be handled with 5GHz clock, therefore data flow dredging collateral low-voltage differential module reduction of speed is arrived
Handled under 250M clocks, obtain the high-speed parallel data stream of 20 sampled points of each cycle (160).Data flow is sent into voltage ratio
Compared with device module.Assuming that triggering level is 0V, with being represented in binary as 01111111, triggering level is transformed to trigger band, then touched
It is 10000001 to send out the upper limit, and triggering lower limit is 01111101.Data flow is compared with the triggering upper limit and triggering lower limit respectively,
Obtain the HData and LData of 20 bit wides.
Then LData (assuming that 0000_0011_1111_1111_1000) is divided into 3 groups, 2 × 2 × 5.First order flowing water will
LData point is 10 groups, every group 2, find in every group whether promising 1 point, obtained result is (Grouped_Ldata1) 00_
0111_1110, while recording the position (Mask_Interim1) that first is 1 in the group.Second level flowing water is by Grouped_
Ldata1 point is 5 groups, every group 2, find in every group whether promising 1 point, obtained result is (Grouped_Ldata2) 0_
1111, while recording the position (Mask_Interim2) that first is 1 in the group.Third level flowing water finds Grouped_
In Ldata2 whether promising 1 position, while recording the position (Mask_Interim3) that the group first is 1, pass through Mask_
It is 6 that Interim1, Mask_Interim2, Mask_Interim3, which can obtain the position that first is 1 in LData,.And
To data mask (HData_Masked) 0000_0011_1111_1111_1111 for handling HData.By HData and
HData_Masked is carried out after "AND", and obtained data arrive final according to LData processing method after 3 grades of flowing water
Trigger point position.
When in LData not for 1 position, illustrate that current period does not have trigger point.As HData and HData_Masked
When in the data after "AND" not for 1 position, illustrate that current period does not have trigger point, HData_Masked is in the next cycle
Complete 1, i.e., the addressing of trigger point position is directly carried out to HData.After sampled data delay and pipeline series identical beat,
Sampled data and trigger position can be corresponded, the high capture rate operation follow-up for realizing.
The preferred embodiments of the present invention are the foregoing is only, the present invention is not restricted to, for the technology of this area
For personnel, the present invention can have various modifications and variations.Within the spirit and principles of the invention, that is made any repaiies
Change, equivalent substitution, improvement etc., should be included within scope of the presently claimed invention.
Claims (4)
1. a kind of method for positioning high-speed parallel data stream trigger point position, it is characterised in that comprise the following steps：
Step 1: be compared parallel data and triggering lower limit with the upper limit simultaneously, the parallel comparative result of two-way is obtained, is remembered
For LData and HData, result of the comparison bit wide is 20；Wherein LData each represents under sample point data stream and triggering band
Result of the comparison is limited, 1 is put during less than triggering lower limit, otherwise sets to 0；Each expression sample point data stream of HData and triggering band
Upper limit result of the comparison, takes more than triggering and puts 1 in limited time, otherwise set to 0；
Step 2: described LData is divided into 10 groups, and every group 2, first by step-by-step "or" inside first order grouped data, it is determined that
Whether the group has value to be 1 bit, while determining the position of the bit that first value is 1 in the group；
Step 3: the first order is grouped to the data obtained after step-by-step "or" is divided into 5 groups, every group 2, looked for using the method for step 2
To position of first value for 1 bit；
Find after second level packet step-by-step "or" in obtained data whether promising 1 position, while recording in the group first
It is worth the position of the bit for 1；
Step 4: after finding in the LData first value for 1 bit, generating corresponding data mask
LDataMask；
Step 5: the data mask LDataMask carries out with operation with above-mentioned HData, data mask is obtained
HDataMask；
Step 6: finding the bit that first value is 1 according to the method for step 2 and step 3 to data mask HDataMask
Position, be the data flow in trigger point position.
2. a kind of method for positioning high-speed parallel data stream trigger point position as claimed in claim 1, it is characterised in that step
Every group of data in every grade of series being classified in three are no more than 5bit.
3. a kind of method for positioning high-speed parallel data stream trigger point position as claimed in claim 1 or 2, it is characterised in that
Methods described is realized using digitized voltage comparator and streamline triggering addressed module, is completed inside FPGA.
4. a kind of method for positioning high-speed parallel data stream trigger point position as claimed in claim 3, it is characterised in that described
Digitized voltage comparator parallel data stream is judged to meet to the parallel trigger signal of triggering level requirement, i.e., user is set
The triggering level put is changing into triggering band, including the triggering upper limit and triggering lower limit, parallel data stream will respectively with the triggering upper limit and
Triggering lower limit relatively obtains two groups of trigger signals.
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| CN101719768A (en) * | 2009-11-20 | 2010-06-02 | 电子科技大学 | Method for positioning trigger point accurately in multi-ADC parallel high-speed data acquisition system |
| CN103199870A (en) * | 2013-02-28 | 2013-07-10 | 电子科技大学 | Quick positioning device for trigger point |
| CN103558434A (en) * | 2013-11-04 | 2014-02-05 | 南京国睿安泰信科技股份有限公司 | Quick-positioning digital oscilloscope trigger point system |
| CN104077492A (en) * | 2014-07-08 | 2014-10-01 | 中国电子科技集团公司第四十一研究所 | Sample data interpolation method based on FPGA |
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2014
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| US5212485A (en) * | 1990-09-27 | 1993-05-18 | Tektronix, Inc. | Analog oscilloscope digitizer |
| CN101719768A (en) * | 2009-11-20 | 2010-06-02 | 电子科技大学 | Method for positioning trigger point accurately in multi-ADC parallel high-speed data acquisition system |
| CN103199870A (en) * | 2013-02-28 | 2013-07-10 | 电子科技大学 | Quick positioning device for trigger point |
| CN103558434A (en) * | 2013-11-04 | 2014-02-05 | 南京国睿安泰信科技股份有限公司 | Quick-positioning digital oscilloscope trigger point system |
| CN104077492A (en) * | 2014-07-08 | 2014-10-01 | 中国电子科技集团公司第四十一研究所 | Sample data interpolation method based on FPGA |
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