WO2018120612A1

WO2018120612A1 - Data sampling method, chip and computer storage medium

Info

Publication number: WO2018120612A1
Application number: PCT/CN2017/085606
Authority: WO
Inventors: 张亚国
Original assignee: 深圳市中兴微电子技术有限公司
Priority date: 2016-12-28
Filing date: 2017-05-24
Publication date: 2018-07-05
Also published as: CN108255231B; CN108255231A

Abstract

A chip, comprising a controller (10) and an SPI (11) connected to the controller, wherein the controller comprises: a clock generation module (100), an input/output module (101), a configuration acquisition module (102), a clock delay module (103), and a sampling module (104); the clock generation module (100) acquires a current clock signal, generates an output clock signal according to the current clock signal, and outputs the output clock signal to the input/output module (101); the input/output module (101) outputs the output clock signal from the SPI (11) to an SPI Flash, and outputs the output clock signal to the clock delay module (103); the configuration acquisition module (102) acquires a configuration parameter and a delay enable signal, and outputs the configuration parameter and the delay enable signal to the clock delay module (103); the clock delay module (103) generates a sampling clock signal according to the delay enable signal, the output clock signal and the configuration parameter, and outputs the sampling clock signal to the sampling module (104); and the sampling module (104) receives SPI data by means of the SPI (11) and samples the SPI data by means of the sampling clock signal.

Description

Data sampling method, chip and computer storage medium

Cross-reference to related applications

The present application is filed on the basis of the Chinese Patent Application No. 20161123961, filed on Dec.

Technical field

The present invention relates to electronic technologies, and more particularly to a data sampling method, a chip, and a computer storage medium.

Background technique

The Serial Peripheral Interface (SPI) is a high-speed, full-duplex, synchronous communication bus that occupies only four wires on the pins of the chip, saving the pins of the chip and printing. The layout of the printed circuit board (PCB) saves space and provides convenience. Due to the ease of use of SPI, more and more chips integrate this communication protocol. With the increasing use of SPI flash (SPI Flash), the speed is getting higher and higher, the original chip design can not meet the demand of high-speed sampling data, and need to increase the support for high speed, this is because SPI FLASH only has input. Clock, no output clock, the output data is sent to the controller for sampling, the controller samples through the internal clock, because different Flash manufacturers output delay is different, PCB board level introduces delay, and possibly bridge chip introduces more delay This will reduce the stability of the data sampling of the controller in the chip. Figure 1 shows the clock and data path delay of the chip and SPI Flash. As shown in Figure 1, the data path delay of the chip and SPI Flash mainly includes: chip clock output delay, PCB clock trace delay, and particle clock input. Delay, particle data output delay, PCB data trace delay, chip input delay. The existing solutions mainly have the following Two kinds:

(1) Add a loop clock input outside the chip to compensate for the chip's internal output delay and input delay.

(2) Add high frequency clock to sample inside the chip.

In the process of implementing the present invention, the inventors have found that at least the following problems exist in the prior art:

(1) Adding a loop clock outside the chip can only compensate the chip's internal output delay and input delay, but it can't compensate PCB delay and external level shifting chip delay. On the other hand, each Flash manufacturer's particle delay range They are all inconsistent and therefore cannot be accurately compensated.

(2) Add a high-frequency clock inside the chip and sample it through different periods of the high-frequency clock. However, the high frequency clock causes trouble to the clock tree, making the sampling operation cumbersome.

Summary of the invention

The embodiment of the invention provides a data sampling method, a chip and a computer storage medium, which can meet the requirement of sampling SPI data of different rates, realize stable sampling of data, and has the characteristics of strong compatibility and software controllability.

To achieve the above objective, the technical solution of the embodiment of the present invention is implemented as follows:

An embodiment of the present invention provides a chip, where the chip includes: a controller and an SPI connected to the controller, where the controller includes: a clock generation module, an input and output module, a configuration acquisition module, and a clock delay module. a sampling module, the input and output module is connected to the SPI, wherein

The clock generation module is configured to acquire a current clock signal, generate an output clock signal according to the current clock signal, and output the output clock signal to the input/output module;

The input/output module is configured to output the output clock signal to the SPI Flash through the SPI, and output the output clock signal to the clock delay module;

The configuration obtaining module is configured to acquire a configuration parameter and a delay enable signal, and output the configuration parameter and the delay enable signal to the clock delay module;

The clock delay module is configured to generate a sampling clock signal according to the delay enable signal, the output clock signal, and the configuration parameter, and output the sampling clock signal to the sampling module;

The sampling module is configured to receive SPI data through the SPI, and sample the SPI data according to the sampling clock signal.

In an embodiment, the configuration obtaining module is configured to configure a delay line level M, a delay unit level N, and the delay enable signal, and the delay line level M, the delay The unit number of stages N and the delay enable signal are output to the clock delay module; wherein, M and N are both natural numbers greater than or equal to one.

In an embodiment, the clock delay module includes: a first selection module, a second selection module, and a delay module; wherein

The clock delay module is configured to configure a first level according to the delay line level M, the first level is a number of stages of the second selection module, and according to the delay line level M configuring a second level, the second level being the number of stages of the delay module;

a first input end of the first selection module is connected to the input and output module, a second input end of the first selection module is connected to the second selection module, and a third input end of the first selection module Connected to the configuration acquisition module, the output end of the first selection module is connected to the sampling module;

The second selection module is composed of an M-level first selection sub-module; wherein, in the k-th stage, there are 2M-k first selection sub-modules; wherein k is a natural number greater than or equal to 1 and less than or equal to M;

The delay module is composed of a 2M-level delay sub-module.

In an embodiment, if M is equal to 1, the first input of the first selection sub-module of the second selection module is connected to the first-stage delay sub-module; the second input of the first selection sub-module The terminal is connected to the second-stage delay sub-module; the output end of the first selection sub-module is connected to the first selection module.

In an embodiment, if M is greater than 1, for the kth first selection submodule of the second selection module:

When k is equal to 1, the first input end of the ith first selection submodule in the first stage is connected to the 2i-1th delay submodule in the 2M level delay submodule; The second input end of the first selection sub-module is connected to the 2i-th delay sub-module of the 2M-level delay sub-module; when i is an even number, the output end of the i-th first selection sub-module Connected to the i/2th first selection submodule of the second stage, or when i is an odd number, the output of the i th first selection submodule and the (i+1)/2 of the second stage The first selection sub-modules are connected; wherein i is a natural number greater than or equal to 1 and less than or equal to 2M;

When k is greater than 1 and less than M, the first input end of the jth first selection submodule in the kth stage is connected to the 2j-1 first selection submodule in the k-1th stage; The second input end of the j first selection sub-modules is connected to the 2j first selection sub-module in the k-1th stage; when j is an even number, the output end of the j-th first selection sub-module The j/2th first selection submodule in the k+1th stage is connected, or when j is an odd number, the output of the jth first selection submodule and the (k+th)th 1)/2 first selection sub-modules are connected; wherein j is a natural number greater than or equal to 1 and less than or equal to 2M-k;

When k is equal to M, the first input of the first selection submodule in the Mth stage is connected to the first first selection submodule of the M-1th stage; the second input of the first selection submodule The terminal is connected to the second first selection submodule in the M-1th stage; the output end of the first selection submodule is connected to the first selection module.

In an embodiment, the delay sub-module includes: a third selection module and a registration module; wherein

The clock delay module is configured to configure a third level according to the delay unit number N, the third level is a number of stages of the third selection module, and according to the delay unit level N configuring a fourth level, the fourth level being the number of stages of the registration module;

The third selection module is composed of an N-level second selection sub-module; wherein, in the h-th stage, there are 2M-h second selection sub-modules; wherein h is a natural number greater than or equal to 1 and less than or equal to N;

The registration module is composed of a 2N-level registration sub-module.

In an embodiment, if N is equal to 1, the first input end of the second selection sub-module of the third selection module is connected to the first-level registration sub-module; the second input end of the second selection sub-module Connected to the second level storage submodule; the output end of the second selection submodule is connected to the second selection module;

In an embodiment, if N is greater than 1, for the second selection sub-module of the h-th level in the third selection module:

When h is equal to 1, the first input end of the pth second selection submodule in the first stage is connected to the 2p-1 level registration submodule in the 2N level register submodule; The second input end of the second selection sub-module is connected to the second p-level registration sub-module of the 2N-level registration sub-module; when p is an even number, the output end of the p-th second selection sub-module a second p/2 second selection module, or an output of the pth second selection submodule and a (p+1)/2 second selection of the second level when p is an odd number a submodule connection; wherein p is a natural number greater than or equal to 1 and less than or equal to 2N;

When h is greater than 1 and less than N, the first input end of the qth second selection submodule in the hth stage is connected with the 2q-1 second selection submodule in the h-1th stage; The second input end of the q second selection sub-modules is connected to the 2q second second selection sub-module in the h-1th stage; when q is an even number, the output end of the q-th second selection sub-module The q/2th second selection submodule in the h+1th stage, or the output of the qth second selection submodule and the (h+)th in the h+1th level when q is an odd number 1)/2 second selection sub-modules are connected; wherein q is a natural number greater than or equal to 1 and less than or equal to 2N-h;

When h is equal to N, the first input of the second selection sub-module in the Nth stage is connected to the first second selection sub-module of the N-1th stage; the second input of the second selection sub-module End and The second second selection sub-module of the N-1 stage is connected; the output end of the second selection sub-module is connected to the second selection module.

In an embodiment, the first selection submodule and the second selection submodule are selectors;

The registration sub-module is a register.

The embodiment of the invention further provides a data sampling method, the method comprising:

Acquiring a current clock signal, and generating an output clock signal according to the current clock signal;

Obtaining a configuration parameter and a delay enable signal, and generating a sampling clock signal according to the delay enable signal, the output clock signal, and the configuration parameter;

The SPI data is received, and the SPI data is sampled by the sampling clock signal.

In an embodiment, the configuration parameter includes a delay line level M and a delay unit level N; wherein M and N are both natural numbers greater than or equal to 1.

In an embodiment, before the receiving the SPI data, the method further includes:

Acquiring preset verification data, sampling the preset verification data by using the sampling clock signal, and obtaining verification sampling data;

Determining, according to the sampling data and the check sampling data, whether the configuration parameter meets a preset rule, and if the configuration parameter satisfies the preset rule, sampling the SPI data.

In an embodiment, the determining, according to the sampling data and the check sampling data, whether the configuration parameter meets a preset rule, further includes:

If the configuration parameter does not meet the preset rule, the configuration parameter is adjusted until the adjusted configuration parameter meets the preset rule.

In an embodiment, the adjusting the configuration parameter includes:

The delay line level M and the delay unit level N are adjusted according to a preset method.

In an embodiment, after the obtaining the sampling data, the method further includes:

Outputting the sampled data to a register;

When the read request is obtained, the sampled data is read according to a preset clock domain to obtain updated sample data;

The updated sampled data is used.

The embodiment of the invention further provides a computer storage medium, wherein the computer storage medium stores computer executable instructions, and the computer executable instructions are used to execute the data sampling method according to the embodiment of the invention.

Therefore, in the technical solution of the embodiment of the present invention, the current clock signal is acquired, an output clock signal is generated according to the current clock signal, and the configuration parameter and the delay enable signal are acquired, according to the delay enable signal, the output clock signal, and the configuration. The parameter generates a sampling clock signal; receives the SPI data, samples the SPI data by the sampling clock signal, and obtains the sampling data. That is to say, in the technical solution proposed by the present invention, the sampling clock signal can be acquired according to the current clock signal, and then the SPI data is sampled by the sampling clock signal, thereby obtaining sampling data. Obviously, compared with the prior art, the technical solution of the embodiment of the present invention can meet the requirement of sampling SPI data of different rates, realize stable sampling of data, and has the characteristics of strong compatibility and software controllability.

DRAWINGS

Figure 1 is a schematic diagram of the clock and data path delay of the chip and SPI Flash;

2 is a schematic diagram of a first component structure of a chip according to an embodiment of the present invention;

3 is a schematic diagram of chip clock signal transmission in an embodiment of the present invention;

4 is a schematic diagram showing a second component structure of a chip according to an embodiment of the present invention;

FIG. 5 is a schematic diagram of a first connection structure of a clock delay module according to an embodiment of the present invention;

6 is a schematic diagram of a second connection structure of a clock delay module according to an embodiment of the present invention;

FIG. 7 is a schematic structural diagram of a third component of a chip according to an embodiment of the present invention; FIG.

8 is a schematic diagram of a first connection structure of a delay sub-module according to an embodiment of the present invention;

FIG. 9 is a schematic flowchart of an implementation process of a data sampling method according to an embodiment of the present invention; FIG.

10 is a schematic flowchart of an implementation process of a method for verifying configuration parameters according to an embodiment of the present invention;

FIG. 11 is a schematic diagram of a delay of a sampling clock signal according to an embodiment of the present invention.

detailed description

A data sampling method and a chip provided by an embodiment of the present invention are described in detail below with reference to the accompanying drawings.

Embodiment 1

The embodiment of the present invention discloses a chip 1. FIG. 2 is a schematic diagram of a first component structure of a chip according to an embodiment of the present invention. As shown in FIG. 2, the chip 1 includes: a controller 10 and an SPI 11 connected to the controller 10, wherein The controller 10 can generate an output clock by using any one of a single data line, two data lines, and four data lines.

In a specific embodiment of the present invention, the controller 10 includes a clock generation module 100, an input and output module 101, a configuration acquisition module 102, a clock delay module 103, and a sampling module 104. The input and output module 101 is connected to the SPI 11.

The clock generation module 100 is configured to acquire a current clock signal, generate an output clock signal according to the current clock signal, and output the output clock signal to the input/output module 101.

In a specific embodiment of the present invention, the clock generation module 100 can acquire the current clock signal of the current working clock domain, and then generate an output clock signal according to the current clock signal, and output the clock signal to the input/output module 101.

In a specific embodiment of the present invention, since the frequency of the current working clock domain is twice the output clock signal, the clock generating module 100 needs to convert the acquired current clock signal to obtain an output clock signal.

In a specific embodiment of the present invention, the clock generation module 100 may output the output clock signal to the input/output module 101 through any one of a single data line, two data lines, and four data lines.

In a specific embodiment of the present invention, the clock generation module 100 is configured to output the clock signal At the same time as the input/output module 101, a preset enable signal is output to the input/output module 101, and the preset enable signal is used to control whether the input/output module 101 outputs the output clock signal.

The input and output module 101 is configured to output an output clock signal to the SPI Flash through the SPI 11 and output the output clock signal to the clock delay module 103.

In an embodiment of the present invention, after receiving the output clock signal sent by the clock generation module 100, the input and output module 101 can simultaneously output the output clock signal to the SPI Flash and the clock delay module 103. The input/output module 101 outputs an output clock signal through the SPI 11.

In the specific embodiment of the present invention, the input and output module 101 receives the output clock signal sent by the clock generation module 100, and the input and output module 101 further receives the preset enable signal sent by the clock generation module 100. The enable signal is used to control whether the input/output module 101 outputs the output clock signal.

In a specific embodiment of the present invention, when the preset enable signal corresponds to a preset enable signal, the input and output module 101 simultaneously outputs the output clock signal to the SPI Flash and the clock delay module 103; When the enable signal corresponds to a preset off signal, the input/output module 101 will not output the output clock signal.

The configuration obtaining module 102 is configured to acquire configuration parameters and a delay enable signal, and output the configuration parameters and the delay enable signal to the clock delay module 103.

In a specific embodiment of the present invention, after the configuration obtaining module 102 acquires the configuration parameter and the delay enable signal, the configuration parameter and the delay enable signal are output to the clock delay module 103. The configuration parameters and the delay enable signal may be pre-stored in a register in the chip and then sent to the configuration acquisition module 102 by the register.

In a specific embodiment of the present invention, the configuration obtaining module 102 is configured to configure a configuration parameter and a delay enable signal, and output the configuration parameter and the delay enable signal to the clock delay module 103. The configuration parameters include: a delay line level M and a delay unit level N; wherein, M and N are natural numbers greater than or equal to 1.

In a specific embodiment of the present invention, the configuration parameters are used to configure the composition of the clock delay module 103, and the delay enable signal is used to control whether the clock delay module 103 outputs the sampling clock signal.

The clock delay module 103 is configured to generate a sampling clock signal according to the delay enable signal, the output clock signal, and the configuration parameter, and output the sampling clock signal to the sampling module 104.

In a specific embodiment of the present invention, after receiving the output clock signal sent by the input/output module 101, the configuration parameters sent by the configuration acquisition module 102, and the delay enable signal, the clock delay module 103 is enabled according to the delay. The signal, the output clock signal, and the configuration parameters generate a sampling clock signal, and the sampling clock signal is output to the sampling module 104.

The sampling module 104 is configured to receive SPI data through the SPI 11 and sample the SPI data according to the sampling clock signal.

In a specific embodiment of the present invention, after acquiring the sampling clock signal sent by the clock delay module 103, the sampling module 104 can receive the SPI data through the SPI11, and then sample the SPI data according to the sampling clock signal, and finally obtain the sampling data.

3 is a schematic diagram of chip clock signal transmission according to an embodiment of the present invention. As shown in FIG. 3, the clock generation module 100 acquires a current clock signal wclk, generates an output clock signal spi_clk_o, and a preset enable signal spi_clk_oe, and outputs the output clock signal and a pre- An enable signal is provided to the input/output module 101; the input/output module 101 outputs the output clock signal spi_clk_o as a communication synchronous clock signal spi_clk to the SPI Flash through the SPI 11, and outputs the output clock signal spi_clk_o as an input clock signal clk_in to the clock delay module 103. The clock delay module 103 receives the output clock signal sent by the input/output module 101, the configuration parameters M and N sent by the configuration acquisition module 102, and the delay enable signal tapdly_en, according to the delay enable signal and the output clock. Signal and configuration parameters, generate sampling clock signal clk_sample, output sampling clock signal to sampling module 104; sampling module 104 can receive SPI data spi_dat through SPI11, After that, the SPI data is sampled according to the sampling clock signal, and finally the sampling data is obtained, and the sampling data is output to the first-in first-out queue to_fifo.

Embodiment 2

4 is a schematic diagram of a second component structure of a chip according to an embodiment of the present invention. As shown in FIG. 4, the clock delay module 103 includes a first selection module 1030, a second selection module 1031, and a delay module 1032. The module 1031 includes a first selection sub-module 10310, and the delay module 1032 includes a delay sub-module 10320.

In a specific embodiment of the present invention, the clock delay module 103 is configured to configure a first level according to the delay line number M, wherein the first level is the number of stages of the second selection module 1031, and according to The delay line level M is configured with a second level, and the second level is the number of stages of the delay module 1032. For example, when the delay line level M is 3, the clock delay module 103 configures the first level to be 3, and the second level is also set to 3.

In a specific embodiment of the present invention, the second selection module 1031 is composed of an M-level first selection sub-module 10310; wherein, in the k-th stage, there are 2M-k first selection sub-modules 10310; wherein k is greater than or equal to 1 And the natural number is less than or equal to M; the delay module 1032 is composed of the 2M-level delay sub-module 10320.

FIG. 5 is a schematic diagram of a first connection structure of a clock delay module according to an embodiment of the present invention. As shown in FIG. 5, a first input end of the first selection module 1030 is connected to the input/output module 101, and a second selection module 1030 is second. The input end is connected to the second selection module 1031, the third input end of the first selection module 1030 is connected to the configuration acquisition module 102, and the output end of the first selection module 1030 is connected to the sampling module 104.

In a specific embodiment of the present invention, the first selection module 1030 acquires the output clock signal sent by the input and output module 101, and the first selection module 1030 acquires the sampling clock signal sent by the second selection module 1031, and at the same time, the first selection The module 1030 obtains the delay enable signal sent by the configuration acquisition module 102, and the first selection module 1030 selects and outputs the output according to the delay enable signal. The clock signal is output, or the sampling clock signal is output.

In a specific real-time example of the present invention, the delay enable signal sent by the configuration obtaining module 102 is used to control the output of the first selection module 1030. As an implementation manner, the delay enable signal is configured according to the rate of the output clock signal. of.

In a specific embodiment of the present invention, when the rate of the output clock signal is greater than a preset threshold, the delay enable signal may be set to 1, indicating that the first selection module 1030 is controlled to output the sampling clock signal; when the rate of the clock signal is output When the threshold is less than the preset threshold, the delay enable signal may be set to 0, indicating that the first selection module 1030 is controlled to output a clock signal.

FIG. 6 is a schematic diagram of a second connection structure of a clock delay module according to an embodiment of the present invention.

As shown in FIG. 6, when M is equal to 1, that is, the second selection module 1031 is composed of the first-order first selection sub-module 10310, the delay module 1032 is composed of the 2-level delay sub-module 10320. The first input end of the first selection submodule 10310 in the second selection module 1031 is connected to the first stage delay submodule 10320; the second input end of the first selection submodule 10310 is connected to the second stage delay submodule 10320. The output of the first selection sub-module 10310 is coupled to the first selection module 1030.

As shown in FIG. 6 above, when M is greater than 1, that is, the second selection module 1031 is composed of the M-level first selection sub-module 10310, and the delay module 1032 is composed of the 2M-level delay sub-module 10320.

In a specific embodiment of the present invention, for the kth level first selection submodule 10310 in the second selection module 1031:

When k is equal to 1, the first input of the i-th first selection sub-module 10310 in the first stage is connected to the 2i-1-th delay sub-module 10320 in the 2M-stage delay sub-module 10320; the ith The second input end of the first selection sub-module 10310 is connected to the 2i-th delay sub-module 10320 in the 2M-level delay sub-module 10320; when i is an even number, the output of the i-th first selection sub-module 10310 is The i/2th first selection submodule 10310 of the second stage is connected, or when i is an odd number, the output of the i th first selection submodule 10310 and the (i+1)/2th of the second level The first selection sub-module 10310 is connected; wherein i is a natural number greater than or equal to 1 and less than or equal to 2M; when k is greater than 1 and less than M, the first input end of the jth first selection submodule 10310 in the kth stage is connected to the 2j-1 first selection submodule 10310 in the k-1th stage; the jth The second input end of a selection submodule 10310 is connected to the 2jth first selection submodule 10310 in the k-1th stage; when j is an even number, the output end of the jth first selection submodule 10310 and the kth The j/2th first selection sub-module 10310 in the +1 level is connected, or when j is an odd number, the output end of the jth first selection sub-module 10310 and the (k+1)th of the k+1th level /2 first selection sub-modules 10310 are connected; wherein j is a natural number greater than or equal to 1 and less than or equal to 2M-k; when k is equal to M, the first input end of the first selection sub-module 10310 in the M-th stage The first first selection sub-module 10310 in the M-1 level is connected; the second input end of the first selection sub-module 10310 is connected to the second first selection sub-module 10310 in the M-1th stage; The output of the sub-module 10310 is coupled to the first selection module 1030.

In a specific embodiment of the present invention, based on the third connection structure diagram of the clock delay module of FIG. 6, for example, when M=3, i=1, j=2, the first first selection in the first stage The first input end of the sub-module 10310 is connected to the first-stage delay sub-module 10320 in the 8-level delay sub-module 10320; the second input end of the first first selection sub-module 10310 and the 8-level delay sub-module 10320 The second stage delay sub-module 10320 is connected; the output of the first first selection sub-module 10310 is connected to the second first selection sub-module 10310 of the second stage; the second first in the second stage The first input of the selection sub-module 10310 is connected to the third first selection sub-module 10310 of the first stage; the second input of the second first selection sub-module 10310 and the fourth of the first level A selection sub-module 10310 is connected; the output of the second first selection sub-module 10310 is connected to the first first selection sub-module 10310 of the third-level; the first input of the first selection sub-module 10310 in the third level The terminal is connected to the first first selection submodule 10310 in the second stage; the first selection submodule 10310 second input terminal of the second stage of the second sub first selection module 10310 is connected; a first output terminal selection sub-module 10310 and the first selection module 1030 is connected.

Embodiment 3

FIG. 7 is a schematic diagram of a third component structure of a chip according to an embodiment of the present invention. As shown in FIG. 7, the delay sub-module 10320 includes a third selection module 103200 and a registration module 103201, wherein the third selection module 103200 includes a second selector. Module 1032000, registration module 103201 includes a registration sub-module 1032010.

In a specific embodiment of the present invention, the clock delay module 103 is configured to configure a third level according to the delay unit level N, wherein the third level is the number of stages of the third selection module 103200, and according to the delay The unit number N configures a fourth level, which is the number of stages of the registration module 103201. For example, when the delay unit number N is 3, the clock delay module 103 configures the number of stages of the third selection module 103200 to be 3, and the number of stages of the configuration registration module 103201 is also 3.

In a specific embodiment of the present invention, the third selection module 103200 is composed of an N-level second selection sub-module 1032000; wherein, in the k-th stage, there are 2N-k second selection sub-modules 1032000; wherein k is greater than or equal to 1 And a natural number less than or equal to M; the registration module 103201 is composed of a 2N-level registration sub-module 1032010.

FIG. 8 is a schematic diagram of a first connection structure of a delay sub-module according to an embodiment of the present invention.

As shown in FIG. 8, when N is equal to 1, that is, the third selection module 10320 is constituted by the 1-stage second selection sub-module 1032000, the registration module 103201 is constituted by the 2-level registration sub-module 1032010. The first input end of the second selection sub-module 1032000 in the third selection module 103200 is connected to the first-level registration sub-module 1032010; the second input end of the second selection sub-module 1032000 is connected to the second-level registration sub-module 1032010; The output of the second selection submodule 1032000 is connected to the second selection module 1031;

As shown in FIG. 8 above, when N is greater than 1, that is, the third selection module 103200 is constituted by the N-level second selection sub-module 1032000, and the registration module 103201 is constituted by the 2N-level registration sub-module 1032010.

In a specific embodiment of the present invention, for the second selection submodule 1032000 in the third selection module 10320:

When h is equal to 1, the first input of the pth second selection submodule 1032000 in the first stage is connected to the 2p-1 level registration submodule 1032010 in the 2N level registration submodule 1032010; the pth second The second input of the selection sub-module 1032000 is connected to the 2p-level registration sub-module 1032010 in the 2N-level registration sub-module 1032010; when p is an even number, the output of the p-th second selection sub-module 1032000 and the second-level The p/2 second selection modules 1032000 are connected, or when p is an odd number, the output of the pth second selection submodule 1032000 and the (p+1)/2 second selection submodules of the second stage 1032000 connection; wherein p is a natural number greater than or equal to 1 and less than or equal to 2N; when h is greater than 1 and less than N, the first input end and the h-1th of the qth second selection submodule 1032000 in the hth stage The 2q-1 second selection sub-modules 1032000 in the stage are connected; the second input end of the qth second selection sub-module 1032000 is connected to the 2qth second selection sub-module 1032000 in the h-1th level; When q is an even number, the output of the qth second selection submodule 1032000 and the q/2th second selection submodule 1 of the h+1th stage 032000 is connected, or when q is an odd number, the output of the qth second selection sub-module 1032000 is connected to the (q+1)/2 second selection sub-module 1032000 in the h+1th stage; , q is a natural number greater than or equal to 1 and less than or equal to 2N-h; when h is equal to N, the first input end of the second selection sub-module 1032000 in the Nth stage and the first second of the N-1th stage The selection sub-module 1032000 is connected; the second input end of the second selection sub-module 1032000 is connected to the second second selection sub-module 1032000 in the N-1th stage; the output end of the second selection sub-module 1032000 and the second selection module 1031 connection.

In a specific embodiment of the present invention, based on the first connection structure diagram of the delay sub-module of FIG. 8 above, for example, when N=3, p=1, q=2, the first one in the first stage The first input end of the second selection sub-module 1032000 is connected to the first-level registration sub-module 1032010 in the 8-level registration sub-module 1032010; the second input end of the first second selection sub-module 1032000 and the 8-level registration sub-module 1032010 The second level storage sub-module 1032010 is connected; the output of the first second selection sub-module 1032000 is connected to the first second selection sub-module 1032000 of the second level; The first input of the second second selection sub-module 1032000 in the second stage is coupled to the third second selection sub-module 1032000 in the first stage; the second input of the second second selection sub-module 1032000 Connected to the fourth second selection sub-module 1032000 in the first stage; the output of the second second selection sub-module 1032000 is connected to the first second selection sub-module 1032000 in the third stage; The first input of the second selection sub-module 1032000 is coupled to the first second selection sub-module 1032000 of the second stage; the second input of the second selection sub-module 1032000 and the second of the second level The second selection sub-module 1032000 is connected; the output end of the second selection sub-module 1032000 is connected to the second selection module 1031.

In an embodiment of the present invention, as an embodiment, the first selection sub-module 10310 and the second selection sub-module 1032000 may be selectors, and the registration sub-module 1032010 may be a register.

In the chip of the embodiment of the present invention, the chip includes: a controller and an SPI connected to the controller, wherein the controller includes: a clock generation module, an input and output module, a configuration acquisition module, a clock delay module, and a sampling module. The input and output modules are connected to the SPI. The clock generation module is configured to acquire a current clock signal, generate an output clock signal according to the current clock signal, and output the output clock signal to the input/output module; the input/output module is configured to output the output clock signal to the SPI Flash through the SPI, and output the output The clock signal is output to the clock delay module; the configuration acquisition module is configured to obtain the configuration parameter and the delay enable signal, and output the configuration parameter and the delay enable signal to the clock delay module; the clock delay module is configured to be based on the delay The signal, the output clock signal and the configuration parameters generate a sampling clock signal, and the sampling clock signal is output to the sampling module; the sampling module is configured to receive the SPI data through the SPI, and sample the SPI data according to the sampling clock signal. In the technical solution proposed by the present invention, the sampling clock signal can be obtained according to the current clock signal, and then the SPI data is sampled by the sampling clock signal, thereby obtaining sampling data. Obviously, compared with the prior art, a data sampling method and a chip proposed by the embodiments of the present invention can meet the requirement of sampling SPI data of different rates, and realize data stabilization. Fixed sampling, with strong compatibility and software controllable features; and, it is simple and convenient to implement, easy to popularize, and has a wider application range.

Embodiment 4

FIG. 9 is a schematic flowchart of an implementation of a data sampling method according to an embodiment of the present invention. As shown in FIG. 9 , in a specific embodiment of the present invention, a method for data sampling specifically includes the following steps:

Step 101: Acquire a current clock signal, and generate an output clock signal according to the current clock signal.

In a specific embodiment of the invention, the controller may acquire a current clock signal of the current working clock domain and then generate an output clock signal according to the current clock signal.

In a specific embodiment of the present invention, since the frequency of the current working clock domain is twice the output clock signal, the controller needs to convert the acquired current clock signal to obtain an output clock signal.

In a specific embodiment of the present invention, the controller may output the output clock signal by any one of a single data line, two data lines, and four data lines.

In a specific embodiment of the present invention, the controller generates the output clock signal and also generates a preset enable signal for controlling whether to output the output clock signal.

In a specific embodiment of the present invention, when the preset enable signal corresponds to a preset turn-on signal, the controller outputs the output clock signal; when the preset enable signal corresponds to a preset turn-off signal, the control The output clock signal will not be output.

Step 102: Acquire a configuration parameter and a delay enable signal, and generate a sampling clock signal according to the delay enable signal, the output clock signal, and the configuration parameter.

In a specific embodiment of the present invention, the controller may acquire a configuration parameter and a delay enable signal, and generate a sampling clock signal according to the delay enable signal, the output clock signal, and the configuration parameter. Wherein, the configuration parameters and the delay enable signal can be pre-stored in a register in the chip, and then registered The device is sent to the controller.

In a specific embodiment of the present invention, the configuration parameters include: a delay line level M and a delay unit level N; wherein, M and N are both natural numbers greater than or equal to 1.

In a specific embodiment of the invention, the configuration parameters are used to configure the generation of the sampling clock signal, and the delay enable signal is used to control the output of the sampling clock signal.

Step 103: Receive SPI data, sample the SPI data by using a sampling clock signal, and obtain sampling data.

In a specific embodiment of the present invention, after acquiring the sampling clock signal sent by the clock delay module 103, the controller may receive the SPI data through the SPI, and then sample the SPI data according to the sampling clock signal, and finally obtain the sampling data.

As shown in FIG. 9 above, after the sampling data is obtained, the data sampling method proposed by the specific embodiment of the present invention further includes the following steps:

Step 104: Output the sampled data to a register.

Step 105: When acquiring a read request, reading the sampled data according to a preset clock domain to obtain updated sample data;

Step 106, using the updated sample data.

In a specific embodiment of the present invention, the controller may synchronize the sampled data obtained by sampling the SPI data into a preset clock domain for reading, thereby obtaining updated sample data, and finally performing the next update data. Level of processing and use.

Embodiment 5

10 is a schematic flowchart of a method for verifying configuration parameters in an embodiment of the present invention. As shown in FIG. 10, in a specific embodiment of the present invention, a method for verifying configuration parameters specifically includes the following steps:

Step 201: Acquire preset verification data, and sample preset calibration data by using a sampling clock signal to obtain verification sampling data.

In a specific embodiment of the invention, the controller obtains a preset school before receiving the SPI data. The data is verified, and the preset verification data is sampled by the sampling clock signal to obtain the verification sampling data.

In a specific embodiment of the present invention, before the controller samples the SPI data, the configuration parameter needs to be verified to determine whether the configuration parameter can be configured to satisfy the sampling requirement of the sampling requirement. The method for verifying the configuration parameters by the controller may be: acquiring preset verification data, sampling the preset verification data by using the sampling clock signal, and obtaining verification sampling data.

Step 202: Determine, according to the sampling data and the verification sampling data, whether the configuration parameter satisfies a preset rule. If the configuration parameter satisfies the preset rule, the SPI data is sampled.

In a specific embodiment of the present invention, after obtaining the verification sampling data according to the configuration parameter, the controller may determine, according to the sampling data and the verification sampling data, whether the configuration parameter satisfies a preset rule, and if the configuration parameter satisfies the preset rule, The SPI data is sampled.

In a specific embodiment of the present invention, after acquiring the verification sampling data, the controller compares the verification sampling data with the verification data to obtain a comparison result, and the controller may determine, according to the comparison, whether the preset rule is met, if the , the above configuration parameters can be considered to meet the preset requirements of the data sampling, and the sampling signal can be configured according to the above configuration parameters.

As shown in FIG. 10 above, the method for verifying configuration parameters further includes:

Step 203: If the configuration parameter does not meet the preset rule, the configuration parameter is adjusted until the adjusted configuration parameter meets the preset rule.

In a specific embodiment of the present invention, if the configuration parameter does not satisfy the preset rule, the controller adjusts the configuration parameter, generates a sampling signal according to the adjusted configuration parameter, and then resamples the sampled data until the adjusted configuration. The parameters satisfy the preset rules.

In a specific embodiment of the present invention, when the comparison result of the verification sampling data and the verification data does not satisfy the preset rule, the controller may adjust the configuration parameter according to the preset method, that is, the controller may perform the preset method according to the preset method. The delay line level M and the delay unit level N are adjusted.

FIG. 11 is a schematic diagram of a delay of a sampling clock signal according to an embodiment of the present invention. As shown in FIG. 11 , in the case of not delaying the sampling clock signal in (a), the sampling clock signal can satisfy the sampling time. The order relationship, just on the rising edge of clk_sample, can just sample spi_datX (X can be 1, 2 or 4 bits). Since the phase of spi_datX in (b) is shifted later than the phase of (a), if the clk_in is not delayed, it is impossible to effectively sample spi_datX on the rising edge of clk_sample. Therefore, the delay enable signal tapdly_en and the configuration parameter M need to be configured. N. The spi_datX in (c) moves more backward than the phase of (b), so it is necessary to delay the clk_in more.

The data sampling method provided by the embodiment of the present invention acquires a current clock signal, generates an output clock signal according to the current clock signal, acquires a configuration parameter and a delay enable signal, and generates a sampling according to the delay enable signal, the output clock signal, and the configuration parameter. The clock signal; receiving the SPI data, sampling the SPI data by the sampling clock signal, and obtaining the sampling data. That is to say, in the technical solution proposed by the present invention, the sampling clock signal can be acquired according to the current clock signal, and then the SPI data is sampled by the sampling clock signal, thereby obtaining sampling data. Obviously, compared with the prior art, a data sampling method and a chip proposed by the embodiments of the present invention can meet the requirement of sampling SPI data of different rates, achieve stable sampling of data, have strong compatibility, and are software controllable. The characteristics are; simple, convenient to implement, easy to popularize, and a wider range of applications.

Those skilled in the art will appreciate that embodiments of the present invention can be provided as a method, system, or computer program product. Accordingly, the present invention can take the form of a hardware embodiment, a software embodiment, or a combination of software and hardware. Moreover, the invention can take the form of a computer program product embodied on one or more computer-usable storage media (including but not limited to disk storage and optical storage, etc.) including computer usable program code.

The present invention has been described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (system), and computer program products according to embodiments of the invention. It will be understood that each flow and/or block of the flowchart illustrations and/or FIG. These computer program instructions can be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing device to produce a machine for the execution of instructions for execution by a processor of a computer or other programmable data processing device. Realize A means of function specified in a flow or a flow and/or a block diagram of a block or blocks.

The computer program instructions can also be stored in a computer readable memory that can direct a computer or other programmable data processing device to operate in a particular manner, such that the instructions stored in the computer readable memory produce an article of manufacture comprising the instruction device. The apparatus implements the functions specified in one or more blocks of a flow or a flow and/or block diagram of the flowchart.

These computer program instructions can also be loaded onto a computer or other programmable data processing device such that a series of operational steps are performed on a computer or other programmable device to produce computer-implemented processing for execution on a computer or other programmable device. The instructions provide steps for implementing the functions specified in one or more of the flow or in a block or blocks of a flow diagram.

The above is only the preferred embodiment of the present invention and is not intended to limit the scope of the present invention.

Industrial applicability

The technical solution of the embodiment of the present invention can obtain a sampling clock signal according to a current clock signal, and then sample the SPI data by using the sampling clock signal, thereby obtaining sampling data. Obviously, compared with the prior art, a data sampling method and a chip proposed by the embodiments of the present invention can meet the requirement of sampling SPI data of different rates, achieve stable sampling of data, have strong compatibility, and are software controllable. The characteristics are; simple, convenient to implement, easy to popularize, and a wider range of applications.

Claims

A chip comprising: a controller and a serial peripheral interface SPI connected to the controller, the controller comprising: a clock generation module, an input and output module, a configuration acquisition module, a clock delay module, and sampling a module, the input and output module is connected to the SPI, wherein

The clock generation module is configured to acquire a current clock signal, generate an output clock signal according to the current clock signal, and output the output clock signal to the input/output module;

The input/output module is configured to output the output clock signal to the SPI Flash through the SPI, and output the output clock signal to the clock delay module;

The configuration obtaining module is configured to acquire a configuration parameter and a delay enable signal, and output the configuration parameter and the delay enable signal to the clock delay module;

The clock delay module is configured to generate a sampling clock signal according to the delay enable signal, the output clock signal, and the configuration parameter, and output the sampling clock signal to the sampling module;

The sampling module is configured to receive SPI data through the SPI, and sample the SPI data according to the sampling clock signal.
The chip according to claim 1, wherein

The configuration obtaining module is configured to configure a delay line level M, a delay unit level N, and the delay enable signal, and the delay line level M, the delay unit level N, and The delay enable signal is output to the clock delay module; wherein M and N are both natural numbers greater than or equal to 1.
The chip of claim 2, wherein the clock delay module comprises: a first selection module, a second selection module, and a delay module; wherein

The clock delay module is configured to configure a first level according to the delay line level M, the first level is a number of stages of the second selection module, and according to the delay line level M configuring a second level, the second level being the number of stages of the delay module;

a first input end of the first selection module is connected to the input and output module, a second input end of the first selection module is connected to the second selection module, and a third input end of the first selection module Connected to the configuration acquisition module, the output end of the first selection module is connected to the sampling module;

The second selection module is composed of an M-level first selection sub-module; wherein, in the k-th stage, there are 2M-k first selection sub-modules; wherein k is a natural number greater than or equal to 1 and less than or equal to M;

The delay module is composed of a 2M-level delay sub-module.
The chip according to claim 3, wherein

If M is equal to 1, the first input end of the first selection sub-module of the second selection module is connected to the first-stage delay sub-module; the second input end of the first selection sub-module and the second-order extension The sub-module is connected; the output of the first selection sub-module is connected to the first selection module.
The chip according to claim 3, wherein

If M is greater than 1, for the kth first selection submodule in the second selection module:

When k is equal to 1, the first input end of the ith first selection submodule in the first stage is connected to the 2i-1th delay submodule in the 2M level delay submodule; The second input end of the first selection sub-module is connected to the 2i-th delay sub-module of the 2M-level delay sub-module; when i is an even number, the output end of the i-th first selection sub-module Connected to the i/2th first selection submodule of the second stage, or when i is an odd number, the output of the i th first selection submodule and the (i+1)/2 of the second stage The first selection sub-modules are connected; wherein i is a natural number greater than or equal to 1 and less than or equal to 2M;

When k is greater than 1 and less than M, the first input end of the jth first selection submodule in the kth stage is connected to the 2j-1 first selection submodule in the k-1th stage; The second input end of the j first selection sub-modules is connected to the 2j first selection sub-module in the k-1th stage; when j is an even number, the output end of the j-th first selection sub-module The j/2th first selection submodule in the k+1th stage is connected, or when j is an odd number, the output end of the jth first selection submodule The (j+1)/2th first selection submodule of k+1 level is connected; wherein j is a natural number greater than or equal to 1 and less than or equal to 2M-k;

When k is equal to M, the first input of the first selection submodule in the Mth stage is connected to the first first selection submodule of the M-1th stage; the second input of the first selection submodule The terminal is connected to the second first selection submodule in the M-1th stage; the output end of the first selection submodule is connected to the first selection module.
The chip according to claim 3, wherein the delay sub-module comprises: a third selection module and a registration module; wherein

The clock delay module is configured to configure a third level according to the delay unit number N, the third level is a number of stages of the third selection module, and according to the delay unit level N configuring a fourth level, the fourth level being the number of stages of the registration module;

The third selection module is composed of an N-level second selection sub-module; wherein, in the h-th stage, there are 2M-h second selection sub-modules; wherein h is a natural number greater than or equal to 1 and less than or equal to N;

The registration module is composed of a 2N-level registration sub-module.
The chip according to claim 6, wherein

If N is equal to 1, the first input end of the second selection sub-module of the third selection module is connected to the first-level registration sub-module; the second input end and the second-level storage sub-module of the second selection sub-module a module connection; an output end of the second selection submodule is connected to the second selection module;
The chip according to claim 6, wherein

If N is greater than 1, for the second selection sub-module of the h-th level in the third selection module:

When h is equal to 1, the first input end of the pth second selection submodule in the first stage is connected to the 2p-1 level registration submodule in the 2N level register submodule; The second input end of the second selection sub-module is connected to the second p-level registration sub-module of the 2N-level registration sub-module; when p is an even number, the output end of the p-th second selection sub-module The p/2 second selection modules of the second level, or when the p is an odd number, the transmission of the pth second selection submodule The output is connected to the (p+1)/2 second selection submodules of the second level; wherein p is a natural number greater than or equal to 1 and less than or equal to 2N;

When h is greater than 1 and less than N, the first input end of the qth second selection submodule in the hth stage is connected with the 2q-1 second selection submodule in the h-1th stage; The second input end of the q second selection sub-modules is connected to the 2q second second selection sub-module in the h-1th stage; when q is an even number, the output end of the q-th second selection sub-module The q/2th second selection submodule in the h+1th stage, or the output of the qth second selection submodule and the (h+)th in the h+1th level when q is an odd number 1)/2 second selection sub-modules are connected; wherein q is a natural number greater than or equal to 1 and less than or equal to 2N-h;

When h is equal to N, the first input of the second selection sub-module in the Nth stage is connected to the first second selection sub-module of the N-1th stage; the second input of the second selection sub-module The terminal is connected to the second second selection submodule of the N-1th stage; the output of the second selection submodule is connected to the second selection module.
The chip according to claim 3 or 5, wherein

The first selection submodule and the second selection submodule are selectors;

The registration sub-module is a register.
A data sampling method, the method comprising:

Acquiring a current clock signal, and generating an output clock signal according to the current clock signal;

Obtaining a configuration parameter and a delay enable signal, and generating a sampling clock signal according to the delay enable signal, the output clock signal, and the configuration parameter;

The SPI data is received, and the SPI data is sampled by the sampling clock signal.
The method according to claim 10, wherein said configuration parameter comprises a delay line level number M and a delay unit level number N; wherein M and N are both natural numbers greater than or equal to one.
The method of claim 10, wherein before the receiving the SPI data, the method further comprises:

Acquiring preset verification data, sampling the preset verification data by using the sampling clock signal, and obtaining verification sampling data;

Determining, according to the sampling data and the check sampling data, whether the configuration parameter meets a preset rule, and if the configuration parameter satisfies the preset rule, sampling the SPI data.
The method of claim 12, wherein the method further comprises:

If the configuration parameter does not meet the preset rule, the configuration parameter is adjusted until the adjusted configuration parameter meets the preset rule.
The method of claim 13, wherein the adjusting the configuration parameters comprises:

The delay line level M and the delay unit level N are adjusted according to a preset method.
The method of claim 10, wherein after the obtaining the sampled data, the method further comprises:

Outputting the sampled data to a register;

When the read request is obtained, the sampled data is read according to a preset clock domain to obtain updated sample data;

The updated sampled data is used.
A computer storage medium having stored therein computer executable instructions for performing the data sampling method of any one of claims 10 to 15.