CN102866979A - Synchronous serial interface signal sensor data acquisition device - Google Patents
Synchronous serial interface signal sensor data acquisition device Download PDFInfo
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- CN102866979A CN102866979A CN2012103233697A CN201210323369A CN102866979A CN 102866979 A CN102866979 A CN 102866979A CN 2012103233697 A CN2012103233697 A CN 2012103233697A CN 201210323369 A CN201210323369 A CN 201210323369A CN 102866979 A CN102866979 A CN 102866979A
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Abstract
The invention provides a synchronous serial interface (SSI) signal sensor data acquisition device, which comprises a digital signal processor (DSP) for an executable program, a serial port and controller area network (CAN) driver group module, an electrically erasable programmable read-only memory (EEPROM), a four-path-SSI driver group module and a two-row-needle type universal plugin, wherein control software for controlling an acquisition device to run is stored in a memory of the DSP. The device supplies various working mode options, such as a sampling rate, an SSI signal data acquisition port, the frequency of a synchronous clock signal and a data forwarding interface, to a user, and the user can select the working modes by collocating parameters on line in a manner that external parameter collocation equipment such as a personal computer and an embedded system is connected with a first serial port of a system to send an instruction according to a protocol; and an automatic judgment mechanism of the system can intelligently judge and process system collocation parameters sent by the user.
Description
Technical field
The invention belongs to the data collector technical field, be specifically related to a kind of synchronous serial interface signal transducer data collector.
Background technology
Synchronous serial interface (Synchronous Serial Interface is called for short SSI) signal absolute value encoder is widely used in the technical fields such as numerically-controlled machine, mobile robot and photoelectric follow-up; The device that SSI signal absolute value encoder data are carried out gathering real-time and transmit has become the key equipment in these fields.SSI initiatively sends the synchronizing clock signals of certain frequency by main equipment, realize data transmission with most significant digit to the mode that the sequence synchronization of lowest order transmits data to main equipment from equipment, has very strong transmittability and antijamming capability.Existing SSI signal transducer data collector can have been realized the sensor data acquisition of real-time multichannel SSI signal; But have usually that mode of operation is fixing and the data retransmission interface is single and do not possess the function of user's Configuration Online parameter.
Disclose a kind of denomination of invention such as the Chinese patent literature database and be the patented claim technology of " a kind of peripheral component interconnection harvester of synchronous serial interface signal " (publication number is CN201020529373), this invention belongs to a kind of harvester take the FPGA module as core of SSI signal transducer data collecting field, its technical characterstic is: with the FPGA module as key control unit, one end drives chip with SSI and is connected, and the other end is connected with pci bus through pci bridge chip.The other end that SSI drives chip is connected with four road SSI signal transducers, simultaneously four road SSI signal transducer data is carried out gathering real-time, gathers and is forwarded to industrial computer by pci bus; Fixing mode of operation and single pci data forwarding interface have limited the scope of application of device.
Summary of the invention
In order to satisfy embedded system to diversity and the dirigibility demand of SSI signal transducer data collector, the invention provides a kind of synchronous serial interface signal transducer data collector.
The technical solution used in the present invention is as follows:
But the hardware of the harvester of the Configuration Online of synchronous serial interface signal transducer data of the present invention comprises the dsp processor of executable program, serial ports and CAN driver bank module, erasable and programable memory EEPROM, four road SSI driver bank modules and double pin type general connector; Harvester is take the dsp processor of executable program as core, the private communication interface of dsp processor is connected with CAN driver bank module with serial ports, communicate by letter with the external parameter configuration device with the first serial in the CAN driver bank module by serial ports, dsp processor receives user's system configuration parameter, automatic decision mechanism is carried out intelligent decision and processing to user configured system configuration parameter, returns information; Can be forwarded to outside receiving equipment by second serial or CAN behind the sensing data coding of the SSI signal that gathers; The SPI interface of dsp processor is connected with erasable and programable memory EEPROM, automatically reads the system configuration parameter that is stored among the erasable and programable memory EEPROM and revises the system configuration parameter that is stored among the erasable and programable memory EEPROM; The GPIOA of dsp processor is connected with four road SSI driver bank modules with the GPIOB port, and the other end of four road SSI driver bank modules is connected with the SSI signal transducer by four-wire system SSI signal wire; Produce the synchronizing clock signals of the frequency of user's setting by the data register of software control GPIOA, read chronologically the data of the data register of GPIOB simultaneously, realize the real time data Quick Acquisition.
The control software that is used for the operation of control harvester is arranged on the storer of dsp processor, and control software is carried out following steps:
CPU timer in a initialization dsp processor, GPIO, SCI, CAN and SPI module, the variable in the initialization executable program configures and enables first serial in the dsp processor;
The control cycle sign that b waiting for CPU timer produces is effective, if sign effectively, clear flag changes next step over to;
C judges whether the system configuration parameter modified logo is effective, if indicate invalidly, changes step e over to;
D when modified logo is effective in the c step, clear flag, the reading system configuration parameter, GP configuring IO, SCI, CAN and SPI module are again to the initialization of variable in the executable program;
E sampling period counter adds one;
F judges whether sample counter satisfies limit value, if do not satisfy limit value, changes step l over to;
G sample counter in step f has satisfied limit value, with counter O reset;
H judges whether selected enabling of four road SSI signal data acquisition mouths, does not enable if all have to be selected, and changes step l over to;
I is when having among the step h that SSI signal data acquisition mouth is selected to enable, start the SSI signal data acquisition mouth that is enabled, the data register corresponding positions of control GPIOA produces the synchronizing clock signals of the frequency of user's setting, read chronologically simultaneously the value of the data register corresponding positions of GPIOB, the displacement coding is circulated to and gathers complete end;
J judges that whether second serial or CAN are selected as the data retransmission interface effective, if invalid, changes step l over to;
K encodes to image data and sends according to the agreement of selected communication port when having communication port to be selected as forwarding interface among the step j, is sent end;
What l judged first serial receives whether Data Labels is effective, if invalid, changes step p over to;
M removes and receives Data Labels when receiving that Data Labels is effective among the step l, decodes behind the reading out data, and automatic decision mechanism judges whether data are correct and reasonable, if condition does not satisfy, the modified logo of putting system configuration parameter is invalid, please change step o over to;
When n satisfies when step m conditional, the system configuration parameter of storing in the erasable and programable memory EEPROM is made amendment, the modified logo of juxtaposition system configuration parameter is effective;
O returns information;
Whether the p judgement exits command effective, if effectively, program stops, otherwise changes step b over to.
The present invention has following characteristics: 1. GPIO, the SCI, CAN and the SPI module that take full advantage of on the dsp processor sheet realize the collection of SSI signal transducer data software control mode, data encoding and data retransmission, and system configuration parameter storage and modify feature, hardware configuration is simple; 2. the user is connected the mode Configuration Online parameter that sends instruction by external parameter configuration devices such as personal computer or embedded systems with the system first serial; 3. device provides multiple-working mode to select to use to the user, such as the sampling rate of four different brackets, and one or more SSI signal data acquisition mouths, the frequency of the synchronizing clock signals of five different frequencies, two data forwarding interfaces; 4. automatic decision mechanism is provided, and according to the synchronizing clock signals frequency, serial ports and CAN communication baud rate are subjected to the constraint condition of sampling rate and sensor figure place, and user configured system configuration parameter is carried out intelligent decision and processing, and return information.
Description of drawings
But Fig. 1 is the structural representation of the synchronous serial interface signal transducer data collector of Configuration Online of the present invention;
But Fig. 2 is the synchronous serial interface signal transducer data collector core board schematic diagram of the Configuration Online among the present invention;
But Fig. 3 is the program flow diagram of the synchronous serial interface signal transducer data collector of the Configuration Online among the present invention.
Embodiment
The present invention is described in detail below in conjunction with drawings and Examples.
But Fig. 1 is the structural representation of the synchronous serial interface signal transducer data collector of Configuration Online of the present invention.As shown in Figure 1, but the hardware module of the synchronous serial interface signal transducer data collector 18 of Configuration Online of the present invention comprises the dsp processor 10 of executable program, serial ports and CAN driver bank module 11, erasable and programable memory EEPROM12, the main modular such as four road SSI driver bank modules 13 and double pin type general connector 14.Harvester is take the dsp processor 10 of executable program as core; The private communication interface 110 of dsp processor 10 is connected with CAN driver bank module with serial ports and is connected, communicate by letter with external parameter configuration device 15 with the first serial 111 in the CAN driver bank module 11 by serial ports, receive user configured system configuration parameter, automatic decision mechanism is carried out intelligent decision and processing to user configured system configuration parameter, returns information; Can be forwarded to outside receiving equipment 17 by second serial 112 or CAN113 behind SSI signal transducer 16 data encodings that gather; The SPI120 of dsp processor 10 is connected with erasable and programable memory EEPROM12, automatically reads the system configuration parameter that is stored among the erasable and programable memory EEPROM12 and revises the system configuration parameter that is stored among the erasable and programable memory EEPROM12; The GPIOA of dsp processor 10 is connected with four road SSI driver bank modules 13 with GPIOB130, and the other end of four road SSI driver bank modules 13 is connected with SSI signal transducer 16 by four-wire system SSI signal wire 131; At first A12 ~ A15 pin is set to output interface in the direction register of GPIOA, and B12 in the direction register of GPIOB ~ B15 pin is set to input interface; During data acquisition, data register bit12, bit13, bit14, the bit15 bit timing of GPIOA are put 1 and clear 0 synchronizing clock signals that produces the frequency that the user arranges, read chronologically data register bit12, bit13, the bit14 of GPIOB, the value of bit15 position simultaneously.Harvester adopts double pin type general connector 14 to be connected with outside, and it is more convenient and simple that the user can select connected mode, user to use according to actual needs.
But Fig. 2 is the synchronous serial interface signal transducer data collector core board schematic diagram of the Configuration Online among the present invention.As shown in Figure 2, it is core that DSP core control panel of the present invention adopts the TMS320F2812DSP processor 20 of the 150MHz dominant frequency of TI company, be connected with two MAX2311 serial driver (21,22) and PCA82C250CAN driver 23 respectively by carrying the private communication interface, SCI communicates by letter with 2.0CAN with CAN module realization RS-232 serial ports on the bonding pad.CLK, the SIMO of dsp processor by SPI and SOMI signal data line and model are that the erasable and programable memory EEPROM24 of X25650AF is connected, and read online and revise the system configuration parameter in the erasable and programable memory EEPROM.Be connected with the SSI driver (25,26,27,28) of four MAX490 with GPIOB by GPIOA, GPIOA is as the synchronizing clock signals output interface, GPIOB is as Data Input Interface, according to the requirement of SSI sequential, 12,13,14,15 pins among the software operation GPADAT register control GPIOA produce the synchronous clock pulse signal of user configured frequency, read simultaneously the GPBDAT register of 12 among the GPIOA, 13,14,15 pins and realize the data acquisition of SSI signal transducer.Harvester is connected double pin type general connector 29 realizations of the DIP144-14-40-10 that all passes through 40 pins with all of outside.
But Fig. 3 is the program flow diagram of the synchronous serial interface signal transducer data collector of the Configuration Online among the present invention.As shown in Figure 3, step 30 is system initialization, realizes CPU timer, CAN, SCI, GPIO, SPI and the initialization of outside extended memory interface module to dsp processor, the variable in the initialization executable program, the configuration and enable first serial, delay time a second.Judge at first in step 31 whether the control cycle sign is effective, sign is to be set to effectively by the interrupt service routine that two milliseconds CPU timer produces, if be masked as invalid then the system wait sign is set to effectively, if after being masked as effectively, clear flag enters step 32.Judge in step 32 whether the configuration parameter modified logo is effective, if modified logo is invalid, the parameter of expression system operation is user configured system configuration parameter, then changes step 34 over to; If modified logo is effectively, the expression user reconfigures systematic parameter and this parameter does not also configure to system, and dsp processor will read parameter configuration to system in erasable and programable memory EEPROM in step 33, removes the configuration parameter modified logo.In step 34, the sampling period counter is added one.In step 35, the sampling period parameter that sampling period counter and user are arranged relatively, if counter less than the sampling period parameter, counter satisfies to limit and is masked as invalidly, then changes step 37 over to; If counter equates with the sampling period parameter, counter satisfies to limit and is masked as effectively, then changes step 36 over to.
In step 36, with the sample counter zero clearing.In step 361, judge whether selected enabling of the first acquisition port, if selected not enabling not then changes step 362 over to; If selected enabling, in step 3611, by software timing the value of the bit12 position of the data register of GPIOA is composed 1 or clear 0, produce the synchronizing clock signals of the frequency of user's setting, read chronologically simultaneously the value of bit12 position of the data register of GPIOB, the displacement coding, be circulated to data acquisition complete, change step 362 over to.In step 362, judge whether selected enabling of the second acquisition port, if selected not enabling not then changes step 363 over to; If selected enabling, in step 3621, by software timing the value of the bit13 position of the data register of GPIOA is composed 1 or clear 0, produce the synchronizing clock signals of the frequency of user's setting, read chronologically simultaneously the value of bit13 position of the data register of GPIOB, the displacement coding, be circulated to data acquisition complete, change step 363 over to.In step 363, judge whether selected enabling of the 3rd acquisition port, if selected not enabling not then changes step 364 over to; If selected enabling, in step 3631, by software timing the value of the bit14 position of the data register of GPIOA is composed 1 or clear 0, produce the synchronizing clock signals of the frequency of user's setting, read chronologically simultaneously the value of bit14 position of the data register of GPIOB, the displacement coding, be circulated to data acquisition complete, change step 364 over to.In step 364, judge whether selected enabling of the 4th acquisition port, if selected not enabling not then changes step 365 over to; If selected enabling, in step 3641, by software timing the value of the bit15 position of the data register of GPIOA is composed 1 or clear 0, produce the synchronizing clock signals of the frequency of user's setting, read chronologically simultaneously the value of bit15 position of the data register of GPIOB, the displacement coding, be circulated to data acquisition complete, change step 365 over to.Judge in step 365 whether second serial is selected as data and sends mouth, if not selected, then changes step 3652 over to; If be selected as sending mouth, the data that gather are encoded and transmission according to serial communication protocol, be sent, change step 37 over to.Judge in step 3652 whether CAN is selected as data and sends mouth, if not selected, then changes step 37 over to; If be selected as sending mouth, the data that gather are encoded and transmission according to CAN communication protocol, be sent, change step 37 over to.
At first judging to receive in the first serial buffer zone whether Data Labels is effective in step 37, is invalid if receive Data Labels, then changes step 38 over to; If receiving Data Labels is effectively, expression has serial data to be received and is not processed, removes in step 371 and receives Data Labels, receives and press the protocol analysis data.Automatic decision mechanism judges whether data are correct and reasonable in step 372, if data are incorrect or irrational, will revise the parameter sign and be set to invalid and change step 373 over to; If data are correct and reasonably, revise in step 3721 that system configuration parameter juxtaposition configuration parameter modified logo be effective in the erasable and programable memory EEPROM, change step 373 over to after complete.In step 373, send the parameter sign prompting information of revising.
Whether effective at step 38 determining program exit instruction, if effectively, EOP (end of program) then, otherwise change step 31 over to.
The primitive rule of the automatic decision mechanism among the present invention is: the synchronizing clock signals of low frequency and baud rate only are used for low-frequency sampling rate system, and high frequency sampling rate system can only select CAN as data output interface.
Claims (2)
1. synchronous serial interface signal transducer data collector, it is characterized in that: described harvester comprises the dsp processor (10) of executable program, serial ports and CAN driver bank module (11), erasable and programable memory EEPROM(12), four road SSI driver bank modules (13) and double pin type general connector (14); Harvester is take the dsp processor of executable program as core, the private communication interface (110) of dsp processor is connected 11 with serial ports with CAN driver bank module) be connected, communicate by letter with the external parameter configuration device with the first serial (111) in the CAN driver bank module (11) by serial ports, dsp processor receives user's system configuration parameter, automatic decision mechanism is carried out intelligent decision and processing to user configured system configuration parameter, returns information; Can be by second serial (112) behind the sensing data coding of the SSI signal that gathers or CAN(113) be forwarded to outside receiving equipment; SPI interface (120) and the erasable and programable memory EEPROM(12 of dsp processor) be connected, automatically read and be stored in erasable and programable memory EEPROM(12) in system configuration parameter and modification be stored in erasable and programable memory EEPROM(12) in system configuration parameter; The GPIOA of dsp processor (10) is connected 130 with the GPIOB port) be connected with four road SSI driver bank modules (13), the other end of four road SSI driver bank modules (13) is connected with the SSI signal transducer by four-wire system SSI signal wire (131); Produce the synchronizing clock signals of the frequency of user's setting by the data register of software control GPIOA, read chronologically the data of the data register of GPIOB simultaneously, realize the real time data Quick Acquisition; The control software that is used for the operation of control harvester is stored in the storer of dsp processor (10).
2. harvester according to claim 1, it is characterized in that: the software in the dsp processor of described harvester integrated circuit board may further comprise the steps:
CPU timer in a initialization dsp processor, GPIO, SCI, CAN and SPI module, the variable in the initialization executable program configures and enables first serial in the dsp processor;
The control cycle sign that b waiting for CPU timer produces is effective, if sign effectively, clear flag changes next step over to;
C judges whether the system configuration parameter modified logo is effective, if indicate invalidly, changes step e over to;
D when modified logo is effective in the c step, clear flag, the reading system configuration parameter, GP configuring IO, SCI, CAN and SPI module are again to the initialization of variable in the executable program;
E sampling period counter adds one;
F judges whether sample counter satisfies limit value, if do not satisfy limit value, changes step l over to;
G sample counter in step f has satisfied limit value, with counter O reset;
H judges whether selected enabling of four road SSI signal data acquisition mouths, does not enable if all have to be selected, and changes step l over to;
I is when having among the step h that SSI signal data acquisition mouth is selected to enable, start the SSI signal data acquisition mouth that is enabled, the data register corresponding positions of control GPIOA produces the synchronizing clock signals of the frequency of user's setting, read chronologically simultaneously the value of the data register corresponding positions of GPIOB, the displacement coding is circulated to and gathers complete end;
J judges that whether second serial or CAN are selected as the data retransmission interface effective, if invalid, changes step l over to;
K encodes to image data and sends according to the agreement of selected communication port when having communication port to be selected as forwarding interface among the step j, is sent end;
What l judged first serial receives whether Data Labels is effective, if invalid, changes step p over to;
M removes and receives Data Labels when receiving that Data Labels is effective among the step l, decodes behind the reading out data, and automatic decision mechanism judges whether data are correct and reasonable, if condition does not satisfy, the modified logo of putting system configuration parameter is invalid, please change step o over to;
When n satisfies when step m conditional, the system configuration parameter of storing in the erasable and programable memory EEPROM is made amendment, the modified logo of juxtaposition system configuration parameter is effective;
O returns information;
Whether the p judgement exits command effective, if effectively, program stops, otherwise changes step b over to.
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| CN108111426A (en) * | 2017-12-14 | 2018-06-01 | 迈普通信技术股份有限公司 | Communication device with synchronous serial interface, synchronous serial interface bandwidth synchronization system and method |
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| CN111568424A (en) * | 2020-05-26 | 2020-08-25 | 江苏省肿瘤医院 | Device for synchronizing respiratory motion signals in radiotherapy and using method thereof |
| CN111726186A (en) * | 2019-03-20 | 2020-09-29 | 北京米文动力科技有限公司 | Synchronous configuration method of embedded chip and external equipment and embedded chip |
| CN113259888A (en) * | 2021-04-25 | 2021-08-13 | 黑芝麻智能科技(上海)有限公司 | Sensor configuration method and device, computer equipment and storage medium |
| CN114741343A (en) * | 2022-02-28 | 2022-07-12 | 惠州华阳通用电子有限公司 | Controller port expansion device and method |
| CN115017095A (en) * | 2022-08-05 | 2022-09-06 | 微传智能科技（常州）有限公司 | Current output type AK protocol wheel speed chip communication system and method |
| CN113259888B (en) * | 2021-04-25 | 2024-04-30 | 黑芝麻智能科技(上海)有限公司 | Sensor configuration method, device, computer equipment and storage medium |
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| CN105278553A (en) * | 2015-10-13 | 2016-01-27 | 华中科技大学 | Dual-controller synchronization contour control method |
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| CN108111426B (en) * | 2017-12-14 | 2021-06-08 | 迈普通信技术股份有限公司 | Communication device with synchronous serial port, synchronous serial port bandwidth synchronization system and method |
| TWI698123B (en) * | 2018-07-26 | 2020-07-01 | 大陸商深圳市愛協生科技有限公司 | Display device |
| CN111726186A (en) * | 2019-03-20 | 2020-09-29 | 北京米文动力科技有限公司 | Synchronous configuration method of embedded chip and external equipment and embedded chip |
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| CN111568424B (en) * | 2020-05-26 | 2023-09-26 | 江苏省肿瘤医院 | Device for synchronizing respiratory motion signals in radiotherapy and application method thereof |
| CN113259888A (en) * | 2021-04-25 | 2021-08-13 | 黑芝麻智能科技(上海)有限公司 | Sensor configuration method and device, computer equipment and storage medium |
| CN113259888B (en) * | 2021-04-25 | 2024-04-30 | 黑芝麻智能科技(上海)有限公司 | Sensor configuration method, device, computer equipment and storage medium |
| CN114741343A (en) * | 2022-02-28 | 2022-07-12 | 惠州华阳通用电子有限公司 | Controller port expansion device and method |
| CN115017095A (en) * | 2022-08-05 | 2022-09-06 | 微传智能科技（常州）有限公司 | Current output type AK protocol wheel speed chip communication system and method |
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Effective date of registration: 20210401 Address after: 621000 building 31, No.7, Section 2, Xianren Road, Youxian District, Mianyang City, Sichuan Province Patentee after: China Ordnance Equipment Group Automation Research Institute Co.,Ltd. Address before: 621000 Mianyang province Sichuan City Youxian District Road No. 7 two immortals Patentee before: SICHUAN MIANYANG SOUTHWEST AUTOMATION INSTITUTE |