CN102866979B - Synchronous serial interface signal sensor data acquisition device - Google Patents
Synchronous serial interface signal sensor data acquisition device Download PDFInfo
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- CN102866979B CN102866979B CN201210323369.7A CN201210323369A CN102866979B CN 102866979 B CN102866979 B CN 102866979B CN 201210323369 A CN201210323369 A CN 201210323369A CN 102866979 B CN102866979 B CN 102866979B
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Abstract
The invention provides a synchronous serial interface (SSI) signal sensor data acquisition device, which comprises a digital signal processor (DSP) for an executable program, a serial port and controller area network (CAN) driver group module, an electrically erasable programmable read-only memory (EEPROM), a four-path-SSI driver group module and a two-row-needle type universal plugin, wherein control software for controlling an acquisition device to run is stored in a memory of the DSP. The device supplies various working mode options, such as a sampling rate, an SSI signal data acquisition port, the frequency of a synchronous clock signal and a data forwarding interface, to a user, and the user can select the working modes by collocating parameters on line in a manner that external parameter collocation equipment such as a personal computer and an embedded system is connected with a first serial port of a system to send an instruction according to a protocol; and an automatic judgment mechanism of the system can intelligently judge and process system collocation parameters sent by the user.
Description
Technical field
The invention belongs to data collector technical field, be specifically related to a kind of synchronous serial interface signal transducer data collector.
Background technology
Synchronous serial interface (Synchronous Serial Interface is called for short SSI) signal absolute value encoder is widely used in the technical fields such as numerically-controlled machine, mobile robot and photoelectric follow-up; The device carrying out gathering real-time and forwarding to SSI signal absolute value encoder data has become the key equipment in these fields.SSI initiatively sends the synchronizing clock signals of certain frequency by main equipment, realizes data transmission, have very strong transmittability and antijamming capability from equipment with most significant digit to the sequential synchronous transmission data of lowest order to the mode of main equipment.Existing SSI signal transducer data collector can achieve the sensor data acquisition of real-time multichannel SSI signal; But usually there is mode of operation fix single with data retransmission interface and do not possess the function of user's Configuration Online parameter.
As Chinese patent literature database discloses a kind of denomination of invention and be the patented claim technology of " a kind of peripheral component interconnection harvester of synchronous serial interface signal " (publication number is CN201020529373), this invention belong to SSI signal transducer data collecting field a kind of take FPGA module as the harvester of core, its technical characterstic is: using FPGA module as key control unit, one end is connected with SSI driving chip, and the other end is connected with pci bus through pci bridge chip.The other end of SSI driving chip is connected with four road SSI signal transducers, carries out gathering real-time simultaneously, be forwarded to industrial computer after collection through pci bus to four road SSI signal transducer data; Fixing mode of operation and single pci data forwarding interface limit the scope of application of device.
Summary of the invention
In order to meet embedded system to the diversity of SSI signal transducer data collector and dirigibility demand, the invention provides a kind of synchronous serial interface signal transducer data collector.
The technical solution used in the present invention is as follows:
Synchronous serial interface signal transducer data of the present invention the hardware of harvester of Configuration Online can comprise the dsp processor of executable program, serial ports and CAN driver bank module, erasable and programable memory EEPROM, four road SSI driver bank modules and double pin type general connector; Harvester with the dsp processor of executable program for core, the private communication interface of dsp processor and serial ports and CAN driver bank model calling, communicated with external parameter configuration device with the first serial in CAN driver bank module by serial ports, dsp processor receives the system configuration parameter of user, automatic decision mechanism carries out intelligent decision and process to user configured system configuration parameter, returns information; External reception equipment is forwarded to by second serial or CAN after the sensing data coding of the SSI signal gathered; The SPI interface of dsp processor is connected with erasable and programable memory EEPROM, automatically reads the system configuration parameter that the system configuration parameter be stored in erasable and programable memory EEPROM is stored in erasable and programable memory EEPROM with amendment; GPIOA and the GPIOB port of dsp processor and four road SSI driver bank model calling, the other end of four road SSI driver bank modules is connected with SSI signal transducer by four-wire system SSI signal wire; Produced the synchronizing clock signals of the frequency that user is arranged by the data register of software control GPIOA, read the data of the data register of GPIOB simultaneously chronologically, realize real time data Quick Acquisition.
The control software design run for controlling harvester is arranged in the storer of dsp processor, and control software design performs following steps:
CPU timer in a initialization dsp processor, GPIO, SCI, CAN and SPI module, the variable in initialization executable program, configuration and enable dsp processor in first serial;
The control cycle mark that b waiting for CPU timer produces is effective, if mark effectively, clear flag, proceeds to next step;
C judges that system configuration parameter modified logo is whether effective, if indicate invalid, proceeds to step e;
D when in step c, modified logo is effective, clear flag, reading system configuration parameter, GP configuring IO, SCI, CAN and SPI module, again to the initialization of variable in executable program;
E sample period counter adds one;
F judges whether sample counter meets limit value, if do not meet limit value, proceeds to step l;
G works as sample counter in step f and meets limit value, by counter O reset;
H judges that whether four road SSI signal data acquisition mouths are enable by selection, if all not enable by selection, proceeds to step l;
I is when there being SSI signal data acquisition mouth to be selected enable in step h, start the SSI signal data acquisition mouth be enabled, the data register corresponding positions of control GPIOA produces the synchronizing clock signals of the frequency that user is arranged, read the value of the data register corresponding positions of GPIOB chronologically simultaneously, displacement coding, is circulated to and gathers complete end;
J judges whether effectively second serial or CAN are selected as data retransmission interface, if invalid, proceed to step l;
K, when there being communication port to be selected as forwarding interface in step j, being encoded to image data according to selecting the agreement of communication port and sends, being sent end;
L judge first serial whether receive Data Labels effective, if invalid, proceed to step p;
M, when receiving Data Labels in step l and being effective, removes and receives Data Labels, decodes after reading data, and automatic decision mechanism judges that whether data are correct and rationally, if condition does not meet, the modified logo putting system configuration parameter is invalid, please proceed to step o;
N, when step m conditional meets, modifies to the system configuration parameter stored in erasable and programable memory EEPROM, and the modified logo of juxtaposition system configuration parameter is effective;
O returns information;
Effectively whether p judge to exit command, if effectively, and program determination, otherwise proceed to step b.
The present invention has following characteristics: 1. GPIO, SCI, CAN and SPI module made full use of on dsp processor sheet realizes the collection of SSI signal transducer data software control mode, data encoding and data retransmission, and system configuration parameter stores and modify feature, hardware configuration is simple; 2. user is connected by the external parameter such as personal computer or embedded system configuration device the mode Configuration Online parameter sending instruction with system first serial; 3. device provides multiple-working mode to select to use to user, the such as sampling rate of four different brackets, one or more SSI signal data acquisition mouth, the frequency of the synchronizing clock signals of five different frequencies, two data forwarding interfaces; 4. provide automatic decision mechanism, according to synchronizing clock signals frequency, serial ports and CAN communication baud rate are subject to the constraint condition of sampling rate and sensor figure place, carry out intelligent decision and process, and return information to user configured system configuration parameter.
Accompanying drawing explanation
Fig. 1 be of the present invention can the structural representation of synchronous serial interface signal transducer data collector of Configuration Online;
Fig. 2 be in the present invention can the synchronous serial interface signal transducer data collector core board schematic diagram of Configuration Online;
Fig. 3 be in the present invention can the program flow diagram of synchronous serial interface signal transducer data collector of Configuration Online.
Embodiment
Below in conjunction with drawings and Examples, the present invention is described in detail.
Fig. 1 be of the present invention can the structural representation of synchronous serial interface signal transducer data collector of Configuration Online.As shown in Figure 1, of the present inventionly the hardware module of synchronous serial interface signal transducer data collector 18 of Configuration Online can comprise the dsp processor 10 of executable program, serial ports and CAN driver bank module 11, erasable and programable memory EEPROM12, the main modular such as four road SSI driver bank modules 13 and double pin type general connector 14.Harvester with the dsp processor 10 of executable program for core; The private communication interface 110 of dsp processor 10 is connected with serial ports and CAN driver bank module 11, communicated with external parameter configuration device 15 with the first serial 111 in CAN driver bank module 11 by serial ports, receive user configured system configuration parameter, automatic decision mechanism carries out intelligent decision and process to user configured system configuration parameter, returns information; External reception equipment 17 is forwarded to by second serial 112 or CAN113 after SSI signal transducer 16 data encoding gathered; The SPI120 of dsp processor 10 is connected with erasable and programable memory EEPROM12, automatically reads the system configuration parameter that the system configuration parameter be stored in erasable and programable memory EEPROM12 is stored in erasable and programable memory EEPROM12 with amendment; GPIOA with GPIOB130 of dsp processor 10 is connected with four road SSI driver bank modules 13, and the other end of four road SSI driver bank modules 13 is connected with SSI signal transducer 16 by four-wire system SSI signal wire 131; First in the direction register of GPIOA, A12 ~ A15 pin is set to output interface, in the direction register of GPIOB, B12 ~ B15 pin is set to input interface; During data acquisition, the synchronizing clock signals that 1 and clear 0 produces the frequency that user is arranged is put to data register bit12, bit13, bit14, bit15 bit timing of GPIOA, reads the value of data register bit12, bit13, bit14, bit15 position of GPIOB simultaneously chronologically.Harvester adopts double pin type general connector 14 to be connected with outside, and user can select connected mode according to actual needs, and user uses more convenient and simple.
Fig. 2 be in the present invention can the synchronous serial interface signal transducer data collector core board schematic diagram of Configuration Online.As shown in Figure 2, DSP core control panel of the present invention adopts the TMS320F2812DSP processor 20 of the 150MHz dominant frequency of TI company to be core, be connected with two MAX2311 serial driver (21,22) and PCA82C250CAN driver 23 respectively by carrying private communication interface, on bonding pad, SCI and CAN module realize RS-232 serial ports and communicate with 2.0CAN.The erasable and programable memory EEPROM24 that dsp processor is X25650AF by CLK, SIMO of SPI and SOMI signal data line and model is connected, and reads and system configuration parameter in amendment erasable and programable memory EEPROM online.Be connected with the SSI driver (25,26,27,28) of four MAX490 by GPIOA with GPIOB, GPIOA is as synchronizing clock signals output interface, GPIOB is as Data Input Interface, according to SSI timing requirements, 12,13,14,15 pins in software operation GPADAT register control GPIOA produce the synchronous clock pulse signal of user configured frequency, and the GPBDAT register of 12,13,14,15 pins simultaneously read in GPIOA realizes the data acquisition of SSI signal transducer.Harvester is all realized by the double pin type general connector 29 of the DIP144-14-40-10 of 40 pins with outside all connection.
Fig. 3 be in the present invention can the program flow diagram of synchronous serial interface signal transducer data collector of Configuration Online.As shown in Figure 3, step 30 is system initialization, realizes the CPU timer to dsp processor, CAN, SCI, GPIO, SPI and the initialization of outside extended memory interface module, the variable in initialization executable program, configuration and enable first serial, time delay one second.First judge that whether control cycle mark is effective in step 31, mark is that the interrupt service routine produced by the CPU timer of two milliseconds is set to effectively, if it is invalid to be masked as, system wait mark is set to effectively, if be masked as effectively, clear flag enters step 32.Judge that whether configuration parameter modified logo is effective in the step 32, if modified logo is invalid, represents that the parameter of system cloud gray model is user configured system configuration parameter, then proceed to step 34; If modified logo is effectively, represent that user reconfigures systematic parameter and this parameter does not also configure to system, dsp processor will read parameter configuration to system in erasable and programable memory EEPROM in step 33, remove configuration parameter modified logo.In step 34 sample period counter is added one.In step 35, compared by sample period counter with the sampling period parameter that user is arranged, if counter is less than sampling period parameter, counter meets restriction and is masked as invalid, then proceed to step 37; If counter is equal with sampling period parameter, counter meets restriction and is masked as effectively, then proceed to step 36.
In step 36, sample counter is reset.In step 361, judge that whether the first acquisition port is enable by selection, if not enable by selection, then proceed to step 362; If enable by selection, in step 3611, by software timing, the value of the bit12 position of the data register of GPIOA is composed 1 or clear 0, produce the synchronizing clock signals of the frequency that user is arranged, read the value of the bit12 position of the data register of GPIOB chronologically simultaneously, displacement coding, be circulated to data acquisition complete, proceed to step 362.In step 362, judge that whether the second acquisition port is enable by selection, if not enable by selection, then proceed to step 363; If enable by selection, in step 3621, by software timing, the value of the bit13 position of the data register of GPIOA is composed 1 or clear 0, produce the synchronizing clock signals of the frequency that user is arranged, read the value of the bit13 position of the data register of GPIOB chronologically simultaneously, displacement coding, be circulated to data acquisition complete, proceed to step 363.In step 363, judge that whether the 3rd acquisition port is enable by selection, if not enable by selection, then proceed to step 364; If enable by selection, in step 3631, by software timing, the value of the bit14 position of the data register of GPIOA is composed 1 or clear 0, produce the synchronizing clock signals of the frequency that user is arranged, read the value of the bit14 position of the data register of GPIOB chronologically simultaneously, displacement coding, be circulated to data acquisition complete, proceed to step 364.In step 364, judge that whether the 4th acquisition port is enable by selection, if not enable by selection, then proceed to step 365; If enable by selection, in step 3641, by software timing, the value of the bit15 position of the data register of GPIOA is composed 1 or clear 0, produce the synchronizing clock signals of the frequency that user is arranged, read the value of the bit15 position of the data register of GPIOB chronologically simultaneously, displacement coding, be circulated to data acquisition complete, proceed to step 365.In step 365, judge whether second serial is selected as data and sends mouth, if do not selected, then proceeds to step 3652; Send mouth if be selected as, the data of collection encoded according to serial communication protocol and sends, being sent, proceeding to step 37.In step 3652, judge whether CAN is selected as data and sends mouth, if do not selected, then proceeds to step 37; Send mouth if be selected as, the data of collection are sent according to CAN communication protocol code, is sent, proceeds to step 37.
In step 37, whether effective first judge in first serial buffer zone, to receive Data Labels, if it is invalid for receiving Data Labels, then proceed to step 38; If it is effective for receiving Data Labels, indicate that serial data is received and not processed, remove in step 371 and receive Data Labels, receive and press protocol analysis data.In step 372, automatic decision mechanism judges that whether data are correct and reasonable, if data are incorrect or irrational, are set to invalid and proceed to step 373 by amendment parameter flag; If data are correct and reasonably, it is effective for revising system configuration parameter juxtaposition configuration parameter modified logo in erasable and programable memory EEPROM in step 3721, after proceed to step 373.Amendment parameter flag information is sent in step 373.
Whether effective in step 38 determining program exit instruction, if effectively, then EOP (end of program), otherwise proceed to step 31.
The primitive rule of the automatic decision mechanism in the present invention is: the synchronizing clock signals of low frequency and baud rate are only for low-frequency sampling rate system, and high frequency sampling rate system can only select CAN as data output interface.
Claims (2)
1. a synchronous serial interface signal transducer data collector, it is characterized in that: described harvester comprises the dsp processor of executable program (10), serial ports and CAN driver bank module (11), erasable and programable memory EEPROM(12), four roads SSI driver bank module (13) and double pin type general connector (14); Harvester with the dsp processor of executable program for core, the private communication interface (110) of dsp processor is connected with serial ports and CAN driver bank module (11), communicated with external parameter configuration device with the first serial (111) in CAN driver bank module (11) by serial ports, dsp processor receives the system configuration parameter of user, automatic decision mechanism carries out intelligent decision and process to user configured system configuration parameter, returns information; External reception equipment is forwarded to by second serial (112) or CAN(113) after the sensing data coding of the SSI signal gathered; SPI interface (120) and the erasable and programable memory EEPROM(12 of dsp processor) be connected, automatically read and be stored in erasable and programable memory EEPROM(12) in system configuration parameter and amendment be stored in erasable and programable memory EEPROM(12) in system configuration parameter; GPIOA with the GPIOB port (130) of dsp processor (10) is connected with four roads SSI driver bank module (13), and the other end on four roads SSI driver bank module (13) is connected with SSI signal transducer by four-wire system SSI signal wire (131); Produced the synchronizing clock signals of the frequency that user is arranged by the data register of software control GPIOA, read the data of the data register of GPIOB simultaneously chronologically, realize real time data Quick Acquisition; The control software design run for controlling harvester is stored in the storer of dsp processor (10);
Described automatic decision mechanism refers to that the synchronizing clock signals of low frequency and baud rate are only for low-frequency sampling rate system, and high frequency sampling rate system can only select CAN as data output interface.
2. harvester according to claim 1, is characterized in that: the software in the dsp processor of described harvester board comprises the following steps:
CPU timer in a initialization dsp processor, GPIO, SCI, CAN and SPI module, the variable in initialization executable program, configuration and enable dsp processor in first serial;
The control cycle mark that b waiting for CPU timer produces is effective, if mark effectively, clear flag, proceeds to next step;
C judges that system configuration parameter modified logo is whether effective, if indicate invalid, proceeds to step e;
D when in step c, modified logo is effective, clear flag, reading system configuration parameter, GP configuring IO, SCI, CAN and SPI module, again to the initialization of variable in executable program;
E sample period counter adds one;
F judges whether sample counter meets limit value, if do not meet limit value, proceeds to step l;
G works as sample counter in step f and meets limit value, by counter O reset;
H judges that whether four road SSI signal data acquisition mouths are enable by selection, if all not enable by selection, proceeds to step l;
I is when there being SSI signal data acquisition mouth to be selected enable in step h, start the SSI signal data acquisition mouth be enabled, the data register corresponding positions of control GPIOA produces the synchronizing clock signals of the frequency that user is arranged, read the value of the data register corresponding positions of GPIOB chronologically simultaneously, displacement coding, is circulated to and gathers complete end;
J judges whether effectively second serial or CAN are selected as data retransmission interface, if invalid, proceed to step l;
K, when there being communication port to be selected as forwarding interface in step j, being encoded to image data according to selecting the agreement of communication port and sends, being sent end;
L judge first serial whether receive Data Labels effective, if invalid, proceed to step p;
M, when receiving Data Labels in step l and being effective, removes and receives Data Labels, decodes after reading data, and automatic decision mechanism judges that whether data are correct and rationally, if condition does not meet, the modified logo putting system configuration parameter is invalid, please proceed to step o;
N, when step m conditional meets, modifies to the system configuration parameter stored in erasable and programable memory EEPROM, and the modified logo of juxtaposition system configuration parameter is effective;
O returns information;
Effectively whether p judge to exit command, if effectively, and program determination, otherwise proceed to step b.
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| CN108111426B (en) * | 2017-12-14 | 2021-06-08 | 迈普通信技术股份有限公司 | Communication device with synchronous serial port, synchronous serial port bandwidth synchronization system and method |
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| CN111726186B (en) * | 2019-03-20 | 2022-09-09 | 北京米文动力科技有限公司 | Synchronous configuration method of embedded chip and external equipment and embedded chip |
| CN111568424B (en) * | 2020-05-26 | 2023-09-26 | 江苏省肿瘤医院 | Device for synchronizing respiratory motion signals in radiotherapy and application method thereof |
| CN113259888B (en) * | 2021-04-25 | 2024-04-30 | 黑芝麻智能科技(上海)有限公司 | Sensor configuration method, device, computer equipment and storage medium |
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Effective date of registration: 20210401 Address after: 621000 building 31, No.7, Section 2, Xianren Road, Youxian District, Mianyang City, Sichuan Province Patentee after: China Ordnance Equipment Group Automation Research Institute Co.,Ltd. Address before: 621000 Mianyang province Sichuan City Youxian District Road No. 7 two immortals Patentee before: SICHUAN MIANYANG SOUTHWEST AUTOMATION INSTITUTE |