CN104485325A - Structure for reducing warpage of wafer-level integrated passive device and manufacturing method - Google Patents
Structure for reducing warpage of wafer-level integrated passive device and manufacturing method Download PDFInfo
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- CN104485325A CN104485325A CN201410758727.6A CN201410758727A CN104485325A CN 104485325 A CN104485325 A CN 104485325A CN 201410758727 A CN201410758727 A CN 201410758727A CN 104485325 A CN104485325 A CN 104485325A
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Abstract
The invention relates to a structure for reducing warpage of a wafer-level integrated passive device and a manufacturing method. The structure comprises a first metal layer and a second metal layer; the second metal layer is positioned on the upper layer of the first metal layer; the second metal layer is of a spiral coil structure; the first metal layer is a bridge wire for connecting the inside and the outside of a coil. The structure is characterized in that an insulating layer is arranged in a region where the first metal layer and the second metal layer are mutually overlapped. The manufacturing method comprises the following steps: (1) manufacturing the first metal layer on a wafer; (2) coating a photosensitive organic polymer on the integral wafer, making a through hole, removing the photosensitive organic polymer, retaining the photosensitive organic polymer in the region where the first metal layer is positioned and curing; (3) manufacturing the second metal layer and enabling the overlapped region between the second metal layer and the first metal layer to be overlapped with the insulating layer. According to the structure for reducing warpage of the wafer-level integrated passive device and the manufacturing method, the problem of warpage of the wafer, which is caused by an organic medium layer, is improved.
Description
Technical field
The present invention relates to a kind of structure and the manufacture method that reduce wafer level integrated passive devices warpage, belong to the wafer level integrated technology field of passive device.
Background technology
Traditional passive device adopts discrete encapsulation, only comprises an electronic component in an encapsulation.This packing forms cannot meet growing low cost, the demand of high integration, and therefore integrated passive devices is developed rapidly.Utilizing thin film technique on disk, make integrated passive devices is the potential integrated passive devices production program of a kind of tool.
Organic polymer (as polyimides, BCB(benzocyclobutene) etc.) due to low cost, technical maturity, the advantages such as good electric performance, can be used as the dielectric layer of integrated passive devices.The scheme of traditional making organic dielectrics is, applies a flood organic media in disk surfaces, and on this layer of organic dielectric layer, makes through hole by schemes such as etching or photoetching, realizes the interconnection between the upper and lower double layer of metal of dielectric layer.But, because the thermal coefficient of expansion CTE(of organic polymer is as BCB 42ppm/ DEG C) with backing material (as silicon 3.2ppm/ DEG C, laminated material 15 ~ 17ppm/ DEG C) thermal coefficient of expansion gap excessive, in process due to photoetching, in the intensification temperature-fall period of the techniques such as solidification, often there is larger thermal stress, cause disk warpage, affect craft precision, and integrity problem served by band, affects rate of finished products.
Summary of the invention
The object of the invention is to overcome the deficiencies in the prior art, a kind of structure and the manufacture method that reduce wafer level integrated passive devices warpage are provided, by reducing organic dielectric layer area coverage, improve the problem of the disk warpage caused due to organic dielectric layer occurred in technique.
According to technical scheme provided by the invention, the structure of described reduction wafer level integrated passive devices warpage, comprise and be arranged on first layer metal layer on disk and second layer metal layer, second layer metal layer is positioned at the upper strata of first layer metal layer, and second layer metal layer is for being arranged in the spiral wire coil structures of disk surfaces; One end of described first layer metal layer is positioned at the inner ring of second layer metal layer line circle, and the other end of first layer metal layer is positioned at the outer ring of second layer metal layer line circle, and first layer metal layer forms the bridge line connected inside and outside second layer metal layer line circle; It is characterized in that: between described first layer metal layer and second layer metal layer, mutually overlapping region arranges insulating barrier, insulating barrier covers first layer metal layer region, isolates the overlapping part of bridge line and coil.
Further, the flat shape of described insulating barrier is round rectangle.
Further, described first layer metal layer is connected by the through hole be arranged on disk with second layer metal layer.
The manufacture method of described reduction wafer level integrated passive devices warped structures, is characterized in that, comprise the following steps:
(1) on disk, first layer metal layer is made, as the bridge line connected inside and outside inductance coil;
(2) on whole disk, apply photosensitive organic polymer, make by photoetching or etching technics the through hole connecting first layer metal layer and second layer metal layer; Get rid of photosensitive organic polymer, retain the photosensitive organic polymer of first layer metal layer region, form insulating barrier, insulating barrier is cured;
(3) on disk, make second layer metal layer, the overlapping region between second layer metal layer and first layer metal layer and insulating barrier overlap, and first layer metal layer and second layer metal layer are realized isolation by insulating barrier.
Further, described photosensitive organic polymer adopts BCB material.
The present invention has the following advantages: (1) area of the present invention significantly reduces, and the organic media area on whole disk can be reduced to original less than 30%; (2) be conducive to reducing the stress of dielectric layer and the warpage that causes thereof, make the crackle that occurs in flow process or other integrity problems can not spread to whole disk simultaneously, thus effectively improve rate of finished products under the prerequisite not increasing cost.
Accompanying drawing explanation
Fig. 1 is structural representation of the present invention.
Sequence number in figure: first layer metal layer 101, photosensitive bcb layer 102, insulating barrier 103, second layer metal layer 104.
Embodiment
Below in conjunction with concrete accompanying drawing, the invention will be further described.
As shown in Figure 1: the structure of described reduction wafer level integrated passive devices warpage, comprise and be arranged on first layer metal layer 101 on disk and second layer metal layer 104, second layer metal layer 104 is positioned at the upper strata of first layer metal layer 101, and second layer metal layer 104 is for being arranged in the spiral wire coil structures of disk surfaces; One end of described first layer metal layer 101 is positioned at the inner ring of second layer metal layer 104 coil, the other end of first layer metal layer 101 is positioned at the outer ring of second layer metal layer 104 coil, thus first layer metal layer 101 forms the bridge line connected inside and outside second layer metal layer 104 coil; Between described first layer metal layer 101 and second layer metal layer 104, mutually overlapping region arranges insulating barrier 103, and insulating barrier 103 covers first layer metal layer 101 region, and insulating barrier 103 is in order to isolate the overlapping part of bridge line and coil;
The flat shape of described insulating barrier 103 is round rectangle, adopts fillet to reduce stress concentration point;
Described first layer metal layer 101 is connected by the through hole be arranged on disk with second layer metal layer 104.
The manufacture method of described reduction wafer level integrated passive devices warped structures, comprises the following steps:
(1) adopt photoetching electroplating technology on disk, form first layer metal layer 101, as the bridge line connected inside and outside inductance coil;
(2) on whole disk, apply photosensitive BCB material 102, form by photoetching or etching technics the through hole connecting first layer metal layer 101 and second layer metal layer 104; And get rid of BCB material by exposure imaging, retain the BCB material of first layer metal layer 101 region, form insulating barrier 103, the BCB material of insulating barrier 103 is cured;
(3) on disk, second layer metal layer 104 is made by photoetching electroplating technology, overlapping region between second layer metal layer 104 and first layer metal layer 101 and insulating barrier 103 overlap, thus first layer metal layer 101 and second layer metal layer 104 are realized isolation by insulating barrier 103, first layer metal layer 101, insulating barrier 103 and second layer metal layer 104 constitute planar coil inductance jointly.
The insulating barrier 103 that the present invention adopts covers first layer metal layer 101 and the mutually overlapping region of second layer metal layer 104, the insulating barrier of relative traditional handicraft median-plane inductance covers the method for the whole disk except through hole, area of the present invention significantly reduces, organic media area on whole disk can be reduced to original less than 30%, be conducive to the stress reducing dielectric layer and the warpage caused thereof, make the crackle that occurs in flow process or other integrity problems can not spread to whole disk simultaneously, thus effectively rate of finished products is improved under the prerequisite not increasing cost.
Claims (5)
1. one kind reduces the structure of wafer level integrated passive devices warpage, comprise and be arranged on first layer metal layer (101) on disk and second layer metal layer (104), second layer metal layer (104) is positioned at the upper strata of first layer metal layer (101), and second layer metal layer (104) is for being arranged in the spiral wire coil structures of disk surfaces; One end of described first layer metal layer (101) is positioned at the inner ring of second layer metal layer (104) coil, the other end of first layer metal layer (101) is positioned at the outer ring of second layer metal layer (104) coil, and first layer metal layer (101) forms the bridge line connected inside and outside second layer metal layer (104) coil; It is characterized in that: between described first layer metal layer (101) and second layer metal layer (104), mutually overlapping region arranges insulating barrier (103), insulating barrier (103) covers first layer metal layer (101) region, isolates the overlapping part of bridge line and coil.
2. the structure reducing wafer level integrated passive devices warpage as claimed in claim 1, is characterized in that: the flat shape of described insulating barrier (103) is round rectangle.
3. the structure reducing wafer level integrated passive devices warpage as claimed in claim 1, is characterized in that: described first layer metal layer (101) is connected by the through hole be arranged on disk with second layer metal layer (104).
4. reduce a manufacture method for wafer level integrated passive devices warped structures, it is characterized in that, comprise the following steps:
(1) on disk, first layer metal layer (101) is made, as the bridge line connected inside and outside inductance coil;
(2) on whole disk, apply photosensitive organic polymer (102), make by photoetching or etching technics the through hole connecting first layer metal layer (101) and second layer metal layer (104); Get rid of photosensitive organic polymer, retain the photosensitive organic polymer of first layer metal layer (101) region, form insulating barrier (103), insulating barrier (103) is cured;
(3) on disk, make second layer metal layer (104), overlapping region between second layer metal layer (104) and first layer metal layer (101) and insulating barrier (103) overlap, and first layer metal layer (101) and second layer metal layer (104) are realized isolation by insulating barrier (103).
5. the manufacture method reducing wafer level integrated passive devices warped structures as claimed in claim 4, is characterized in that: described photosensitive organic polymer adopts BCB material.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN201410758727.6A CN104485325A (en) | 2014-12-11 | 2014-12-11 | Structure for reducing warpage of wafer-level integrated passive device and manufacturing method |
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| CN201410758727.6A CN104485325A (en) | 2014-12-11 | 2014-12-11 | Structure for reducing warpage of wafer-level integrated passive device and manufacturing method |
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| CN104485325A true CN104485325A (en) | 2015-04-01 |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US10283249B2 (en) | 2016-09-30 | 2019-05-07 | International Business Machines Corporation | Method for fabricating a magnetic material stack |
| US10304603B2 (en) | 2016-06-29 | 2019-05-28 | International Business Machines Corporation | Stress control in magnetic inductor stacks |
| US10811177B2 (en) | 2016-06-30 | 2020-10-20 | International Business Machines Corporation | Stress control in magnetic inductor stacks |
| CN115732165A (en) * | 2022-11-24 | 2023-03-03 | 昆山联滔电子有限公司 | Multi-coil structure, manufacturing method thereof and electronic device with same |
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| US5307045A (en) * | 1989-12-28 | 1994-04-26 | Murata Manufacturing Co., Ltd. | High-frequency inductor and manufacturing method thereof |
| US5922514A (en) * | 1997-09-17 | 1999-07-13 | Dale Electronics, Inc. | Thick film low value high frequency inductor, and method of making the same |
| CN1431709A (en) * | 2001-12-14 | 2003-07-23 | 富士通株式会社 | Electronic device |
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2014
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5307045A (en) * | 1989-12-28 | 1994-04-26 | Murata Manufacturing Co., Ltd. | High-frequency inductor and manufacturing method thereof |
| US5922514A (en) * | 1997-09-17 | 1999-07-13 | Dale Electronics, Inc. | Thick film low value high frequency inductor, and method of making the same |
| CN1431709A (en) * | 2001-12-14 | 2003-07-23 | 富士通株式会社 | Electronic device |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US10304603B2 (en) | 2016-06-29 | 2019-05-28 | International Business Machines Corporation | Stress control in magnetic inductor stacks |
| US10573444B2 (en) | 2016-06-29 | 2020-02-25 | International Business Machines Corporation | Stress control in magnetic inductor stacks |
| US10811177B2 (en) | 2016-06-30 | 2020-10-20 | International Business Machines Corporation | Stress control in magnetic inductor stacks |
| US10283249B2 (en) | 2016-09-30 | 2019-05-07 | International Business Machines Corporation | Method for fabricating a magnetic material stack |
| US10943732B2 (en) | 2016-09-30 | 2021-03-09 | International Business Machines Corporation | Magnetic material stack and magnetic inductor structure fabricated with surface roughness control |
| US11205541B2 (en) | 2016-09-30 | 2021-12-21 | International Business Machines Corporation | Method for fabricating a magnetic material stack |
| CN115732165A (en) * | 2022-11-24 | 2023-03-03 | 昆山联滔电子有限公司 | Multi-coil structure, manufacturing method thereof and electronic device with same |
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Application publication date: 20150401 |